7). 196Mx's ROM type CPU
In 196Mx's ROM type CPU, some addresses have been moved.
 CPU register name  Old address           EasyPack support name  New address
 CPU:P3_REG:           1FFCH      ------->   EP:P3_REG:           FFFCH
 CPU:P4_REG:           1FFDH      ------->   EP:P4_REG:           FFFDH
 CPU:P3_PIN:           1FFEH      ------->   EP:P3_PIN:           FFFEH
 CPU:P4_PIN:           1FFFH      ------->   EP:P4_PIN:           FFFFH
 CPU:P5_REG:           1FF5H      ------->   EP:P5_REG:           FFF5H
 CPU:P5_PIN:           1FF7H      ------->   EP:P5_PIN:           FFF7H
 CPU:P5_MODE:          1FF1H      ------->   EP:P5_MODE:          FFF1H
 CPU:P5_DIR:           1FF3H      ------->   EP:P5_DIR:           FFF3H
For examples: When user wants to write a data to the CPU:P3_REG(1FFCH), user
shall modify his/her program: to write the data to EP:P3_REG(FFFCH)

8) About P5_MODE,P5_DIR
The register EP:P5_MODE(FFF1H) and EP:P5_DIR(FFF3H) do not function really.
These values are only for show.
In user's program, User shall not change the registers: CPU:P5_MODE(1FF1) and
CPU:P5_DIR  (1FF3H).

9) About WDE bit in the CCR1
The WDE(Watch timer enable) is forced to function:  "1 = enabled first time
it is cleared"