//defined the register id seq
typedef enum {
/*   0       1         2       3          4       5       6       7  */
   R_PC,    R_ACC,   R_B,     R_PSW,    R_PSW1,  R_SP,    R_SPH,   R_DPL,
   R_DPH,   R_DPXL,  R_PCON,  R_IE0,    R_IPH0,  R_IPL0,  R_WCON   R_P0,
   R_P1,    R_P2,    R_P3,    R_SCON,   R_SBUF,  R_SADEN, R_SADDR, R_TL0,
   R_TH0,   R_TL1,   R_TH1,   R_TL2,    R_TH2,   R_TCON,  R_TMOD,  R_T2CON,
   R_T2MOD, R_RCAP2L,R_RCAP2H,R_WDTRST, R_CCON,  R_CMOD,  R_CCAPM0,R_CCAPM1,
   R_CCAPM2,R_CCAPM3,R_CCAPM4,R_CL,R_CH,R_CCAP0L,R_CCAP1L,R_CCAP2L,
   MAX_CPU_REG_NO
}CPU_REGISTER;

typedef enum {
/*  0        1       2       3       4        5        6        7  */
   NR_0,   NR_1,   NR_2,   NR_3,    NR_4     NR_5,    NR_6,    NR_7,
   NR_8,   NR_9,   NR_10,  NR_11,   NR_12,   NR_13,   NR_14    NR_15,
   NR_WR16,NR_WR18,NR_WR20,NR_ WR22,NR_ WR24,NR_ WR26,NR_ WR28,NR_ WR30,
   NR_ DR0,NR_DR4, NR_DR56,NR_DR60,
   MAX_NORMAL_REG_NO
}NORMAL_REGISTER;