Project Information                                           c:\ovrm\ovrm.rpt

MAX+plus II Compiler Report File
Version 6.1 02/28/96
Compiled: 06/03/96 11:21:11

Copyright (c) 1996 by Altera Corporation.  All rights reserved.  This text
contains proprietary, confidential information of Altera Corporation, and
may be used, copied, and/or disclosed only pursuant to the terms of a
valid software license agreement with Altera Corporation.  This copyright
notice must be retained as part of this text at all times.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

OVRM      EPM7064LC84-10   32       25       8      41      8           64 %

User Pins:                 32       25       8  



Project Information                                           c:\ovrm\ovrm.rpt

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

OVRM@57                           CEMA17
OVRM@9                            CPA4
OVRM@37                           CPD0
OVRM@39                           CPD1
OVRM@56                           CPD2
OVRM@55                           CPD3
OVRM@54                           CPD4
OVRM@41                           CPD5
OVRM@40                           CPD6
OVRM@68                           CPD7
OVRM@18                           CPS8
OVRM@22                           CPS9
OVRM@74                           DIR
OVRM@63                           EA16
OVRM@46                           EA17
OVRM@25                           EA18
OVRM@27                           EA19
OVRM@65                           EA20
OVRM@4                            EMUSPACE
OVRM@36                           INHIMAP
OVRM@34                           MAPCOVSEL
OVRM@79                           MD0
OVRM@77                           MD8
OVRM@23                           NBPBUS0
OVRM@11                           NBPBUS1
OVRM@84                           NCOVSELG
OVRM@21                           NCPCS8
OVRM@76                           NEMRD0
OVRM@73                           NEMRD1
OVRM@16                           NEMVALID
OVRM@8                            NENEM
OVRM@71                           NENEMBH
OVRM@70                           NENEMBL
OVRM@28                           NENMAP
OVRM@52                           NEN1M0
OVRM@45                           NEN1M1
OVRM@58                           NEN2M0
OVRM@62                           NEN2M1
OVRM@61                           NEN2M2
OVRM@60                           NEN2M3
OVRM@69                           NEN8B
OVRM@50                           NEN512K0
OVRM@48                           NEN512K1
OVRM@6                            NERD
OVRM@51                           NEWE
OVRM@30                           NGUARD
OVRM@12                           NMAX8M
OVRM@31                           NMBEN0
OVRM@49                           NMBEN1
OVRM@75                           NMCS2L
OVRM@83                           NMEMRQ
OVRM@2                            NRDOEG
OVRM@35                           NRDOEOUT
OVRM@10                           NRDONLY
OVRM@20                           NRESET
OVRM@15                           NSTROBE
OVRM@33                           NVIOLBRK
OVRM@64                           NWE0
OVRM@67                           NWE1
OVRM@5                            N1MVLD
OVRM@1                            N2MVLD0
OVRM@14                           N2MVLD1
OVRM@29                           N512KVLD
OVRM@24                           RESERVE
OVRM@17                           SEL8


Project Information                                           c:\ovrm\ovrm.rpt

** FILE HIERARCHY **



|7474:U57|
|7474:U147|
|7474:U148|
|7474:U149|
|7474:U159|
|7474:U163|


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

***** Logic for device 'OVRM' compiled without errors.




Device: EPM7064LC84-10
Turbo: ON
Security: OFF


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** ERROR SUMMARY **

Info: Chip 'OVRM' in device 'EPM7064LC84-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                                              
                                    E           N        R  R                 
               N  N                 M        N  C        E  E                 
               B  R              N  U     N  2  O  N     S  S           N  N  
               P  D     N        1  S     R  M  V  M     E  E           E  M  
               B  O  C  E     N  M  P     D  V  S  E     R  R           M  C  
               U  N  P  N  G  E  V  A  V  O  L  E  M  G  V  V  M  V  M  R  S  
               S  L  A  E  N  R  L  C  C  E  D  L  R  N  E  E  D  C  D  D  2  
               1  Y  4  M  D  D  D  E  C  G  0  G  Q  D  D  D  0  C  8  0  L  
             -----------------------------------------------------------------_ 
           /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
   NMAX8M | 12                                                              74 | DIR 
      VCC | 13                                                              73 | NEMRD1 
  N2MVLD1 | 14                                                              72 | GND 
  NSTROBE | 15                                                              71 | NENEMBH 
 NEMVALID | 16                                                              70 | NENEMBL 
     SEL8 | 17                                                              69 | NEN8B 
     CPS8 | 18                                                              68 | CPD7 
      GND | 19                                                              67 | NWE1 
   NRESET | 20                                                              66 | VCC 
   NCPCS8 | 21                                                              65 | EA20 
     CPS9 | 22                        EPM7064LC84-10                        64 | NWE0 
  NBPBUS0 | 23                                                              63 | EA16 
  RESERVE | 24                                                              62 | NEN2M1 
     EA18 | 25                                                              61 | NEN2M2 
      VCC | 26                                                              60 | NEN2M3 
     EA19 | 27                                                              59 | GND 
   NENMAP | 28                                                              58 | NEN2M0 
 N512KVLD | 29                                                              57 | CEMA17 
   NGUARD | 30                                                              56 | CPD2 
   NMBEN0 | 31                                                              55 | CPD3 
      GND | 32                                                              54 | CPD4 
          |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
            ------------------------------------------------------------------ 
               N  M  N  I  C  V  C  C  C  G  V  R  N  E  G  N  N  N  N  N  V  
               V  A  R  N  P  C  P  P  P  N  C  E  E  A  N  E  M  E  E  E  C  
               I  P  D  H  D  C  D  D  D  D  C  S  N  1  D  N  B  N  W  N  C  
               O  C  O  I  0     1  6  5        E  1  7     5  E  5  E  1     
               L  O  E  M                       R  M        1  N  1     M     
               B  V  O  A                       V  1        2  1  2     0     
               R  S  U  P                       E           K     K           
               K  E  T                          D           1     0           
                  L                                                           


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)  16/16(100%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32    14/16( 87%)  16/16(100%)   2/16( 12%)  18/36( 50%) 
C:    LC33 - LC48    12/16( 75%)  15/16( 93%)   4/16( 25%)  11/36( 30%) 
D:    LC49 - LC64    15/16( 93%)  14/16( 87%)   5/16( 31%)  26/36( 72%) 


Total dedicated input pins used:                 4/4    (100%)
Total I/O pins used:                            61/64   ( 95%)
Total logic cells used:                         41/64   ( 64%)
Total shareable expanders used:                  8/64   ( 12%)
Total Turbo logic cells used:                   41/64   ( 64%)
Total shareable expanders not available (n/a):   3/64   (  4%)

Total input pins required:                      32
Total output pins required:                     25
Total bidirectional pins required:               8
Total logic cells required:                     41
Total flipflops required:                       12
Total shareable expanders in database:           7

Synthesized logic cells:                         0/  64 (  0%)



Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   9   (12)  (A)      INPUT              0      0   0    0    0    4    6  CPA4
  37     20    B      BIDIR              0      0   0    3    2    1    1  CPD0
  39     19    B      BIDIR              0      0   0    2    1    1    0  CPD1
  56     43    C      BIDIR              0      0   0    3    0    1    0  CPD2
  55     42    C      BIDIR              0      0   0    3    0    0    1  CPD3
  54     41    C      BIDIR              0      0   0    3    0    1    0  CPD4
  41     17    B      BIDIR              0      0   0    4    1    0    1  CPD5
  40     18    B      BIDIR              0      0   0    3    0    0    3  CPD6
  68     53    D      BIDIR              0      0   0    0    0    0    3  CPD7
  18    (4)  (A)      INPUT              0      0   0    0    0    6    6  CPS8
  22    (1)  (A)      INPUT              0      0   0    0    0   11    0  CPS9
  63   (49)  (D)      INPUT              0      0   0    0    0    8    0  EA16
  46   (35)  (C)      INPUT              0      0   0    0    0    9    0  EA17
  25   (30)  (B)      INPUT              0      0   0    0    0    8    0  EA18
  27   (29)  (B)      INPUT              0      0   0    0    0    8    0  EA19
  65   (51)  (D)      INPUT              0      0   0    0    0    8    0  EA20
   4   (16)  (A)      INPUT              0      0   0    0    0    5    2  EMUSPACE
  23   (32)  (B)      INPUT              0      0   0    0    0    3    0  NBPBUS0
  11   (10)  (A)      INPUT              0      0   0    0    0    3    0  NBPBUS1
  84      -   -       INPUT              0      0   0    0    0    0    0  NCOVSELG (U155)
  21    (2)  (A)      INPUT              0      0   0    0    0   12    6  NCPCS8
  16    (6)  (A)      INPUT              0      0   0    0    0    2    2  NEMVALID
   8   (13)  (A)      INPUT              0      0   0    0    0    5    0  NENEM
   6   (14)  (A)      INPUT              0      0   0    0    0    5    0  NERD
  51   (39)  (C)      INPUT              0      0   0    0    0    2    1  NEWE
  30   (26)  (B)      INPUT              0      0   0    0    0    0    1  NGUARD
  12    (9)  (A)      INPUT              0      0   0    0    0   10    0  NMAX8M
  31   (25)  (B)      INPUT              0      0   0    0    0    2    0  NMBEN0
  49   (37)  (C)      INPUT              0      0   0    0    0    3    0  NMBEN1
  75   (59)  (D)      INPUT              0      0   0    0    0    3    0  NMCS2L
  83      -   -       INPUT              0      0   0    0    0    5    2  NMEMRQ
   2      -   -       INPUT              0      0   0    0    0    0    0  NRDOEG (U154)
  10   (11)  (A)      INPUT              0      0   0    0    0    2    1  NRDONLY
  20    (3)  (A)      INPUT              0      0   0    0    0    4    8  NRESET
  15    (7)  (A)      INPUT              0      0   0    0    0    3    0  NSTROBE
   5   (15)  (A)      INPUT              0      0   0    0    0    9    0  N1MVLD
   1      -   -       INPUT              0      0   0    0    0    9    0  N2MVLD0
  14    (8)  (A)      INPUT              0      0   0    0    0    9    0  N2MVLD1
  29   (27)  (B)      INPUT              0      0   0    0    0    1    0  N512KVLD
  17    (5)  (A)      INPUT              0      0   0    0    0    2    0  SEL8


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  57     44    C     OUTPUT     t        0      0   0    2    0    0    0  CEMA17
  37     20    B        TRI     t        0      0   0    3    2    1    1  CPD0
  39     19    B        TRI     t        0      0   0    2    1    1    0  CPD1
  56     43    C        TRI     t        0      0   0    3    0    1    0  CPD2
  55     42    C        TRI     t        0      0   0    3    0    0    1  CPD3
  54     41    C        TRI     t        0      0   0    3    0    1    0  CPD4
  41     17    B        TRI     t        0      0   0    4    1    0    1  CPD5
  40     18    B        TRI     t        0      0   0    3    0    0    3  CPD6
  68     53    D        TRI     t        0      0   0    0    0    0    3  CPD7
  74     58    D     OUTPUT     t        0      0   0    2    1    0    0  DIR
  36     21    B         FF     t        1      1   0    4    1    0    0  INHIMAP (|7474:U147|:10)
  34     23    B         FF     t        1      1   0    4    1    5    0  MAPCOVSEL (|7474:U148|:9)
  79     62    D        TRI     t        0      0   0    0    0    0    0  MD0
  77     61    D        TRI     t        0      0   0    0    0    0    0  MD8
  76     60    D     OUTPUT     t        0      0   0    2    1    0    0  NEMRD0
  73     57    D     OUTPUT     t        0      0   0    2    1    0    0  NEMRD1
  71     56    D     OUTPUT     t        0      0   0    7    3    0    0  NENEMBH
  70     55    D     OUTPUT     t        0      0   0    6    3    0    0  NENEMBL
  28     28    B         FF     t        1      1   0    4    1    0    0  NENMAP (|7474:U149|:9)
  52     40    C     OUTPUT     t        2      2   0    9    0    0    0  NEN1M0
  45     34    C     OUTPUT     t        2      2   0    9    0    0    0  NEN1M1
  58     45    C     OUTPUT     t        0      0   0    9    0    0    0  NEN2M0
  62     48    C     OUTPUT     t        0      0   0    9    0    0    0  NEN2M1
  61     47    C     OUTPUT     t        0      0   0    9    0    0    0  NEN2M2
  60     46    C     OUTPUT     t        0      0   0    9    0    0    0  NEN2M3
  69     54    D     OUTPUT     t        0      0   0    8    3    0    0  NEN8B
  50     38    C     OUTPUT     t        2      2   0    9    0    0    0  NEN512K0
  48     36    C     OUTPUT     t        2      0   1    9    0    0    0  NEN512K1
  35     22    B     OUTPUT     t        0      0   0    3    1    0    0  NRDOEOUT
  33     24    B     OUTPUT     t        0      0   0    0    3    0    0  NVIOLBRK
  64     50    D     OUTPUT     t        2      1   1   10    4    0    0  NWE0
  67     52    D     OUTPUT     t        2      1   1   10    4    0    0  NWE1
  24     31    B         FF     t        1      1   0    4    1    0    0  RESERVE (|7474:U147|:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (80)    63    D       DFFE     t        1      1   0    6    1    2    0  WPFLG_3 (|7474:U57|:9)
 (75)    59    D       DFFE     t        1      1   0    5    1    2    0  GUFLG_3 (|7474:U57|:10)
 (63)    49    D       DFFE     t        1      1   0    4    1    2    0  DISRDONLY_1 (|7474:U148|:10)
 (65)    51    D       DFFE     t        1      1   0    4    1    1    0  NENVIOL_1 (|7474:U149|:10)
 (31)    25    B       DFFE     t        1      1   0    4    2    3    0  ENIDCODE_7 (|7474:U159|:9)
 (25)    30    B       DFFE     t        1      0   0    4    1    5    0  NDMA_1 (|7474:U159|:10)
 (27)    29    B       DFFE     t        1      1   0    4    2    0    2  NPRVIOL_1 (|7474:U163|:9)
 (29)    27    B       DFFE     t        1      1   0    4    2    8    0  DIAG_1 (|7474:U163|:10)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                     Logic cells placed in LAB 'B'
        +--------------------------- LC20 CPD0
        | +------------------------- LC19 CPD1
        | | +----------------------- LC17 CPD5
        | | | +--------------------- LC18 CPD6
        | | | | +------------------- LC21 INHIMAP
        | | | | | +----------------- LC23 MAPCOVSEL
        | | | | | | +--------------- LC28 NENMAP
        | | | | | | | +------------- LC22 NRDOEOUT
        | | | | | | | | +----------- LC24 NVIOLBRK
        | | | | | | | | | +--------- LC31 RESERVE
        | | | | | | | | | | +------- LC25 ENIDCODE_7
        | | | | | | | | | | | +----- LC30 NDMA_1
        | | | | | | | | | | | | +--- LC29 NPRVIOL_1
        | | | | | | | | | | | | | +- LC27 DIAG_1
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC20 -> - - - - - - - - - * - * - - | - * - - | <-- CPD0
LC19 -> - - - - * - - - - - - - - - | - * - - | <-- CPD1
LC18 -> - - - - - - - - - - * - * * | - * - - | <-- CPD6
LC25 -> * - * - - - - * - - - - - - | - * - - | <-- ENIDCODE_7

Pin
9    -> - - - - * * * - - * * * * * | - * - * | <-- CPA4
18   -> - - - - * * * - - * * * * * | - * - * | <-- CPS8
22   -> * * * * - - - * - - - - - - | - * * * | <-- CPS9
84   -> - - - - - - - - - - - - - - | - - - - | <-- NCOVSELG
21   -> * * * * * * * * - * * * * * | - * * * | <-- NCPCS8
12   -> - - * - - - - - - - - - - - | - * * - | <-- NMAX8M
75   -> * - * - - - - * - - - - - - | - * - - | <-- NMCS2L
83   -> - - - - - - - - - - - - - - | - - - * | <-- NMEMRQ
2    -> - - - - - - - - - - - - - - | - - - - | <-- NRDOEG
20   -> - - - - * * * - - * * * * * | - * - * | <-- NRESET
1    -> - - - - - - - - - - - - - - | - - * - | <-- N2MVLD0
29   -> - - - * - - - - - - - - - - | - * - - | <-- N512KVLD
LC43 -> - - - - - * - - - - - - - - | - * - - | <-- CPD2
LC41 -> - - - - - - * - - - - - - - | - * - - | <-- CPD4
LC53 -> - - - - - - - - - - * - * * | - * - - | <-- CPD7
LC63 -> * - - - - - - - * - - - - - | - * - - | <-- WPFLG_3
LC59 -> - * - - - - - - * - - - - - | - * - - | <-- GUFLG_3
LC51 -> - - - - - - - - * - - - - - | - * - - | <-- NENVIOL_1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                 Logic cells placed in LAB 'C'
        +----------------------- LC44 CEMA17
        | +--------------------- LC43 CPD2
        | | +------------------- LC42 CPD3
        | | | +----------------- LC41 CPD4
        | | | | +--------------- LC40 NEN1M0
        | | | | | +------------- LC34 NEN1M1
        | | | | | | +----------- LC45 NEN2M0
        | | | | | | | +--------- LC48 NEN2M1
        | | | | | | | | +------- LC47 NEN2M2
        | | | | | | | | | +----- LC46 NEN2M3
        | | | | | | | | | | +--- LC38 NEN512K0
        | | | | | | | | | | | +- LC36 NEN512K1
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':

Pin
22   -> - * * * - - - - - - - - | - * * * | <-- CPS9
63   -> - - - - * * * * * * * * | - - * - | <-- EA16
46   -> * - - - * * * * * * * * | - - * - | <-- EA17
25   -> - - - - * * * * * * * * | - - * - | <-- EA18
27   -> - - - - * * * * * * * * | - - * - | <-- EA19
65   -> - - - - * * * * * * * * | - - * - | <-- EA20
84   -> - - - - - - - - - - - - | - - - - | <-- NCOVSELG
21   -> - * * * - - - - - - - - | - * * * | <-- NCPCS8
12   -> * - - - * * * * * * * * | - * * - | <-- NMAX8M
83   -> - - - - - - - - - - - - | - - - * | <-- NMEMRQ
2    -> - - - - - - - - - - - - | - - - - | <-- NRDOEG
5    -> - * - - * * * * * * * * | - - * - | <-- N1MVLD
1    -> - - * - * * * * * * * * | - - * - | <-- N2MVLD0
14   -> - - - * * * * * * * * * | - - * - | <-- N2MVLD1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                       Logic cells placed in LAB 'D'
        +----------------------------- LC53 CPD7
        | +--------------------------- LC58 DIR
        | | +------------------------- LC62 MD0
        | | | +----------------------- LC61 MD8
        | | | | +--------------------- LC60 NEMRD0
        | | | | | +------------------- LC57 NEMRD1
        | | | | | | +----------------- LC56 NENEMBH
        | | | | | | | +--------------- LC55 NENEMBL
        | | | | | | | | +------------- LC54 NEN8B
        | | | | | | | | | +----------- LC50 NWE0
        | | | | | | | | | | +--------- LC52 NWE1
        | | | | | | | | | | | +------- LC63 WPFLG_3
        | | | | | | | | | | | | +----- LC59 GUFLG_3
        | | | | | | | | | | | | | +--- LC49 DISRDONLY_1
        | | | | | | | | | | | | | | +- LC51 NENVIOL_1
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC49 -> - - - - - - - - - * * - - - - | - - - * | <-- DISRDONLY_1

Pin
9    -> - - - - - - - - - - - - - * * | - * - * | <-- CPA4
18   -> - - - - - - - - - * * - - * * | - * - * | <-- CPS8
22   -> - * - - * * - - - - - - - - - | - * * * | <-- CPS9
4    -> - - - - - - * * * * * * * - - | - - - * | <-- EMUSPACE
23   -> - - - - - - - * * * - - - - - | - - - * | <-- NBPBUS0
11   -> - - - - - - * - * - * - - - - | - - - * | <-- NBPBUS1
84   -> - - - - - - - - - - - - - - - | - - - - | <-- NCOVSELG
21   -> - - - - - - - - - - - - - * * | - * * * | <-- NCPCS8
16   -> - - - - - - - - - * * * * - - | - - - * | <-- NEMVALID
8    -> - - - - - - * * * * * - - - - | - - - * | <-- NENEM
6    -> - * - - * * - - - * * - - - - | - - - * | <-- NERD
51   -> - - - - - - - - - * * * - - - | - - - * | <-- NEWE
30   -> - - - - - - - - - - - - * - - | - - - * | <-- NGUARD
31   -> - - - - - - - * - * - - - - - | - - - * | <-- NMBEN0
49   -> - - - - - - * - * - * - - - - | - - - * | <-- NMBEN1
83   -> - - - - - - * * * * * * * - - | - - - * | <-- NMEMRQ
2    -> - - - - - - - - - - - - - - - | - - - - | <-- NRDOEG
10   -> - - - - - - - - - * * * - - - | - - - * | <-- NRDONLY
20   -> - - - - - - - - - - - * * * * | - * - * | <-- NRESET
15   -> - - - - - - * * * - - - - - - | - - - * | <-- NSTROBE
1    -> - - - - - - - - - - - - - - - | - - * - | <-- N2MVLD0
17   -> - - - - - - * - * - - - - - - | - - - * | <-- SEL8
LC42 -> - - - - - - - - - - - - - * - | - - - * | <-- CPD3
LC17 -> - - - - - - - - - - - - - - * | - - - * | <-- CPD5
LC23 -> - - - - - - * * * * * - - - - | - - - * | <-- MAPCOVSEL
LC30 -> - - - - - - * * * * * - - - - | - - - * | <-- NDMA_1
LC29 -> - - - - - - - - - - - * * - - | - - - * | <-- NPRVIOL_1
LC27 -> - * - - * * * * * * * - - - - | - - - * | <-- DIAG_1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  c:\ovrm\ovrm.rpt
OVRM

** EQUATIONS **

CPA4     : INPUT;
CPS8     : INPUT;
CPS9     : INPUT;
EA16     : INPUT;
EA17     : INPUT;
EA18     : INPUT;
EA19     : INPUT;
EA20     : INPUT;
EMUSPACE : INPUT;
NBPBUS0  : INPUT;
NBPBUS1  : INPUT;
NCOVSELG : INPUT;
NCPCS8   : INPUT;
NEMVALID : INPUT;
NENEM    : INPUT;
NERD     : INPUT;
NEWE     : INPUT;
NGUARD   : INPUT;
NMAX8M   : INPUT;
NMBEN0   : INPUT;
NMBEN1   : INPUT;
NMCS2L   : INPUT;
NMEMRQ   : INPUT;
NRDOEG   : INPUT;
NRDONLY  : INPUT;
NRESET   : INPUT;
NSTROBE  : INPUT;
N1MVLD   : INPUT;
N2MVLD0  : INPUT;
N2MVLD1  : INPUT;
N512KVLD : INPUT;
SEL8     : INPUT;

-- Node name is 'CEMA17' 
-- Equation name is 'CEMA17', location is LC044, type is output.
 CEMA17  = LCELL( _EQ001 $  VCC);
  _EQ001 = !EA17 & !NMAX8M;

-- Node name is 'CPD0' 
-- Equation name is 'CPD0', location is LC020, type is bidir.
CPD0     = TRI(_LC020, GLOBAL(!NRDOEG));
_LC020   = LCELL( _EQ002 $  GND);
  _EQ002 = !CPS9 &  ENIDCODE_7 & !NMCS2L
         # !CPS9 & !NCPCS8 & !WPFLG_3;

-- Node name is 'CPD1' 
-- Equation name is 'CPD1', location is LC019, type is bidir.
CPD1     = TRI(_LC019, GLOBAL(!NRDOEG));
_LC019   = LCELL( _EQ003 $  GND);
  _EQ003 = !CPS9 & !GUFLG_3 & !NCPCS8;

-- Node name is 'CPD2' 
-- Equation name is 'CPD2', location is LC043, type is bidir.
CPD2     = TRI(_LC043, GLOBAL(!NRDOEG));
_LC043   = LCELL( _EQ004 $  GND);
  _EQ004 = !CPS9 & !NCPCS8 &  N1MVLD;

-- Node name is 'CPD3' 
-- Equation name is 'CPD3', location is LC042, type is bidir.
CPD3     = TRI(_LC042, GLOBAL(!NRDOEG));
_LC042   = LCELL( _EQ005 $  GND);
  _EQ005 = !CPS9 & !NCPCS8 &  N2MVLD0;

-- Node name is 'CPD4' 
-- Equation name is 'CPD4', location is LC041, type is bidir.
CPD4     = TRI(_LC041, GLOBAL(!NRDOEG));
_LC041   = LCELL( _EQ006 $  GND);
  _EQ006 = !CPS9 & !NCPCS8 &  N2MVLD1;

-- Node name is 'CPD5' 
-- Equation name is 'CPD5', location is LC017, type is bidir.
CPD5     = TRI(_LC017, GLOBAL(!NRDOEG));
_LC017   = LCELL( _EQ007 $  GND);
  _EQ007 = !CPS9 &  ENIDCODE_7 & !NMCS2L
         # !CPS9 & !NCPCS8 &  NMAX8M;

-- Node name is 'CPD6' 
-- Equation name is 'CPD6', location is LC018, type is bidir.
CPD6     = TRI(_LC018, GLOBAL(!NRDOEG));
_LC018   = LCELL( _EQ008 $  GND);
  _EQ008 = !CPS9 & !NCPCS8 &  N512KVLD;

-- Node name is 'CPD7' 
-- Equation name is 'CPD7', location is LC053, type is bidir.
CPD7     = TRI(_LC053, GLOBAL(!NRDOEG));
_LC053   = LCELL( GND $  GND);

-- Node name is '|7474:U163|:10' = 'DIAG_1' 
-- Equation name is 'DIAG_1', location is LC027, type is buried.
DIAG_1   = DFFE( _EQ009 $  GND,  _EQ010,  NRESET,  VCC,  VCC);
  _EQ009 = !CPD6 &  CPD7;
  _EQ010 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is 'DIR' 
-- Equation name is 'DIR', location is LC058, type is output.
 DIR     = LCELL( _EQ011 $  GND);
  _EQ011 = !CPS9 &  DIAG_1
         # !DIAG_1 & !NERD;

-- Node name is '|7474:U148|:10' = 'DISRDONLY_1' 
-- Equation name is 'DISRDONLY_1', location is LC049, type is buried.
DISRDONLY_1 = DFFE( CPD3 $  GND,  _EQ012,  VCC,  NRESET,  VCC);
  _EQ012 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is '|7474:U159|:9' = 'ENIDCODE_7' 
-- Equation name is 'ENIDCODE_7', location is LC025, type is buried.
ENIDCODE_7 = DFFE( _EQ013 $  GND,  _EQ014,  NRESET,  VCC,  VCC);
  _EQ013 =  CPD6 &  CPD7;
  _EQ014 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is '|7474:U57|:10' = 'GUFLG_3' 
-- Equation name is 'GUFLG_3', location is LC059, type is buried.
GUFLG_3  = DFFE( GND $  GND,  VCC, !_EQ015, !_EQ016,  VCC);
  _EQ015 =  _X002;
  _X002  = EXP( NPRVIOL_1 &  NRESET);
  _EQ016 =  EMUSPACE & !NEMVALID & !NGUARD & !NMEMRQ;

-- Node name is 'INHIMAP' = '|7474:U147.2q' 
-- Equation name is 'INHIMAP', type is output 
 INHIMAP = DFFE( CPD1 $  GND,  _EQ017,  VCC,  NRESET,  VCC);
  _EQ017 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is 'MAPCOVSEL' = '|7474:U148.1q' 
-- Equation name is 'MAPCOVSEL', type is output 
 MAPCOVSEL = DFFE( CPD2 $  GND,  _EQ018,  VCC,  NRESET,  VCC);
  _EQ018 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is 'MD0' 
-- Equation name is 'MD0', location is LC062, type is output.
MD0      = TRI(_LC062, GLOBAL(!NCOVSELG));
_LC062   = LCELL( GND $  VCC);

-- Node name is 'MD8' 
-- Equation name is 'MD8', location is LC061, type is output.
MD8      = TRI(_LC061, GLOBAL(!NCOVSELG));
_LC061   = LCELL( GND $  VCC);

-- Node name is '|7474:U159|:10' = 'NDMA_1' 
-- Equation name is 'NDMA_1', location is LC030, type is buried.
NDMA_1   = DFFE( CPD0 $  GND,  _EQ019,  VCC,  NRESET,  VCC);
  _EQ019 =  _X003;
  _X003  = EXP( CPA4 & !CPS8 & !NCPCS8);

-- Node name is 'NEMRD0' 
-- Equation name is 'NEMRD0', location is LC060, type is output.
 NEMRD0  = LCELL( _EQ020 $  GND);
  _EQ020 =  CPS9 &  DIAG_1
         # !DIAG_1 &  NERD;

-- Node name is 'NEMRD1' 
-- Equation name is 'NEMRD1', location is LC057, type is output.
 NEMRD1  = LCELL( _EQ021 $  GND);
  _EQ021 =  CPS9 &  DIAG_1
         # !DIAG_1 &  NERD;

-- Node name is 'NENEMBH' 
-- Equation name is 'NENEMBH', location is LC056, type is output.
 NENEMBH = LCELL( _EQ022 $  VCC);
  _EQ022 = !DIAG_1 &  EMUSPACE &  MAPCOVSEL &  NBPBUS1 & !NENEM & !NMBEN1 & 
             !NMEMRQ & !NSTROBE & !SEL8
         # !DIAG_1 &  MAPCOVSEL &  NBPBUS1 & !NDMA_1 & !NENEM & !NMBEN1 & 
             !NMEMRQ & !NSTROBE & !SEL8;

-- Node name is 'NENEMBL' 
-- Equation name is 'NENEMBL', location is LC055, type is output.
 NENEMBL = LCELL( _EQ023 $  VCC);
  _EQ023 = !DIAG_1 &  EMUSPACE &  MAPCOVSEL &  NBPBUS0 & !NENEM & !NMBEN0 & 
             !NMEMRQ & !NSTROBE
         # !DIAG_1 &  MAPCOVSEL &  NBPBUS0 & !NDMA_1 & !NENEM & !NMBEN0 & 
             !NMEMRQ & !NSTROBE
         #  DIAG_1 & !NBPBUS0;

-- Node name is 'NENMAP' = '|7474:U149.1q' 
-- Equation name is 'NENMAP', type is output 
 NENMAP  = DFFE( CPD4 $  GND,  _EQ024,  VCC,  NRESET,  VCC);
  _EQ024 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is '|7474:U149|:10' = 'NENVIOL_1' 
-- Equation name is 'NENVIOL_1', location is LC051, type is buried.
NENVIOL_1 = DFFE( CPD5 $  GND,  _EQ025,  VCC,  NRESET,  VCC);
  _EQ025 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is 'NEN1M0' 
-- Equation name is 'NEN1M0', location is LC040, type is output.
 NEN1M0  = LCELL( _EQ026 $  VCC);
  _EQ026 = !EA16 &  EA17 &  NMAX8M & !N1MVLD &  _X004
         # !EA18 &  EA19 & !NMAX8M & !N1MVLD &  _X005;
  _X004  = EXP( EA18 & !N2MVLD0 & !N2MVLD1);
  _X005  = EXP( EA20 & !N2MVLD0 & !N2MVLD1);

-- Node name is 'NEN1M1' 
-- Equation name is 'NEN1M1', location is LC034, type is output.
 NEN1M1  = LCELL( _EQ027 $  VCC);
  _EQ027 =  EA16 &  EA17 &  NMAX8M & !N1MVLD &  _X004
         #  EA18 &  EA19 & !NMAX8M & !N1MVLD &  _X005;
  _X004  = EXP( EA18 & !N2MVLD0 & !N2MVLD1);
  _X005  = EXP( EA20 & !N2MVLD0 & !N2MVLD1);

-- Node name is 'NEN2M0' 
-- Equation name is 'NEN2M0', location is LC045, type is output.
 NEN2M0  = LCELL( _EQ028 $  VCC);
  _EQ028 = !EA16 & !EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         # !EA18 & !EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

-- Node name is 'NEN2M1' 
-- Equation name is 'NEN2M1', location is LC048, type is output.
 NEN2M1  = LCELL( _EQ029 $  VCC);
  _EQ029 =  EA16 & !EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA18 & !EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

-- Node name is 'NEN2M2' 
-- Equation name is 'NEN2M2', location is LC047, type is output.
 NEN2M2  = LCELL( _EQ030 $  VCC);
  _EQ030 = !EA16 &  EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         # !EA18 &  EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

-- Node name is 'NEN2M3' 
-- Equation name is 'NEN2M3', location is LC046, type is output.
 NEN2M3  = LCELL( _EQ031 $  VCC);
  _EQ031 =  EA16 &  EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA18 &  EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

-- Node name is 'NEN8B' 
-- Equation name is 'NEN8B', location is LC054, type is output.
 NEN8B   = LCELL( _EQ032 $  VCC);
  _EQ032 = !DIAG_1 &  EMUSPACE &  MAPCOVSEL &  NBPBUS0 & !NENEM & !NMBEN1 & 
             !NMEMRQ & !NSTROBE &  SEL8
         # !DIAG_1 &  MAPCOVSEL &  NBPBUS0 & !NDMA_1 & !NENEM & !NMBEN1 & 
             !NMEMRQ & !NSTROBE &  SEL8
         #  DIAG_1 & !NBPBUS1;

-- Node name is 'NEN512K0' 
-- Equation name is 'NEN512K0', location is LC038, type is output.
 NEN512K0 = LCELL( _EQ033 $  VCC);
  _EQ033 = !EA16 & !EA17 &  NMAX8M &  _X004
         # !EA18 & !EA19 & !NMAX8M &  _X005
         # !EA16 &  NMAX8M &  N1MVLD
         # !EA18 & !NMAX8M &  N1MVLD;
  _X004  = EXP( EA18 & !N2MVLD0 & !N2MVLD1);
  _X005  = EXP( EA20 & !N2MVLD0 & !N2MVLD1);

-- Node name is 'NEN512K1' 
-- Equation name is 'NEN512K1', location is LC036, type is output.
 NEN512K1 = LCELL( _EQ034 $  GND);
  _EQ034 =  EA18 & !N1MVLD & !N2MVLD0 & !N2MVLD1 &  _X006
         #  EA17 &  NMAX8M & !N1MVLD
         #  EA19 & !NMAX8M & !N1MVLD
         # !EA16 &  NMAX8M
         # !EA18 & !NMAX8M;
  _X006  = EXP(!EA20 & !NMAX8M);

-- Node name is '|7474:U163|:9' = 'NPRVIOL_1' 
-- Equation name is 'NPRVIOL_1', location is LC029, type is buried.
NPRVIOL_1 = DFFE( _EQ035 $  VCC,  _EQ036,  VCC,  NRESET,  VCC);
  _EQ035 = !CPD6 & !CPD7;
  _EQ036 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is 'NRDOEOUT' 
-- Equation name is 'NRDOEOUT', location is LC022, type is output.
 NRDOEOUT = LCELL( _EQ037 $  VCC);
  _EQ037 = !CPS9 &  ENIDCODE_7 & !NMCS2L
         # !CPS9 & !NCPCS8;

-- Node name is 'NVIOLBRK' 
-- Equation name is 'NVIOLBRK', location is LC024, type is output.
 NVIOLBRK = LCELL( _EQ038 $  NENVIOL_1);
  _EQ038 = !GUFLG_3 & !NENVIOL_1 & !WPFLG_3;

-- Node name is 'NWE0' 
-- Equation name is 'NWE0', location is LC050, type is output.
 NWE0    = LCELL( _EQ039 $  VCC);
  _EQ039 = !DIAG_1 &  EMUSPACE & !NEMVALID & !NENEM & !NEWE & !NMBEN0 & 
             !NMEMRQ &  _X007
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NEMVALID & !NENEM & !NERD & 
             !NMBEN0 & !NMEMRQ
         # !DIAG_1 & !NDMA_1 & !NENEM & !NEWE & !NMBEN0 & !NMEMRQ &  _X007
         # !DIAG_1 & !MAPCOVSEL & !NDMA_1 & !NENEM & !NERD & !NMBEN0 & 
             !NMEMRQ
         # !CPS8 &  DIAG_1 & !NBPBUS0;
  _X007  = EXP(!DISRDONLY_1 &  MAPCOVSEL & !NRDONLY);

-- Node name is 'NWE1' 
-- Equation name is 'NWE1', location is LC052, type is output.
 NWE1    = LCELL( _EQ040 $  VCC);
  _EQ040 = !DIAG_1 &  EMUSPACE & !NEMVALID & !NENEM & !NEWE & !NMBEN1 & 
             !NMEMRQ &  _X007
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NEMVALID & !NENEM & !NERD & 
             !NMBEN1 & !NMEMRQ
         # !DIAG_1 & !NDMA_1 & !NENEM & !NEWE & !NMBEN1 & !NMEMRQ &  _X007
         # !DIAG_1 & !MAPCOVSEL & !NDMA_1 & !NENEM & !NERD & !NMBEN1 & 
             !NMEMRQ
         # !CPS8 &  DIAG_1 & !NBPBUS1;
  _X007  = EXP(!DISRDONLY_1 &  MAPCOVSEL & !NRDONLY);

-- Node name is 'RESERVE' = '|7474:U147.1q' 
-- Equation name is 'RESERVE', type is output 
 RESERVE = DFFE( CPD0 $  GND,  _EQ041,  VCC,  NRESET,  VCC);
  _EQ041 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

-- Node name is '|7474:U57|:9' = 'WPFLG_3' 
-- Equation name is 'WPFLG_3', location is LC063, type is buried.
WPFLG_3  = DFFE( GND $  GND,  VCC, !_EQ042, !_EQ043,  VCC);
  _EQ042 =  _X002;
  _X002  = EXP( NPRVIOL_1 &  NRESET);
  _EQ043 =  EMUSPACE & !NEMVALID & !NEWE & !NMEMRQ & !NRDONLY;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs -B-D




Project Information                                           c:\ovrm\ovrm.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic I/O Cell Registers        = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,263K
