 
XEPLD, Version XACT-CPLD-V6.0.2a                            Xilinx Inc.
                                  Fitter Report
   Design Name: hd302lc2
Fitting Status: Successful                          Date: 11- 8-97,  4:26PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
hd302lc2      XC9536-5PC44      19 /36  ( 52%) 28 /180 ( 15%)  32 /34  ( 94%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   13          13    |  I/O              :    26        2
Output        :   19          19    |  GCK/IO           :     3        0
Bidirectional :    0           0    |  GTS/IO           :     2        0
GCK           :    0           0    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     32          32

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 19 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 19 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
ELDS                1       2       FB2_13  STD  FAST 29   I/O       O
EPD0                1       1       FB1_1   STD  FAST 2    I/O       O
EPD1                2       3       FB1_2   STD  FAST 3    I/O       O
EPD10               1       1       FB1_11  STD  FAST 13   I/O       O
EPD11               1       1       FB1_12  STD  FAST 14   I/O       O
EPD12               1       1       FB1_13  STD  FAST 18   I/O       O
EPD13               2       2       FB1_14  STD  FAST 19   I/O       O
EPD14               2       2       FB1_15  STD  FAST 20   I/O       O
EPD15               1       1       FB1_16  STD  FAST 22   I/O       O
EPD2                2       3       FB1_4   STD  FAST 4    I/O       O
EPD3                2       3       FB1_3   STD  FAST 5    GCK/I/O   O
EPD4                2       3       FB1_5   STD  FAST 6    GCK/I/O   O
EPD5                1       1       FB1_7   STD  FAST 7    GCK/I/O   O
EPD6                1       1       FB1_6   STD  FAST 8    I/O       O
EPD7                2       3       FB1_8   STD  FAST 9    I/O       O
EPD8                1       1       FB1_9   STD  FAST 11   I/O       O
EPD9                1       1       FB1_10  STD  FAST 12   I/O       O
EUDS                2       3       FB2_14  STD  FAST 28   I/O       O
NCSACTIVE           2       7       FB2_8   STD  FAST 37   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
BMSK8                               FB2_9             36   I/O       I
EDISCPU                             FB2_3             42   GTS/I/O   I
EPOE                                FB2_7             38   I/O       I
EPWEH                               FB2_5             40   GTS/I/O   I
EPWEL                               FB2_6             39   GSR/I/O   I
IAC                                 FB2_2             44   I/O       I
NCS0                                FB2_15            27   I/O       I
NCS1                                FB2_16            26   I/O       I
NCS2                                FB2_17            25   I/O       I
NCS3                                FB1_17            24   I/O       I
NCSEXT                              FB2_10            35   I/O       I
NENHIBYTE                           FB2_4             43   I/O       I
NENLOWBYTE                          FB2_1             1    I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          16           4           4           23        16/0       17   
FB2           3          11          11            5         3/0       17   
            ----                                -----       -----     ----- 
             19                                   28        19/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               4/32
Number of signals used by logic mapping into function block:  4
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
EPD0                  1       0     0   4     FB1_1   STD   2   I/O     O
EPD1                  2       0     0   3     FB1_2   STD   3   I/O     O
EPD3                  2       0     0   3     FB1_3   STD   5   GCK/I/O O
EPD2                  2       0     0   3     FB1_4   STD   4   I/O     O
EPD4                  2       0     0   3     FB1_5   STD   6   GCK/I/O O
EPD6                  1       0     0   4     FB1_6   STD   8   I/O     O
EPD5                  1       0     0   4     FB1_7   STD   7   GCK/I/O O
EPD7                  2       0     0   3     FB1_8   STD   9   I/O     O
EPD8                  1       0     0   4     FB1_9   STD   11  I/O     O
EPD9                  1       0     0   4     FB1_10  STD   12  I/O     O
EPD10                 1       0     0   4     FB1_11  STD   13  I/O     O
EPD11                 1       0     0   4     FB1_12  STD   14  I/O     O
EPD12                 1       0     0   4     FB1_13  STD   18  I/O     O
EPD13                 2       0     0   3     FB1_14  STD   19  I/O     O
EPD14                 2       0     0   3     FB1_15  STD   20  I/O     O
EPD15                 1       0     0   4     FB1_16  STD   22  I/O     O
(unused)              0       0     0   5     FB1_17        24  I/O     I
(unused)              0       0     0   5     FB1_18            (b)     

Signals Used by Logic in Function Block
  1: BMSK8              3: NENHIBYTE          4: NENLOWBYTE       
  2: EPWEH            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
EPD0                 ...X.................................... 1       1
EPD1                 XX.X.................................... 3       3
EPD3                 XX.X.................................... 3       3
EPD2                 XX.X.................................... 3       3
EPD4                 XX.X.................................... 3       3
EPD6                 ...X.................................... 1       1
EPD5                 ...X.................................... 1       1
EPD7                 XX.X.................................... 3       3
EPD8                 ..X..................................... 1       1
EPD9                 ..X..................................... 1       1
EPD10                ..X..................................... 1       1
EPD11                ..X..................................... 1       1
EPD12                ..X..................................... 1       1
EPD13                X.X..................................... 2       2
EPD14                X.X..................................... 2       2
EPD15                ..X..................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               11/25
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
(unused)              0       0     0   5     FB2_1         1   I/O     I
(unused)              0       0     0   5     FB2_2         44  I/O     I
(unused)              0       0     0   5     FB2_3         42  GTS/I/O I
(unused)              0       0     0   5     FB2_4         43  I/O     I
(unused)              0       0     0   5     FB2_5         40  GTS/I/O I
(unused)              0       0     0   5     FB2_6         39  GSR/I/O I
(unused)              0       0     0   5     FB2_7         38  I/O     I
NCSACTIVE             2       0     0   3     FB2_8   STD   37  I/O     O
(unused)              0       0     0   5     FB2_9         36  I/O     I
(unused)              0       0     0   5     FB2_10        35  I/O     I
(unused)              0       0     0   5     FB2_11        34  I/O     
(unused)              0       0     0   5     FB2_12        33  I/O     
ELDS                  1       0     0   4     FB2_13  STD   29  I/O     O
EUDS                  2       0     0   3     FB2_14  STD   28  I/O     O
(unused)              0       0     0   5     FB2_15        27  I/O     I
(unused)              0       0     0   5     FB2_16        26  I/O     I
(unused)              0       0     0   5     FB2_17        25  I/O     I
(unused)              0       0     0   5     FB2_18            (b)     

Signals Used by Logic in Function Block
  1: BMSK8              5: EPWEL              9: NCS2             
  2: EDISCPU            6: IAC               10: NCS3             
  3: EPOE               7: NCS0              11: NCSEXT           
  4: EPWEH              8: NCS1             

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
NCSACTIVE            .X...XXXXXX............................. 7       7
ELDS                 ..X.X................................... 2       2
EUDS                 X.XX.................................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

 ELDS  =  EPOE * EPWEL    

/EPD0  = Vcc    
   EPD0.TRST = /NENLOWBYTE

/EPD1  =  BMSK8 */EPWEH    
   EPD1.TRST = /NENLOWBYTE

/EPD10  = Vcc    
   EPD10.TRST = /NENHIBYTE

/EPD11  = Vcc    
   EPD11.TRST = /NENHIBYTE

/EPD12  = Vcc    
   EPD12.TRST = /NENHIBYTE

/EPD13  =  BMSK8    
   EPD13.TRST = /NENHIBYTE

/EPD14  =  BMSK8    
   EPD14.TRST = /NENHIBYTE

/EPD15  = Vcc    
   EPD15.TRST = /NENHIBYTE

/EPD2  =  BMSK8 */EPWEH    
   EPD2.TRST = /NENLOWBYTE

/EPD3  =  BMSK8 */EPWEH    
   EPD3.TRST = /NENLOWBYTE

/EPD4  =  BMSK8 */EPWEH    
   EPD4.TRST = /NENLOWBYTE

/EPD5  = Gnd    
   EPD5.TRST = /NENLOWBYTE

/EPD6  = Gnd    
   EPD6.TRST = /NENLOWBYTE

/EPD7  =  BMSK8 */EPWEH    
   EPD7.TRST = /NENLOWBYTE

/EPD8  = Vcc    
   EPD8.TRST = /NENHIBYTE

/EPD9  = Vcc    
   EPD9.TRST = /NENHIBYTE

/EUDS  = /EPWEH
       + /BMSK8 */EPOE    

 NCSACTIVE  =  EDISCPU */IAC * NCS1 * NCS2 * NCS3 * NCSEXT
       + /IAC * NCS0 * NCS1 * NCS2 * NCS3 * NCSEXT    

****************************  Device Pin Out ****************************

Device : XC9536-5PC44


                       N                 
                       E     N           
                       N     E           
                       L     N  E        
                       O     H  D        
                       W     I  I     E  
        E  E  E  E  E  B     B  S     P  
        P  P  P  P  P  Y  I  Y  C  V  W  
        D  D  D  D  D  T  A  T  P  C  E  
        4  3  2  1  0  E  C  E  U  C  H  
        --------------------------------  
       /6  5  4  3  2  1  44 43 42 41 40 \
 EPD5 | 7                             39 | EPWEL
 EPD6 | 8                             38 | EPOE
 EPD7 | 9                             37 | NCSACTIVE
  GND | 10                            36 | BMSK8
 EPD8 | 11         XC9536-5PC44       35 | NCSEXT
 EPD9 | 12                            34 | N.C.
EPD10 | 13                            33 | N.C.
EPD11 | 14                            32 | VCC
  TDI | 15                            31 | GND
  TMS | 16                            30 | TDO
  TCK | 17                            29 | ELDS
      \ 18 19 20 21 22 23 24 25 26 27 28 /
        --------------------------------  
        E  E  E  V  E  G  N  N  N  N  E  
        P  P  P  C  P  N  C  C  C  C  U  
        D  D  D  C  D  D  S  S  S  S  D  
        1  1  1     1     3  2  1  0  S  
        2  3  4     5                    


Legend : N.C. = Pin Not Connected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device Selection Mode                       : Single
Device(s) Specified                         : 9536-5PC44
Global Clock Optimization                   : INDESIGN - ON
Global Output Enable Optimization           : INDESIGN - ON
UIM Optimization                            : INDESIGN - ON
Timing Optimization                         : OFF
Ignore Tspecs                               : OFF
Create Programmable Ground Pins             : OFF
Guide File Used                             : NONE
Ignore Pin Assignments                      : OFF
Restore Pin Assignments After Optimizations : ON
Collapsing pterm limit                      : 15
Collapsing input limit                      : 36
