Project Information                                    d:\hdlc302\hd302lc1.rpt

MAX+plus II Compiler Report File
Version 8.3 4/02/98
Compiled: 05/11/98 12:12:09

Copyright (C) 1988-1998 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


The Header controller of MICEpack 68302. rev 2.0


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

hd302lc1  EPM7192SQC160-10 57       40       0      69      48          35 %

User Pins:                 57       40       0  



Project Information                                    d:\hdlc302\hd302lc1.rpt

** PROJECT COMPILATION MESSAGES **

Warning: GLOBAL primitive on node 'epRst' feeds logic -- non-global signal usage may result
Warning: GLOBAL primitive on node 'epClk' feeds logic -- non-global signal usage may result


Project Information                                    d:\hdlc302\hd302lc1.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'epRst' chosen for auto global Clear


Project Information                                    d:\hdlc302\hd302lc1.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

hd302lc1@62                       bmsk8
hd302lc1@43                       brkAck
hd302lc1                          bsw
hd302lc1                          bswen
hd302lc1@38                       busw
hd302lc1@69                       cHaltPin
hd302lc1                          chgMode
hd302lc1@58                       cpenas
hd302lc1@53                       cpends
hd302lc1                          dedicatedMode
hd302lc1                          delBmsk8
hd302lc1@85                       dirpbdh
hd302lc1@104                      dirpbdl
hd302lc1@24                       disnrdy
hd302lc1                          dlyIceBrk0
hd302lc1                          dlyIceBrk1
hd302lc1@113                      dlyLds
hd302lc1@131                      dlyOe
hd302lc1@101                      dlyUds
hd302lc1@136                      dlyWeh
hd302lc1@125                      dlyWel
hd302lc1                          |DVALID:SDvalid|:1
hd302lc1                          |DVALID:SDvalid|:17
hd302lc1                          |DVALID:SDvalid|:21
hd302lc1@147                      eDisCpu
hd302lc1@149                      emuspace
hd302lc1@5                        epAs
hd302lc1@100                      ep_A0
hd302lc1@4                        epA1
hd302lc1@2                        epA2
hd302lc1@159                      epA3
hd302lc1@158                      epA4
hd302lc1@21                       epA5
hd302lc1@15                       epA6
hd302lc1@17                       epA7
hd302lc1@19                       epA8
hd302lc1@20                       epA9
hd302lc1@157                      epA10
hd302lc1@8                        epA11
hd302lc1@160                      epDtack
hd302lc1@33                       epD5
hd302lc1@34                       epD6
hd302lc1@36                       epD8
hd302lc1@22                       epD9
hd302lc1@45                       epD10
hd302lc1@60                       epD15
hd302lc1@152                      epfc0
hd302lc1@151                      epfc1
hd302lc1@150                      epfc2
hd302lc1@51                       epGo
hd302lc1@7                        epHalt
hd302lc1@91                       epIpl0
hd302lc1@99                       epIpl1
hd302lc1@97                       epIpl2
hd302lc1@153                      epOe
hd302lc1@141                      epRst
hd302lc1@37                       epStop
hd302lc1@154                      epWeh
hd302lc1@6                        epWel
hd302lc1                          et1reg
hd302lc1                          et6reg
hd302lc1                          et7reg
hd302lc1@13                       exRdy
hd302lc1@116                      Fdtack
hd302lc1@115                      flagNotRdy
hd302lc1@156                      iac
hd302lc1@14                       iceBrk
hd302lc1@139                      iceClk
hd302lc1@26                       iceRdy
hd302lc1                          indlyLds
hd302lc1                          indlyUds
hd302lc1@9                        isoep
hd302lc1                          iwct0
hd302lc1                          iwct1
hd302lc1                          iwct2
hd302lc1                          iwct3
hd302lc1                          lIpl0
hd302lc1                          lIpl1
hd302lc1                          lIpl2
hd302lc1@123                      nadvalid
hd302lc1@35                       nClrHalt
hd302lc1@41                       nCsActive_I
hd302lc1@87                       ndatavalid
hd302lc1@92                       nDma
hd302lc1@42                       nemdfc
hd302lc1@93                       nemdfcc
hd302lc1@44                       nemsfc
hd302lc1@94                       nemsfcc
hd302lc1@130                      nemvalid
hd302lc1@95                       nenepfc
hd302lc1@112                      nenHiByteO
hd302lc1@27                       nenIpl
hd302lc1@105                      nenLowByteO
hd302lc1@28                       nenNMI
hd302lc1@90                       nenpba
hd302lc1@108                      nenpbd
hd302lc1@77                       nentas
hd302lc1@76                       nenTcs
hd302lc1@109                      nentdh
hd302lc1@106                      nentdl
hd302lc1@83                       nentoe
hd302lc1@80                       nentweh
hd302lc1@79                       nentwel
hd302lc1@78                       nerd
hd302lc1@127                      newr
hd302lc1@88                       nFHalt
hd302lc1@31                       nFReset
hd302lc1@49                       ninshi
hd302lc1@29                       ninslow
hd302lc1@86                       nmemreq
hd302lc1@145                      nmhere
hd302lc1@50                       nRdOnly
hd302lc1@129                      nselepfc
hd302lc1@128                      nstrobe
hd302lc1                          nstrobeDly
hd302lc1@84                       nstsvalid
hd302lc1@52                       Qual
hd302lc1@16                       tIpl0
hd302lc1@12                       tIpl1
hd302lc1@30                       tIpl2
hd302lc1                          wct0
hd302lc1                          wct1
hd302lc1                          wct2
hd302lc1                          wct3
hd302lc1                          wct4


Project Information                                    d:\hdlc302\hd302lc1.rpt

** FILE HIERARCHY **



|dvalid:SDvalid|


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

***** Logic for device 'hd302lc1' compiled without errors.




Device: EPM7192SQC160-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF

                                                                                                  
                                                                                                  
                                                                                                  
                                       e                             R   R   n n         R n R R  
                 e                     m   e                         E   E   e s n       E a E E  
                 p                     u   D   n V         i   V d   S   S   m e s     d S d S S  
                 D     e   V e   e e e s   i   m C     e   c   C l   E V E d v l t     l E v E E  
                 t e e p   C p e p p p p   s # h C     p   e   C y # R C R l a e r n   y R a R R  
                 a p p A i C W p f f f a G C T e I G G R G C G I W T V C V y l p o e G W V l V V  
                 c A A 1 a I e O c c c c N p D r N N N s N l N N e D E I E O i f b w N e E i E E  
                 k 3 4 0 c O h e 0 1 2 e D u I e T D D t D k D T h O D O D e d c e r D l D d D D  
               ----------------------------------------------------------------------------------_ 
              / 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122   |_ 
             /    159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121    | 
       N.C. |  1                                                                                 120 | N.C. 
       epA2 |  2                                                                                 119 | RESERVED 
        GND |  3                                                                                 118 | VCCIO 
       epA1 |  4                                                                                 117 | RESERVED 
       epAs |  5                                                                                 116 | Fdtack 
      epWel |  6                                                                                 115 | flagNotRdy 
     epHalt |  7                                                                                 114 | RESERVED 
      epA11 |  8                                                                                 113 | dlyLds 
      isoep |  9                                                                                 112 | nenHiByteO 
      VCCIO | 10                                                                                 111 | GND 
       N.C. | 11                                                                                 110 | N.C. 
      tIpl1 | 12                                                                                 109 | nentdh 
      exRdy | 13                                                                                 108 | nenpbd 
     iceBrk | 14                                                                                 107 | RESERVED 
       epA6 | 15                                                                                 106 | nentdl 
      tIpl0 | 16                                                                                 105 | nenLowByteO 
       epA7 | 17                                                                                 104 | dirpbdl 
        GND | 18                                                                                 103 | VCCIO 
       epA8 | 19                                                                                 102 | RESERVED 
       epA9 | 20                                                                                 101 | dlyUds 
       epA5 | 21                                EPM7192SQC160-10                                 100 | ep_A0 
       epD9 | 22                                                                                  99 | epIpl1 
       #TMS | 23                                                                                  98 | #TCK 
    disnrdy | 24                                                                                  97 | epIpl2 
      VCCIO | 25                                                                                  96 | GND 
     iceRdy | 26                                                                                  95 | nenepfc 
     nenIpl | 27                                                                                  94 | nemsfcc 
     nenNMI | 28                                                                                  93 | nemdfcc 
    ninslow | 29                                                                                  92 | nDma 
      tIpl2 | 30                                                                                  91 | epIpl0 
    nFReset | 31                                                                                  90 | nenpba 
        GND | 32                                                                                  89 | VCCIO 
       epD5 | 33                                                                                  88 | nFHalt 
       epD6 | 34                                                                                  87 | ndatavalid 
   nClrHalt | 35                                                                                  86 | nmemreq 
       epD8 | 36                                                                                  85 | dirpbdh 
     epStop | 37                                                                                  84 | nstsvalid 
       busw | 38                                                                                  83 | nentoe 
       N.C. | 39                                                                                  82 | N.C. 
      VCCIO | 40                                                                                  81 | GND 
            |      42  44  46  48  50  52  54  56  58  60  62  64  66  68  70  72  74  76  78  80  _| 
             \   41  43  45  47  49  51  53  55  57  59  61  63  65  67  69  71  73  75  77  79   | 
              \----------------------------------------------------------------------------------- 
                 n n b n e R G R n n e Q c N V V G c R e R b R G V G N R c R R R R V R n n n n n  
                 C e r e p E N E i R p u p . C C N p E p E m E N C N . E H E E E E C E e e e e e  
                 s m k m D S D S n d G a e C C C D e S D S s S D C D C S a S S S S C S n n r n n  
                 A d A s 1 E   E s O o l n . I I   n E 1 E k E   I   . E l E E E E I E T t d t t  
                 c f c f 0 R   R h n     d   O N   a R 5 R 8 R   N     R t R R R R O R c a   w w  
                 t c k c   V   V i l     s     T   s V   V   V   T     V P V V V V   V s s   e e  
                 i         E   E   y                 E   E   E         E i E E E E   E       l h  
                 v         D   D                     D   D   D         D n D D D D   D            
                 e                                                                                
                 _                                                                                
                 I                                                                                


N.C. = Not Connected.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System-Programming or Configuration Pin. The JTAG inputs (TMS, TCK, TDI) should be tied to VCC when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions. 


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)  10/10(100%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)  10/10(100%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     1/16(  6%)  10/10(100%)   2/16( 12%)  20/36( 55%) 
D:    LC49 - LC64     1/16(  6%)  10/10(100%)   2/16( 12%)  20/36( 55%) 
E:    LC65 - LC80     1/16(  6%)  10/10(100%)   2/16( 12%)  20/36( 55%) 
F:    LC81 - LC96     2/16( 12%)   7/10( 70%)   2/16( 12%)  18/36( 50%) 
G:   LC97 - LC112     2/16( 12%)   2/10( 20%)   1/16(  6%)   7/36( 19%) 
H:  LC113 - LC128    10/16( 62%)  10/10(100%)  10/16( 62%)  19/36( 52%) 
I:  LC129 - LC144    14/16( 87%)  10/10(100%)   4/16( 25%)  30/36( 83%) 
J:  LC145 - LC160    11/16( 68%)   8/10( 80%)   9/16( 56%)  32/36( 88%) 
K:  LC161 - LC176    11/16( 68%)   4/10( 40%)  13/16( 81%)  23/36( 63%) 
L:  LC177 - LC192    16/16(100%)   8/10( 80%)  14/16( 87%)  22/36( 61%) 


Total dedicated input pins used:                 2/4      ( 50%)
Total I/O pins used:                            99/120    ( 82%)
Total logic cells used:                         69/192    ( 35%)
Total shareable expanders used:                 48/192    ( 25%)
Total Turbo logic cells used:                   69/192    ( 35%)
Total shareable expanders not available (n/a):  11/192    (  5%)
Average fan-in:                                  7.62
Total fan-in:                                   526

Total input pins required:                      57
Total fast input logic cells required:           0
Total output pins required:                     40
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     69
Total flipflops required:                       33
Total pterms required:                         257
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          41

Synthesized logic cells:                         0/ 192   (  0%)



Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  43   (69)  (E)      INPUT              0      0   0    0    0    4    0  brkAck
  38   (73)  (E)      INPUT              0      0   0    0    0    1    0  busw
  58   (85)  (F)      INPUT              0      0   0    0    0    1    0  cpenas
  53   (86)  (F)      INPUT              0      0   0    0    0    3    0  cpends
  24   (61)  (D)      INPUT              0      0   0    0    0    1    0  disnrdy
 147   (13)  (A)      INPUT              0      0   0    0    0   22    4  eDisCpu
 149   (11)  (A)      INPUT              0      0   0    0    0   10    6  emuspace
   5   (22)  (B)      INPUT              0      0   0    0    0    2    2  epAs
   4   (24)  (B)      INPUT              0      0   0    0    0    0    6  epA1
   2   (25)  (B)      INPUT              0      0   0    0    0    0    6  epA2
 159   (29)  (B)      INPUT              0      0   0    0    0    0    6  epA3
 158   (30)  (B)      INPUT              0      0   0    0    0    0    6  epA4
  21   (33)  (C)      INPUT              0      0   0    0    0    0    6  epA5
  15   (41)  (C)      INPUT              0      0   0    0    0    0    6  epA6
  17   (38)  (C)      INPUT              0      0   0    0    0    0    6  epA7
  19   (37)  (C)      INPUT              0      0   0    0    0    0    6  epA8
  20   (35)  (C)      INPUT              0      0   0    0    0    0    6  epA9
 157   (32)  (B)      INPUT              0      0   0    0    0    0    6  epA10
   8   (17)  (B)      INPUT              0      0   0    0    0    0    6  epA11
 160   (27)  (B)      INPUT              0      0   0    0    0    0    2  epDtack
  33   (49)  (D)      INPUT              0      0   0    0    0    0    1  epD5
  34   (80)  (E)      INPUT              0      0   0    0    0    0    1  epD6
  36   (77)  (E)      INPUT              0      0   0    0    0    0    1  epD8
  22   (64)  (D)      INPUT              0      0   0    0    0    0    1  epD9
  45   (65)  (E)      INPUT              0      0   0    0    0    0    1  epD10
  60   (81)  (F)      INPUT              0      0   0    0    0    0    4  epD15
 152    (6)  (A)      INPUT              0      0   0    0    0   19    4  epfc0
 151    (8)  (A)      INPUT              0      0   0    0    0   19    4  epfc1
 150    (9)  (A)      INPUT              0      0   0    0    0   19    4  epfc2
  51   (89)  (F)      INPUT              0      0   0    0    0    1    0  epGo
   7   (19)  (B)      INPUT              0      0   0    0    0    1    9  epHalt
 153    (5)  (A)      INPUT              0      0   0    0    0    9   17  epOe
 141      -   -       INPUT              0      0   0    0    0    2    9  epRst
  37   (75)  (E)      INPUT              0      0   0    0    0    3    0  epStop
 154    (3)  (A)      INPUT              0      0   0    0    0    8   22  epWeh
   6   (21)  (B)      INPUT              0      0   0    0    0    5   22  epWel
  13   (45)  (C)      INPUT              0      0   0    0    0    5    0  exRdy
 156    (1)  (A)      INPUT              0      0   0    0    0   10    6  iac
  14   (43)  (C)      INPUT              0      0   0    0    0    4    1  iceBrk
 139      -   -       INPUT              0      0   0    0    0    3    3  iceClk
  26   (59)  (D)      INPUT              0      0   0    0    0    1    0  iceRdy
   9   (48)  (C)      INPUT              0      0   0    0    0    2    0  isoep
  35   (78)  (E)      INPUT              0      0   0    0    0    1    0  nClrHalt
  41   (72)  (E)      INPUT              0      0   0    0    0    1    5  nCsActive_I
  42   (70)  (E)      INPUT              0      0   0    0    0    2    0  nemdfc
  44   (67)  (E)      INPUT              0      0   0    0    0    2    0  nemsfc
  27   (57)  (D)      INPUT              0      0   0    0    0    3    3  nenIpl
  28   (56)  (D)      INPUT              0      0   0    0    0    3    3  nenNMI
  31   (51)  (D)      INPUT              0      0   0    0    0    1    0  nFReset
  49   (93)  (F)      INPUT              0      0   0    0    0    3    0  ninshi
  29   (54)  (D)      INPUT              0      0   0    0    0    3    0  ninslow
 145   (16)  (A)      INPUT              0      0   0    0    0    9    0  nmhere
  50   (91)  (F)      INPUT              0      0   0    0    0    2    0  nRdOnly
  52   (88)  (F)      INPUT              0      0   0    0    0    1    0  Qual
  16   (40)  (C)      INPUT              0      0   0    0    0    1    1  tIpl0
  12   (46)  (C)      INPUT              0      0   0    0    0    1    1  tIpl1
  30   (53)  (D)      INPUT              0      0   0    0    0    1    1  tIpl2


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  62     99    G         FF     t        0      0   0    3    2   13   21  bmsk8
  69    104    G         FF     t        1      0   0    2    1    1    0  cHaltPin
  85    125    H     OUTPUT     t        2      0   1    9    1    0    0  dirpbdh
 104    150    J     OUTPUT     t        3      0   1   10    1    0    0  dirpbdl
 113    161    K     OUTPUT     t        0      0   0    1    2    0    0  dlyLds
 131    185    L         FF     t        0      0   0    2    0    0    0  dlyOe
 101    147    J     OUTPUT     t        0      0   0    1    3    0    0  dlyUds
 136    192    L         FF     t        0      0   0    2    0    0    0  dlyWeh
 125    177    L         FF     t        0      0   0    2    0    0    0  dlyWel
 100    145    J     OUTPUT     t        0      0   0    1    2    0    0  ep_A0
  91    133    I     OUTPUT     t        1      0   1    5    3    0    0  epIpl0
  99    144    I     OUTPUT     t        1      0   1    5    3    0    0  epIpl1
  97    141    I     OUTPUT     t        1      0   0    5    3    0    0  epIpl2
 116    166    K         FF  +  t        8      1   0    8    9    1    0  Fdtack
 115    165    K         FF  +  t        0      0   0    2    6    1    0  flagNotRdy
 123    174    K     OUTPUT     t        0      0   0    1    0    0    0  nadvalid
  87    128    H     OUTPUT     t        0      0   0    0    3    0    0  ndatavalid
  92    134    I     OUTPUT     t        0      0   0    4    0    0    0  nDma
  93    136    I     OUTPUT     t        0      0   0    5    0    0    0  nemdfcc
  94    137    I     OUTPUT     t        0      0   0    5    0    0    0  nemsfcc
 130    184    L     OUTPUT     t/       2      0   1    7    2    0    0  nemvalid
  95    139    I     OUTPUT     t        0      0   0    6    0    0    0  nenepfc
 112    160    J     OUTPUT     t        0      0   0    6    1    0    0  nenHiByteO
 105    152    J     OUTPUT     t        0      0   0    6    0    0    0  nenLowByteO
  90    131    I     OUTPUT     t        0      0   0    1    0    0    0  nenpba
 108    157    J     OUTPUT     t        0      0   0    7    0    0    0  nenpbd
  77    115    H     OUTPUT     t        2      1   1   10    0    0    0  nentas
  76    113    H     OUTPUT     t        0      0   0    5    0    0    0  nenTcs
 109    158    J     OUTPUT     t        2      0   1    8    1    0    0  nentdh
 106    153    J     OUTPUT     t        2      0   1    9    1    0    0  nentdl
  83    121    H     OUTPUT     t        2      1   1   10    0    0    0  nentoe
  80    120    H     OUTPUT     t        4      2   1   11    1    0    0  nentweh
  79    118    H     OUTPUT     t        3      2   1   11    0    0    0  nentwel
  78    117    H     OUTPUT     t        0      0   0    1    0    0    0  nerd
 127    179    L     OUTPUT     t        0      0   0    2    1    0    0  newr
  88    129    I     OUTPUT     t        0      0   0    1    1    0    0  nFHalt
  86    126    H     OUTPUT     t        0      0   0    6    0    0    0  nmemreq
 129    182    L     OUTPUT     t        0      0   0    5    0    0    0  nselepfc
 128    181    L     OUTPUT     t        0      0   0    3    1    0    0  nstrobe
  84    123    H     OUTPUT     t        0      0   0    1    2    0    0  nstsvalid


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     87    F       DFFE     t        2      2   0   16    1    1    0  bsw
 (60)    81    F       DFFE     t        2      2   0   16    1    1    0  bswen
   -    178    L       DFFE     t        9      9   0    9    3    1    0  chgMode
   -    154    J       DFFE     t        2      2   0   18    1    2    0  dedicatedMode
   -    191    L       DFFE     t        9      9   0    9    2    0    1  delBmsk8
   -    183    L       DFFE     t        9      9   0    8    2    0    1  dlyIceBrk0
(135)   190    L       DFFE     t        9      9   0    7    3    1    0  dlyIceBrk1
   -    186    L       DFFE     t        2      0   0    5    2    2    2  |DVALID:SDvalid|:1
   -    148    J       DFFE  +  t        0      0   0    1    0    0    1  |DVALID:SDvalid|:17
   -    132    I       DFFE  +  t        0      0   0    1    2    2    2  |DVALID:SDvalid|:21
   -    138    I       DFFE  +  t        0      0   0    1    2    1    0  |DVALID:SDvalid|:37
 (29)    54    D       DFFE     t        2      2   0   19    1    1    0  et1reg
 (21)    33    C       DFFE     t        2      2   0   19    1    1    0  et6reg
 (45)    65    E       DFFE     t        2      2   0   19    1    1    0  et7reg
   -    172    K       DFFE     t        1      0   0    3    0    2    0  indlyLds
   -    164    K       DFFE     t        1      0   0    3    0    2    0  indlyUds
(134)   189    L       TFFE  +  t        1      1   0    3    5    0    4  iwct0
   -    188    L       DFFE  +  t        1      1   0    3    5    0    4  iwct1
(132)   187    L       TFFE  +  t        1      1   0    3    5    1    4  iwct2
   -    180    L       TFFE  +  t        1      1   0    3    5    1    4  iwct3
   -    140    I      LCELL     t        1      1   0    5    1    1    1  lIpl0
   -    135    I      LCELL     t        1      1   0    5    1    1    1  lIpl1
   -    143    I      LCELL     t        1      1   0    5    1    1    1  lIpl2
   -    156    J       DFFE  +  t        0      0   0    3    1    1    4  nstrobeDly
   -    175    K       TFFE  +  t        3      3   0    4    1    2    4  wct0
(124)   176    K       TFFE  +  t        3      3   0    4    2    2    3  wct1
(114)   163    K       TFFE  +  t        3      3   0    4    3    2    2  wct2
   -    167    K       TFFE  +  t        3      3   0    4    4    2    1  wct3
(117)   168    K       TFFE  +  t        3      3   0    4    5    2    0  wct4


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

           Logic cells placed in LAB 'C'
        +- LC33 et6reg
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'C'
LC      | | A B C D E F G H I J K L |     Logic cells that feed LAB 'C':

Pin
149  -> * | - - * * * * - * - * - - | <-- emuspace
4    -> * | - - * * * * - - - * - - | <-- epA1
2    -> * | - - * * * * - - - * - - | <-- epA2
159  -> * | - - * * * * - - - * - - | <-- epA3
158  -> * | - - * * * * - - - * - - | <-- epA4
21   -> * | - - * * * * - - - * - - | <-- epA5
15   -> * | - - * * * * - - - * - - | <-- epA6
17   -> * | - - * * * * - - - * - - | <-- epA7
19   -> * | - - * * * * - - - * - - | <-- epA8
20   -> * | - - * * * * - - - * - - | <-- epA9
157  -> * | - - * * * * - - - * - - | <-- epA10
8    -> * | - - * * * * - - - * - - | <-- epA11
22   -> * | - - * - - - - - - - - - | <-- epD9
60   -> * | - - * * * - - - - * - - | <-- epD15
7    -> * | - - * * * - * - * * - * | <-- epHalt
141  -> * | - - * * * - * - * * - * | <-- epRst
154  -> * | - - * * * * - - - * * * | <-- epWeh
6    -> * | - - * * * * - - - * * * | <-- epWel
156  -> * | - - * * * * - * - * * - | <-- iac
139  -> - | - - - - - - - - - - * * | <-- iceClk
LC99 -> * | - - * * * * - * - * * * | <-- bmsk8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

           Logic cells placed in LAB 'D'
        +- LC54 et1reg
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'D'
LC      | | A B C D E F G H I J K L |     Logic cells that feed LAB 'D':

Pin
149  -> * | - - * * * * - * - * - - | <-- emuspace
4    -> * | - - * * * * - - - * - - | <-- epA1
2    -> * | - - * * * * - - - * - - | <-- epA2
159  -> * | - - * * * * - - - * - - | <-- epA3
158  -> * | - - * * * * - - - * - - | <-- epA4
21   -> * | - - * * * * - - - * - - | <-- epA5
15   -> * | - - * * * * - - - * - - | <-- epA6
17   -> * | - - * * * * - - - * - - | <-- epA7
19   -> * | - - * * * * - - - * - - | <-- epA8
20   -> * | - - * * * * - - - * - - | <-- epA9
157  -> * | - - * * * * - - - * - - | <-- epA10
8    -> * | - - * * * * - - - * - - | <-- epA11
36   -> * | - - - * - - - - - - - - | <-- epD8
60   -> * | - - * * * - - - - * - - | <-- epD15
7    -> * | - - * * * - * - * * - * | <-- epHalt
141  -> * | - - * * * - * - * * - * | <-- epRst
154  -> * | - - * * * * - - - * * * | <-- epWeh
6    -> * | - - * * * * - - - * * * | <-- epWel
156  -> * | - - * * * * - * - * * - | <-- iac
139  -> - | - - - - - - - - - - * * | <-- iceClk
LC99 -> * | - - * * * * - * - * * * | <-- bmsk8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

           Logic cells placed in LAB 'E'
        +- LC65 et7reg
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'E'
LC      | | A B C D E F G H I J K L |     Logic cells that feed LAB 'E':

Pin
149  -> * | - - * * * * - * - * - - | <-- emuspace
4    -> * | - - * * * * - - - * - - | <-- epA1
2    -> * | - - * * * * - - - * - - | <-- epA2
159  -> * | - - * * * * - - - * - - | <-- epA3
158  -> * | - - * * * * - - - * - - | <-- epA4
21   -> * | - - * * * * - - - * - - | <-- epA5
15   -> * | - - * * * * - - - * - - | <-- epA6
17   -> * | - - * * * * - - - * - - | <-- epA7
19   -> * | - - * * * * - - - * - - | <-- epA8
20   -> * | - - * * * * - - - * - - | <-- epA9
157  -> * | - - * * * * - - - * - - | <-- epA10
8    -> * | - - * * * * - - - * - - | <-- epA11
45   -> * | - - - - * - - - - - - - | <-- epD10
60   -> * | - - * * * - - - - * - - | <-- epD15
7    -> * | - - * * * - * - * * - * | <-- epHalt
141  -> * | - - * * * - * - * * - * | <-- epRst
154  -> * | - - * * * * - - - * * * | <-- epWeh
6    -> * | - - * * * * - - - * * * | <-- epWel
156  -> * | - - * * * * - * - * * - | <-- iac
139  -> - | - - - - - - - - - - * * | <-- iceClk
LC99 -> * | - - * * * * - * - * * * | <-- bmsk8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

             Logic cells placed in LAB 'F'
        +--- LC87 bsw
        | +- LC81 bswen
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'F'
LC      | | | A B C D E F G H I J K L |     Logic cells that feed LAB 'F':

Pin
149  -> * * | - - * * * * - * - * - - | <-- emuspace
4    -> * * | - - * * * * - - - * - - | <-- epA1
2    -> * * | - - * * * * - - - * - - | <-- epA2
159  -> * * | - - * * * * - - - * - - | <-- epA3
158  -> * * | - - * * * * - - - * - - | <-- epA4
21   -> * * | - - * * * * - - - * - - | <-- epA5
15   -> * * | - - * * * * - - - * - - | <-- epA6
17   -> * * | - - * * * * - - - * - - | <-- epA7
19   -> * * | - - * * * * - - - * - - | <-- epA8
20   -> * * | - - * * * * - - - * - - | <-- epA9
157  -> * * | - - * * * * - - - * - - | <-- epA10
8    -> * * | - - * * * * - - - * - - | <-- epA11
33   -> - * | - - - - - * - - - - - - | <-- epD5
34   -> * - | - - - - - * - - - - - - | <-- epD6
141  -> - - | - - * * * - * - * * - * | <-- epRst
154  -> * * | - - * * * * - - - * * * | <-- epWeh
6    -> * * | - - * * * * - - - * * * | <-- epWel
156  -> * * | - - * * * * - * - * * - | <-- iac
139  -> - - | - - - - - - - - - - * * | <-- iceClk
LC99 -> * * | - - * * * * - * - * * * | <-- bmsk8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

             Logic cells placed in LAB 'G'
        +--- LC99 bmsk8
        | +- LC104 cHaltPin
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'G'
LC      | | | A B C D E F G H I J K L |     Logic cells that feed LAB 'G':

Pin
38   -> * - | - - - - - - * - - - - - | <-- busw
7    -> * - | - - * * * - * - * * - * | <-- epHalt
141  -> * * | - - * * * - * - * * - * | <-- epRst
139  -> - - | - - - - - - - - - - * * | <-- iceClk
35   -> - * | - - - - - - * - - - - - | <-- nClrHalt
LC87 -> * - | - - - - - - * - - - - - | <-- bsw
LC81 -> * - | - - - - - - * - - - - - | <-- bswen
LC178-> - * | - - - - - - * - - - - - | <-- chgMode


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                             Logic cells placed in LAB 'H'
        +------------------- LC125 dirpbdh
        | +----------------- LC128 ndatavalid
        | | +--------------- LC115 nentas
        | | | +------------- LC113 nenTcs
        | | | | +----------- LC121 nentoe
        | | | | | +--------- LC120 nentweh
        | | | | | | +------- LC118 nentwel
        | | | | | | | +----- LC117 nerd
        | | | | | | | | +--- LC126 nmemreq
        | | | | | | | | | +- LC123 nstsvalid
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | A B C D E F G H I J K L |     Logic cells that feed LAB 'H':

Pin
43   -> - - * - * * * - - - | - - - - - - - * - - - - | <-- brkAck
58   -> - - * - - - - - - - | - - - - - - - * - - - - | <-- cpenas
53   -> - - - - * * * - - - | - - - - - - - * - - - - | <-- cpends
147  -> * - * * * * * - * - | - - - - - - - * * * - * | <-- eDisCpu
149  -> * - * * * * * - * - | - - * * * * - * - * - - | <-- emuspace
152  -> * - * * * * * - * - | - - - - - - - * * * - * | <-- epfc0
151  -> * - * * * * * - * - | - - - - - - - * * * - * | <-- epfc1
150  -> * - * * * * * - * - | - - - - - - - * * * - * | <-- epfc2
153  -> * - - - - - - * - - | - - - - - - - * - * * * | <-- epOe
141  -> - - - - - - - - - - | - - * * * - * - * * - * | <-- epRst
13   -> - - * - * * * - - - | - - - - - - - * - - * - | <-- exRdy
156  -> * - * - * * * - * - | - - * * * * - * - * * - | <-- iac
139  -> - - - - - - - - - - | - - - - - - - - - - * * | <-- iceClk
29   -> * - - - - - - - - - | - - - - - - - * - * - - | <-- ninslow
145  -> * - * - * * * - - - | - - - - - - - * - * * - | <-- nmhere
50   -> - - - - - * * - - - | - - - - - - - * - - - - | <-- nRdOnly
52   -> - - - - - - - - - * | - - - - - - - * - - - - | <-- Qual
LC99 -> * - - - - * - - - - | - - * * * * - * - * * * | <-- bmsk8
LC186-> - * - - - - - - - * | - - - - - - - * * - - * | <-- |DVALID:SDvalid|:1
LC132-> - * - - - - - - - * | - - - - - - - * * - - - | <-- |DVALID:SDvalid|:21
LC138-> - * - - - - - - - - | - - - - - - - * - - - - | <-- |DVALID:SDvalid|:37


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'I':

                                     Logic cells placed in LAB 'I'
        +--------------------------- LC132 |DVALID:SDvalid|:21
        | +------------------------- LC138 |DVALID:SDvalid|:37
        | | +----------------------- LC133 epIpl0
        | | | +--------------------- LC144 epIpl1
        | | | | +------------------- LC141 epIpl2
        | | | | | +----------------- LC140 lIpl0
        | | | | | | +--------------- LC135 lIpl1
        | | | | | | | +------------- LC143 lIpl2
        | | | | | | | | +----------- LC134 nDma
        | | | | | | | | | +--------- LC136 nemdfcc
        | | | | | | | | | | +------- LC137 nemsfcc
        | | | | | | | | | | | +----- LC139 nenepfc
        | | | | | | | | | | | | +--- LC131 nenpba
        | | | | | | | | | | | | | +- LC129 nFHalt
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'I'
LC      | | | | | | | | | | | | | | | A B C D E F G H I J K L |     Logic cells that feed LAB 'I':
LC132-> * * - - - - - - - - - - - - | - - - - - - - * * - - - | <-- |DVALID:SDvalid|:21
LC140-> - - * - - * - - - - - - - - | - - - - - - - - * - - - | <-- lIpl0
LC135-> - - - * - - * - - - - - - - | - - - - - - - - * - - - | <-- lIpl1
LC143-> - - - - * - - * - - - - - - | - - - - - - - - * - - - | <-- lIpl2

Pin
147  -> - - * * * - - - * * * * - - | - - - - - - - * * * - * | <-- eDisCpu
5    -> - * - - - - - - - - - - - - | - - - - - - - - * * * * | <-- epAs
160  -> * - - - - - - - - - - - - - | - - - - - - - - * - - * | <-- epDtack
152  -> - - - - - - - - * * * * - - | - - - - - - - * * * - * | <-- epfc0
151  -> - - - - - - - - * * * * - - | - - - - - - - * * * - * | <-- epfc1
150  -> - - - - - - - - * * * * - - | - - - - - - - * * * - * | <-- epfc2
7    -> - - - - - * * * - - - - - - | - - * * * - * - * * - * | <-- epHalt
141  -> - - - - - * * * - - - - - - | - - * * * - * - * * - * | <-- epRst
14   -> - - * * * - - - - - - - - - | - - - - - - - - * - - * | <-- iceBrk
139  -> - - - - - - - - - - - - - - | - - - - - - - - - - * * | <-- iceClk
9    -> - - - - - - - - - - - - * - | - - - - - - - - * * - - | <-- isoep
42   -> - - - - - - - - - * - * - - | - - - - - - - - * - - - | <-- nemdfc
44   -> - - - - - - - - - - * * - - | - - - - - - - - * - - - | <-- nemsfc
27   -> - - * * * * * * - - - - - - | - - - - - - - - * - - - | <-- nenIpl
28   -> - - * * * * * * - - - - - - | - - - - - - - - * - - - | <-- nenNMI
31   -> - - - - - - - - - - - - - * | - - - - - - - - * - - - | <-- nFReset
16   -> - - * - - * - - - - - - - - | - - - - - - - - * - - - | <-- tIpl0
12   -> - - - * - - * - - - - - - - | - - - - - - - - * - - - | <-- tIpl1
30   -> - - - - * - - * - - - - - - | - - - - - - - - * - - - | <-- tIpl2
LC104-> - - - - - - - - - - - - - * | - - - - - - - - * - - - | <-- cHaltPin
LC154-> - - * * - - - - - - - - - - | - - - - - - - - * - - - | <-- dedicatedMode
LC190-> - - - - * - - - - - - - - - | - - - - - - - - * - - - | <-- dlyIceBrk1
LC186-> - * - - - - - - - - - - - - | - - - - - - - * * - - * | <-- |DVALID:SDvalid|:1
LC148-> * - - - - - - - - - - - - - | - - - - - - - - * - - - | <-- |DVALID:SDvalid|:17
LC54 -> - - * - - - - - - - - - - - | - - - - - - - - * - - - | <-- et1reg
LC33 -> - - - * - - - - - - - - - - | - - - - - - - - * - - - | <-- et6reg
LC65 -> - - - - * - - - - - - - - - | - - - - - - - - * - - - | <-- et7reg


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'J':

                               Logic cells placed in LAB 'J'
        +--------------------- LC154 dedicatedMode
        | +------------------- LC150 dirpbdl
        | | +----------------- LC147 dlyUds
        | | | +--------------- LC148 |DVALID:SDvalid|:17
        | | | | +------------- LC145 ep_A0
        | | | | | +----------- LC160 nenHiByteO
        | | | | | | +--------- LC152 nenLowByteO
        | | | | | | | +------- LC157 nenpbd
        | | | | | | | | +----- LC158 nentdh
        | | | | | | | | | +--- LC153 nentdl
        | | | | | | | | | | +- LC156 nstrobeDly
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'J'
LC      | | | | | | | | | | | | A B C D E F G H I J K L |     Logic cells that feed LAB 'J':

Pin
147  -> - * - - - * * * * * - | - - - - - - - * * * - * | <-- eDisCpu
149  -> * * - - - - - - * * - | - - * * * * - * - * - - | <-- emuspace
5    -> - - - - - - - * - - - | - - - - - - - - * * * * | <-- epAs
4    -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA1
2    -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA2
159  -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA3
158  -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA4
21   -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA5
15   -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA6
17   -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA7
19   -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA8
20   -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA9
157  -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA10
8    -> * - - - - - - - - - - | - - * * * * - - - * - - | <-- epA11
60   -> * - - - - - - - - - - | - - * * * - - - - * - - | <-- epD15
152  -> - * - - - * * * * * - | - - - - - - - * * * - * | <-- epfc0
151  -> - * - - - * * * * * - | - - - - - - - * * * - * | <-- epfc1
150  -> - * - - - * * * * * - | - - - - - - - * * * - * | <-- epfc2
7    -> * - - - - - - - - - - | - - * * * - * - * * - * | <-- epHalt
153  -> - * - * - * * - - - * | - - - - - - - * - * * * | <-- epOe
141  -> * - - - - - - - - - - | - - * * * - * - * * - * | <-- epRst
37   -> - - - - - * * * - - - | - - - - - - - - - * - - | <-- epStop
154  -> * - * - * - - - - - * | - - * * * * - - - * * * | <-- epWeh
6    -> * - - - - - - - - - * | - - * * * * - - - * * * | <-- epWel
156  -> * * - - - - - - * * - | - - * * * * - * - * * - | <-- iac
139  -> - - - - - - - - - - - | - - - - - - - - - - * * | <-- iceClk
9    -> - - - - - - - * - - - | - - - - - - - - * * - - | <-- isoep
49   -> - * - - - - - - * * - | - - - - - - - - - * - - | <-- ninshi
29   -> - * - - - - - - - * - | - - - - - - - * - * - - | <-- ninslow
145  -> - * - - - - - - * * - | - - - - - - - * - * * - | <-- nmhere
LC99 -> * * * - * * - - * * * | - - * * * * - * - * * * | <-- bmsk8
LC172-> - - * - - - - - - - - | - - - - - - - - - * * - | <-- indlyLds
LC164-> - - * - * - - - - - - | - - - - - - - - - * - - | <-- indlyUds


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'K':

                               Logic cells placed in LAB 'K'
        +--------------------- LC161 dlyLds
        | +------------------- LC166 Fdtack
        | | +----------------- LC165 flagNotRdy
        | | | +--------------- LC172 indlyLds
        | | | | +------------- LC164 indlyUds
        | | | | | +----------- LC174 nadvalid
        | | | | | | +--------- LC175 wct0
        | | | | | | | +------- LC176 wct1
        | | | | | | | | +----- LC163 wct2
        | | | | | | | | | +--- LC167 wct3
        | | | | | | | | | | +- LC168 wct4
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'K'
LC      | | | | | | | | | | | | A B C D E F G H I J K L |     Logic cells that feed LAB 'K':
LC166-> - * - - - - - - - - - | - - - - - - - - - - * - | <-- Fdtack
LC165-> - - * - - - - - - - - | - - - - - - - - - - * - | <-- flagNotRdy
LC172-> * - - - - - - - - - - | - - - - - - - - - * * - | <-- indlyLds
LC175-> - * * - - - * * * * * | - - - - - - - - - - * - | <-- wct0
LC176-> - * * - - - - * * * * | - - - - - - - - - - * - | <-- wct1
LC163-> - * * - - - - - * * * | - - - - - - - - - - * - | <-- wct2
LC167-> - * * - - - - - - * * | - - - - - - - - - - * - | <-- wct3
LC168-> - * * - - - - - - - * | - - - - - - - - - - * - | <-- wct4

Pin
24   -> - - * - - - - - - - - | - - - - - - - - - - * - | <-- disnrdy
5    -> - - - - - * - - - - - | - - - - - - - - * * * * | <-- epAs
51   -> - - * - - - - - - - - | - - - - - - - - - - * - | <-- epGo
153  -> - * - * * - * * * * * | - - - - - - - * - * * * | <-- epOe
141  -> - - - - - - - - - - - | - - * * * - * - * * - * | <-- epRst
154  -> * * - - * - * * * * * | - - * * * * - - - * * * | <-- epWeh
6    -> - * - * - - * * * * * | - - * * * * - - - * * * | <-- epWel
13   -> - * - - - - - - - - - | - - - - - - - * - - * - | <-- exRdy
156  -> - * - - - - - - - - - | - - * * * * - * - * * - | <-- iac
139  -> - - - * * - - - - - - | - - - - - - - - - - * * | <-- iceClk
26   -> - * - - - - - - - - - | - - - - - - - - - - * - | <-- iceRdy
41   -> - * - - - - * * * * * | - - - - - - - - - - * - | <-- nCsActive_I
145  -> - * - - - - - - - - - | - - - - - - - * - * * - | <-- nmhere
LC99 -> * * - - - - * * * * * | - - * * * * - * - * * * | <-- bmsk8
LC187-> - * - - - - - - - - - | - - - - - - - - - - * * | <-- iwct2
LC180-> - * - - - - - - - - - | - - - - - - - - - - * * | <-- iwct3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'L':

                                         Logic cells placed in LAB 'L'
        +------------------------------- LC178 chgMode
        | +----------------------------- LC191 delBmsk8
        | | +--------------------------- LC183 dlyIceBrk0
        | | | +------------------------- LC190 dlyIceBrk1
        | | | | +----------------------- LC185 dlyOe
        | | | | | +--------------------- LC192 dlyWeh
        | | | | | | +------------------- LC177 dlyWel
        | | | | | | | +----------------- LC186 |DVALID:SDvalid|:1
        | | | | | | | | +--------------- LC189 iwct0
        | | | | | | | | | +------------- LC188 iwct1
        | | | | | | | | | | +----------- LC187 iwct2
        | | | | | | | | | | | +--------- LC180 iwct3
        | | | | | | | | | | | | +------- LC184 nemvalid
        | | | | | | | | | | | | | +----- LC179 newr
        | | | | | | | | | | | | | | +--- LC182 nselepfc
        | | | | | | | | | | | | | | | +- LC181 nstrobe
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'L'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H I J K L |     Logic cells that feed LAB 'L':
LC191-> * - - - - - - - - - - - - - - - | - - - - - - - - - - - * | <-- delBmsk8
LC183-> - - - * - - - - - - - - - - - - | - - - - - - - - - - - * | <-- dlyIceBrk0
LC186-> - - - - - - - * - - - - - - - - | - - - - - - - * * - - * | <-- |DVALID:SDvalid|:1
LC189-> - - - - - - - - * * * * - - - - | - - - - - - - - - - - * | <-- iwct0
LC188-> - - - - - - - - * * * * - - - - | - - - - - - - - - - - * | <-- iwct1
LC187-> - - - - - - - - * * * * - - - - | - - - - - - - - - - * * | <-- iwct2
LC180-> - - - - - - - - * * * * - - - - | - - - - - - - - - - * * | <-- iwct3

Pin
147  -> * * * * - - - - - - - - * - * - | - - - - - - - * * * - * | <-- eDisCpu
5    -> - - - - - - - * - - - - - - - - | - - - - - - - - * * * * | <-- epAs
160  -> - - - - - - - * - - - - - - - - | - - - - - - - - * - - * | <-- epDtack
152  -> * * * * - - - - - - - - * - * - | - - - - - - - * * * - * | <-- epfc0
151  -> * * * * - - - - - - - - * - * - | - - - - - - - * * * - * | <-- epfc1
150  -> * * * * - - - - - - - - * - * - | - - - - - - - * * * - * | <-- epfc2
7    -> * * - - - - - - - - - - - - - - | - - * * * - * - * * - * | <-- epHalt
153  -> * * * * * - - - * * * * * - - * | - - - - - - - * - * * * | <-- epOe
141  -> * * - - - - - - - - - - - - - - | - - * * * - * - * * - * | <-- epRst
154  -> * * * * - * - * * * * * * * - * | - - * * * * - - - * * * | <-- epWeh
6    -> * * * * - - * * * * * * * * - * | - - * * * * - - - * * * | <-- epWel
14   -> - - * - - - - - - - - - - - * - | - - - - - - - - * - - * | <-- iceBrk
139  -> - - - - * * * * - - - - - - - - | - - - - - - - - - - * * | <-- iceClk
LC99 -> * * * * - - - * * * * * * * - * | - - * * * * - * - * * * | <-- bmsk8
LC156-> * * * * - - - - - - - - * - - - | - - - - - - - - - - - * | <-- nstrobeDly


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\hdlc302\hd302lc1.rpt
hd302lc1

** EQUATIONS **

brkAck   : INPUT;
busw     : INPUT;
cpenas   : INPUT;
cpends   : INPUT;
disnrdy  : INPUT;
eDisCpu  : INPUT;
emuspace : INPUT;
epAs     : INPUT;
epA1     : INPUT;
epA2     : INPUT;
epA3     : INPUT;
epA4     : INPUT;
epA5     : INPUT;
epA6     : INPUT;
epA7     : INPUT;
epA8     : INPUT;
epA9     : INPUT;
epA10    : INPUT;
epA11    : INPUT;
epDtack  : INPUT;
epD5     : INPUT;
epD6     : INPUT;
epD8     : INPUT;
epD9     : INPUT;
epD10    : INPUT;
epD15    : INPUT;
epfc0    : INPUT;
epfc1    : INPUT;
epfc2    : INPUT;
epGo     : INPUT;
epHalt   : INPUT;
epOe     : INPUT;
epRst    : INPUT;
epStop   : INPUT;
epWeh    : INPUT;
epWel    : INPUT;
exRdy    : INPUT;
iac      : INPUT;
iceBrk   : INPUT;
iceClk   : INPUT;
iceRdy   : INPUT;
isoep    : INPUT;
nClrHalt : INPUT;
nCsActive_I : INPUT;
nemdfc   : INPUT;
nemsfc   : INPUT;
nenIpl   : INPUT;
nenNMI   : INPUT;
nFReset  : INPUT;
ninshi   : INPUT;
ninslow  : INPUT;
nmhere   : INPUT;
nRdOnly  : INPUT;
Qual     : INPUT;
tIpl0    : INPUT;
tIpl1    : INPUT;
tIpl2    : INPUT;

-- Node name is 'bmsk8' = 'bmsk8FF' from file "hd302lc1.tdf" line 167, column 1
-- Equation name is 'bmsk8', location is LC099, type is output.
 bmsk8   = DFFE(!bsw $  GND,  bswen, !_EQ001, !_EQ002,  VCC);
  _EQ001 =  busw & !epHalt & !epRst;
  _EQ002 = !busw & !epHalt & !epRst;

-- Node name is 'bsw' from file "hd302lc1.tdf" line 163, column 1
-- Equation name is 'bsw', location is LC087, type is buried.
bsw      = DFFE( epD6 $  GND,  _EQ003, GLOBAL( epRst),  VCC,  VCC);
  _EQ003 =  _X001 &  _X002;
  _X001  = EXP(!bmsk8 &  emuspace & !epA1 &  epA2 &  epA3 & !epA4 &  epA5 & !epA6 & 
             !epA7 & !epA8 & !epA9 & !epA10 &  epA11 & !epWeh &  iac);
  _X002  = EXP( emuspace & !epA1 &  epA2 &  epA3 & !epA4 &  epA5 & !epA6 & !epA7 & 
             !epA8 & !epA9 & !epA10 &  epA11 & !epWeh & !epWel &  iac);

-- Node name is 'bswen' from file "hd302lc1.tdf" line 162, column 1
-- Equation name is 'bswen', location is LC081, type is buried.
bswen    = DFFE( epD5 $  GND,  _EQ004, GLOBAL( epRst),  VCC,  VCC);
  _EQ004 =  _X001 &  _X002;
  _X001  = EXP(!bmsk8 &  emuspace & !epA1 &  epA2 &  epA3 & !epA4 &  epA5 & !epA6 & 
             !epA7 & !epA8 & !epA9 & !epA10 &  epA11 & !epWeh &  iac);
  _X002  = EXP( emuspace & !epA1 &  epA2 &  epA3 & !epA4 &  epA5 & !epA6 & !epA7 & 
             !epA8 & !epA9 & !epA10 &  epA11 & !epWeh & !epWel &  iac);

-- Node name is 'cHaltPin' = 'cHalt' from file "hd302lc1.tdf" line 165, column 1
-- Equation name is 'cHaltPin', location is LC104, type is output.
 cHaltPin = DFFE( GND $  VCC,  chgMode, !_EQ005,  VCC,  VCC);
  _EQ005 =  _X003;
  _X003  = EXP( epRst &  nClrHalt);

-- Node name is 'chgMode' from file "hd302lc1.tdf" line 166, column 1
-- Equation name is 'chgMode', location is LC178, type is buried.
chgMode  = DFFE( bmsk8 $  delBmsk8,  _EQ006, !_EQ007,  VCC,  VCC);
  _EQ006 =  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012;
  _X004  = EXP(!bmsk8 & !eDisCpu & !epfc0 &  epfc1 & !epWeh & !nstrobeDly);
  _X005  = EXP(!bmsk8 & !eDisCpu &  epfc1 &  epfc2 & !epWeh & !nstrobeDly);
  _X006  = EXP(!bmsk8 & !eDisCpu &  epfc0 & !epfc1 & !epWeh & !nstrobeDly);
  _X007  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epOe & !nstrobeDly);
  _X008  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epWel & !nstrobeDly);
  _X009  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epOe & !nstrobeDly);
  _X010  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epWel & !nstrobeDly);
  _X011  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epOe & !nstrobeDly);
  _X012  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epWel & !nstrobeDly);
  _EQ007 = !epHalt & !epRst;

-- Node name is 'dedicatedMode' from file "hd302lc1.tdf" line 133, column 1
-- Equation name is 'dedicatedMode', location is LC154, type is buried.
dedicatedMode = DFFE( epD15 $  GND,  _EQ008, !_EQ009,  VCC,  VCC);
  _EQ008 =  _X013 &  _X014;
  _X013  = EXP(!bmsk8 &  emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & 
             !epA7 & !epA8 & !epA9 & !epA10 &  epA11 & !epWeh &  iac);
  _X014  = EXP( emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & !epA7 & 
             !epA8 & !epA9 & !epA10 &  epA11 & !epWeh & !epWel &  iac);
  _EQ009 = !epHalt & !epRst;

-- Node name is 'delBmsk8' from file "hd302lc1.tdf" line 164, column 1
-- Equation name is 'delBmsk8', location is LC191, type is buried.
delBmsk8 = DFFE( bmsk8 $  GND,  _EQ010, !_EQ011, !_EQ012,  VCC);
  _EQ010 =  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012;
  _X004  = EXP(!bmsk8 & !eDisCpu & !epfc0 &  epfc1 & !epWeh & !nstrobeDly);
  _X005  = EXP(!bmsk8 & !eDisCpu &  epfc1 &  epfc2 & !epWeh & !nstrobeDly);
  _X006  = EXP(!bmsk8 & !eDisCpu &  epfc0 & !epfc1 & !epWeh & !nstrobeDly);
  _X007  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epOe & !nstrobeDly);
  _X008  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epWel & !nstrobeDly);
  _X009  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epOe & !nstrobeDly);
  _X010  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epWel & !nstrobeDly);
  _X011  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epOe & !nstrobeDly);
  _X012  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epWel & !nstrobeDly);
  _EQ011 = !bmsk8 & !epHalt & !epRst;
  _EQ012 =  bmsk8 & !epHalt & !epRst;

-- Node name is 'dirpbdh' 
-- Equation name is 'dirpbdh', location is LC125, type is output.
 dirpbdh = LCELL( _EQ013 $  _EQ014);
  _EQ013 = !bmsk8 &  epfc0 &  epfc1 & !epfc2 & !epOe & !iac &  nmhere
         # !bmsk8 &  emuspace & !epOe & !iac &  ninslow &  nmhere
         # !bmsk8 & !epfc0 & !epfc1 & !epOe & !iac &  nmhere
         # !bmsk8 &  eDisCpu & !epOe & !iac &  nmhere;
  _EQ014 =  _X015;
  _X015  = EXP(!bmsk8 & !epOe & !iac);

-- Node name is 'dirpbdl' 
-- Equation name is 'dirpbdl', location is LC150, type is output.
 dirpbdl = LCELL( _EQ015 $  GND);
  _EQ015 =  emuspace &  ninshi &  nmhere &  _X016
         #  epfc0 &  epfc1 & !epfc2 &  nmhere
         # !epfc0 & !epfc1 &  nmhere
         #  eDisCpu &  nmhere
         #  _X017;
  _X016  = EXP( bmsk8 & !ninslow);
  _X017  = EXP(!epOe & !iac);

-- Node name is 'dlyIceBrk0' from file "hd302lc1.tdf" line 130, column 10
-- Equation name is 'dlyIceBrk0', location is LC183, type is buried.
dlyIceBrk0 = DFFE( iceBrk $  GND,  _EQ016,  VCC,  VCC,  VCC);
  _EQ016 =  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012;
  _X004  = EXP(!bmsk8 & !eDisCpu & !epfc0 &  epfc1 & !epWeh & !nstrobeDly);
  _X005  = EXP(!bmsk8 & !eDisCpu &  epfc1 &  epfc2 & !epWeh & !nstrobeDly);
  _X006  = EXP(!bmsk8 & !eDisCpu &  epfc0 & !epfc1 & !epWeh & !nstrobeDly);
  _X007  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epOe & !nstrobeDly);
  _X008  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epWel & !nstrobeDly);
  _X009  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epOe & !nstrobeDly);
  _X010  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epWel & !nstrobeDly);
  _X011  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epOe & !nstrobeDly);
  _X012  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epWel & !nstrobeDly);

-- Node name is 'dlyIceBrk1' from file "hd302lc1.tdf" line 130, column 10
-- Equation name is 'dlyIceBrk1', location is LC190, type is buried.
dlyIceBrk1 = DFFE( dlyIceBrk0 $  GND,  _EQ017,  VCC,  VCC,  VCC);
  _EQ017 =  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012;
  _X004  = EXP(!bmsk8 & !eDisCpu & !epfc0 &  epfc1 & !epWeh & !nstrobeDly);
  _X005  = EXP(!bmsk8 & !eDisCpu &  epfc1 &  epfc2 & !epWeh & !nstrobeDly);
  _X006  = EXP(!bmsk8 & !eDisCpu &  epfc0 & !epfc1 & !epWeh & !nstrobeDly);
  _X007  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epOe & !nstrobeDly);
  _X008  = EXP(!eDisCpu &  epfc1 &  epfc2 & !epWel & !nstrobeDly);
  _X009  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epOe & !nstrobeDly);
  _X010  = EXP(!eDisCpu & !epfc0 &  epfc1 & !epWel & !nstrobeDly);
  _X011  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epOe & !nstrobeDly);
  _X012  = EXP(!eDisCpu &  epfc0 & !epfc1 & !epWel & !nstrobeDly);

-- Node name is 'dlyLds' 
-- Equation name is 'dlyLds', location is LC161, type is output.
 dlyLds  = LCELL( _EQ018 $  indlyLds);
  _EQ018 =  bmsk8 & !epWeh & !indlyLds;

-- Node name is 'dlyOe' = 'indlyOe' from file "hd302lc1.tdf" line 169, column 1
-- Equation name is 'dlyOe', location is LC185, type is output.
 dlyOe   = DFFE( GND $  VCC, !iceClk,  epOe,  VCC,  VCC);

-- Node name is 'dlyUds' 
-- Equation name is 'dlyUds', location is LC147, type is output.
 dlyUds  = LCELL( _EQ019 $  bmsk8);
  _EQ019 =  bmsk8 & !epWeh & !indlyLds
         # !bmsk8 &  indlyUds;

-- Node name is 'dlyWeh' = 'indlyWeh' from file "hd302lc1.tdf" line 171, column 1
-- Equation name is 'dlyWeh', location is LC192, type is output.
 dlyWeh  = DFFE( GND $  VCC, !iceClk,  epWeh,  VCC,  VCC);

-- Node name is 'dlyWel' = 'indlyWel' from file "hd302lc1.tdf" line 170, column 1
-- Equation name is 'dlyWel', location is LC177, type is output.
 dlyWel  = DFFE( GND $  VCC, !iceClk,  epWel,  VCC,  VCC);

-- Node name is 'ep_A0' 
-- Equation name is 'ep_A0', location is LC145, type is output.
 ep_A0   = LCELL( _EQ020 $  GND);
  _EQ020 =  bmsk8 &  epWeh
         # !bmsk8 &  indlyUds;

-- Node name is 'epIpl0' 
-- Equation name is 'epIpl0', location is LC133, type is output.
 epIpl0  = LCELL( _EQ021 $ !eDisCpu);
  _EQ021 = !eDisCpu & !et1reg & !nenIpl & !nenNMI & !tIpl0
         # !dedicatedMode & !eDisCpu & !et1reg &  iceBrk
         # !eDisCpu &  et1reg & !lIpl0
         #  eDisCpu &  tIpl0;

-- Node name is 'epIpl1' 
-- Equation name is 'epIpl1', location is LC144, type is output.
 epIpl1  = LCELL( _EQ022 $ !eDisCpu);
  _EQ022 = !eDisCpu & !et6reg & !nenIpl & !nenNMI & !tIpl1
         # !dedicatedMode & !eDisCpu & !et6reg &  iceBrk
         # !eDisCpu &  et6reg & !lIpl1
         #  eDisCpu &  tIpl1;

-- Node name is 'epIpl2' 
-- Equation name is 'epIpl2', location is LC141, type is output.
 epIpl2  = LCELL( _EQ023 $  VCC);
  _EQ023 = !eDisCpu &  et7reg & !lIpl2 & !nenIpl & !nenNMI
         # !et7reg & !nenIpl & !nenNMI & !tIpl2
         # !eDisCpu &  iceBrk &  _X018
         #  eDisCpu & !tIpl2;
  _X018  = EXP( dlyIceBrk1 &  et7reg &  lIpl2);

-- Node name is 'et1reg' from file "hd302lc1.tdf" line 136, column 1
-- Equation name is 'et1reg', location is LC054, type is buried.
et1reg   = DFFE( _EQ024 $  GND,  _EQ025, !_EQ026,  VCC,  VCC);
  _EQ024 =  epD8 &  epD15;
  _EQ025 =  _X013 &  _X014;
  _X013  = EXP(!bmsk8 &  emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & 
             !epA7 & !epA8 & !epA9 & !epA10 &  epA11 & !epWeh &  iac);
  _X014  = EXP( emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & !epA7 & 
             !epA8 & !epA9 & !epA10 &  epA11 & !epWeh & !epWel &  iac);
  _EQ026 = !epHalt & !epRst;

-- Node name is 'et6reg' from file "hd302lc1.tdf" line 135, column 1
-- Equation name is 'et6reg', location is LC033, type is buried.
et6reg   = DFFE( _EQ027 $  GND,  _EQ028, !_EQ029,  VCC,  VCC);
  _EQ027 =  epD9 &  epD15;
  _EQ028 =  _X013 &  _X014;
  _X013  = EXP(!bmsk8 &  emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & 
             !epA7 & !epA8 & !epA9 & !epA10 &  epA11 & !epWeh &  iac);
  _X014  = EXP( emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & !epA7 & 
             !epA8 & !epA9 & !epA10 &  epA11 & !epWeh & !epWel &  iac);
  _EQ029 = !epHalt & !epRst;

-- Node name is 'et7reg' from file "hd302lc1.tdf" line 134, column 1
-- Equation name is 'et7reg', location is LC065, type is buried.
et7reg   = DFFE( _EQ030 $  GND,  _EQ031, !_EQ032,  VCC,  VCC);
  _EQ030 =  epD10 &  epD15;
  _EQ031 =  _X013 &  _X014;
  _X013  = EXP(!bmsk8 &  emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & 
             !epA7 & !epA8 & !epA9 & !epA10 &  epA11 & !epWeh &  iac);
  _X014  = EXP( emuspace &  epA1 & !epA2 & !epA3 &  epA4 & !epA5 & !epA6 & !epA7 & 
             !epA8 & !epA9 & !epA10 &  epA11 & !epWeh & !epWel &  iac);
  _EQ032 = !epHalt & !epRst;

-- Node name is 'Fdtack' = 'forceDtack' from file "hd302lc1.tdf" line 155, column 1
-- Equation name is 'Fdtack', location is LC166, type is output.
 Fdtack  = DFFE( _EQ033 $  VCC, GLOBAL( iceClk), !_EQ034,  VCC,  VCC);
  _EQ033 = !Fdtack &  _X019 &  _X020 &  _X021 &  _X022 &  _X023 &  _X024 & 
              _X025;
  _X019  = EXP( wct0 &  wct1 &  wct2 &  wct3 &  wct4);
  _X020  = EXP(!exRdy & !iac &  iwct2 &  iwct3 & !nCsActive_I & !nmhere);
  _X021  = EXP(!exRdy & !iac &  iwct3 &  nCsActive_I & !nmhere);
  _X022  = EXP(!exRdy & !iac &  iwct2 &  nCsActive_I & !nmhere);
  _X023  = EXP( iceRdy &  iwct2 &  iwct3 & !nCsActive_I);
  _X024  = EXP( iceRdy &  iwct3 &  nCsActive_I);
  _X025  = EXP( iceRdy &  iwct2 &  nCsActive_I);
  _EQ034 =  epOe &  epWel &  _X026;
  _X026  = EXP(!bmsk8 & !epWeh);

-- Node name is 'flagNotRdy' = 'flagNotRdyFF' from file "hd302lc1.tdf" line 154, column 1
-- Equation name is 'flagNotRdy', location is LC165, type is output.
 flagNotRdy = TFFE( _EQ035, GLOBAL( iceClk), !epGo,  VCC,  VCC);
  _EQ035 = !disnrdy & !flagNotRdy &  wct0 &  wct1 &  wct2 &  wct3 &  wct4;

-- Node name is 'indlyLds' from file "hd302lc1.tdf" line 143, column 1
-- Equation name is 'indlyLds', location is LC172, type is buried.
indlyLds = DFFE( GND $  VCC, !iceClk, !_EQ036,  VCC,  VCC);
  _EQ036 =  _X027;
  _X027  = EXP( epOe &  epWel);

-- Node name is 'indlyUds' from file "hd302lc1.tdf" line 142, column 1
-- Equation name is 'indlyUds', location is LC164, type is buried.
indlyUds = DFFE( GND $  VCC, !iceClk, !_EQ037,  VCC,  VCC);
  _EQ037 =  _X028;
  _X028  = EXP( epOe &  epWeh);

-- Node name is 'iwct0' from file "hd302lc1.tdf" line 157, column 5
-- Equation name is 'iwct0', location is LC189, type is buried.
iwct0    = TFFE(!_EQ038, GLOBAL( iceClk), !_EQ039,  VCC,  VCC);
  _EQ038 =  iwct0 &  iwct1 &  iwct2 &  iwct3;
  _EQ039 =  epOe &  epWel &  _X026;
  _X026  = EXP(!bmsk8 & !epWeh);

-- Node name is 'iwct1' from file "hd302lc1.tdf" line 157, column 5
-- Equation name is 'iwct1', location is LC188, type is buried.
iwct1    = DFFE( _EQ040 $  GND, GLOBAL( iceClk), !_EQ041,  VCC,  VCC);
  _EQ040 =  iwct0 &  iwct1 &  iwct2 &  iwct3
         # !iwct0 &  iwct1
         #  iwct0 & !iwct1;
  _EQ041 =  epOe &  epWel &  _X026;
  _X026  = EXP(!bmsk8 & !epWeh);

-- Node name is 'iwct2' from file "hd302lc1.tdf" line 157, column 5
-- Equation name is 'iwct2', location is LC187, type is buried.
iwct2    = TFFE( _EQ042, GLOBAL( iceClk), !_EQ043,  VCC,  VCC);
  _EQ042 =  iwct0 &  iwct1 &  iwct2 & !iwct3
         #  iwct0 &  iwct1 & !iwct2;
  _EQ043 =  epOe &  epWel &  _X026;
  _X026  = EXP(!bmsk8 & !epWeh);

-- Node name is 'iwct3' from file "hd302lc1.tdf" line 157, column 5
-- Equation name is 'iwct3', location is LC180, type is buried.
iwct3    = TFFE( _EQ044, GLOBAL( iceClk), !_EQ045,  VCC,  VCC);
  _EQ044 =  iwct0 &  iwct1 &  iwct2 & !iwct3;
  _EQ045 =  epOe &  epWel &  _X026;
  _X026  = EXP(!bmsk8 & !epWeh);

-- Node name is 'lIpl0' from file "hd302lc1.tdf" line 233, column 11
-- Equation name is 'lIpl0', location is LC140, type is buried.
lIpl0    = LCELL( _EQ046 $  GND);
  _EQ046 =  lIpl0 &  nenIpl &  _X029
         #  lIpl0 &  nenNMI &  _X029
         # !epHalt & !epRst &  tIpl0
         # !nenIpl & !nenNMI &  tIpl0;
  _X029  = EXP(!epHalt & !epRst);

-- Node name is 'lIpl1' from file "hd302lc1.tdf" line 234, column 11
-- Equation name is 'lIpl1', location is LC135, type is buried.
lIpl1    = LCELL( _EQ047 $  GND);
  _EQ047 =  lIpl1 &  nenIpl &  _X029
         #  lIpl1 &  nenNMI &  _X029
         # !epHalt & !epRst &  tIpl1
         # !nenIpl & !nenNMI &  tIpl1;
  _X029  = EXP(!epHalt & !epRst);

-- Node name is 'lIpl2' from file "hd302lc1.tdf" line 235, column 11
-- Equation name is 'lIpl2', location is LC143, type is buried.
lIpl2    = LCELL( _EQ048 $  GND);
  _EQ048 =  lIpl2 &  nenIpl &  _X029
         #  lIpl2 &  nenNMI &  _X029
         # !epHalt & !epRst &  tIpl2
         # !nenIpl & !nenNMI &  tIpl2;
  _X029  = EXP(!epHalt & !epRst);

-- Node name is 'nadvalid' 
-- Equation name is 'nadvalid', location is LC174, type is output.
 nadvalid = LCELL( epAs $  GND);

-- Node name is 'ndatavalid' 
-- Equation name is 'ndatavalid', location is LC128, type is output.
 ndatavalid = LCELL( _EQ049 $  _LC138);
  _EQ049 =  _LC132 & !_LC138 &  _LC186;

-- Node name is 'nDma' 
-- Equation name is 'nDma', location is LC134, type is output.
 nDma    = LCELL( _EQ050 $ !eDisCpu);
  _EQ050 = !eDisCpu &  epfc0 &  epfc1 & !epfc2
         # !eDisCpu & !epfc0 & !epfc1;

-- Node name is 'nemdfcc' 
-- Equation name is 'nemdfcc', location is LC136, type is output.
 nemdfcc = LCELL( _EQ051 $  nemdfc);
  _EQ051 =  epfc0 &  epfc1 & !epfc2 & !nemdfc
         # !epfc0 & !epfc1 & !nemdfc
         #  eDisCpu & !nemdfc;

-- Node name is 'nemsfcc' 
-- Equation name is 'nemsfcc', location is LC137, type is output.
 nemsfcc = LCELL( _EQ052 $  nemsfc);
  _EQ052 =  epfc0 &  epfc1 & !epfc2 & !nemsfc
         # !epfc0 & !epfc1 & !nemsfc
         #  eDisCpu & !nemsfc;

-- Node name is 'nemvalid' 
-- Equation name is 'nemvalid', location is LC184, type is output.
 nemvalid = LCELL( _EQ053 $  _EQ054);
  _EQ053 = !bmsk8 & !eDisCpu &  epOe &  epWeh &  epWel & !nstrobeDly
         #  bmsk8 & !eDisCpu &  epOe &  epWel & !nstrobeDly
         # !eDisCpu &  epfc0 &  epfc1 & !epfc2 & !nstrobeDly
         # !eDisCpu & !epfc0 & !epfc1 & !nstrobeDly;
  _EQ054 =  _X030;
  _X030  = EXP(!eDisCpu & !nstrobeDly);

-- Node name is 'nenepfc' 
-- Equation name is 'nenepfc', location is LC139, type is output.
 nenepfc = LCELL( _EQ055 $ !eDisCpu);
  _EQ055 = !eDisCpu &  epfc0 &  epfc1 & !epfc2
         # !eDisCpu &  nemdfc &  nemsfc
         # !eDisCpu & !epfc0 & !epfc1;

-- Node name is 'nenHiByteO' 
-- Equation name is 'nenHiByteO', location is LC160, type is output.
 nenHiByteO = LCELL( _EQ056 $  VCC);
  _EQ056 = !bmsk8 & !eDisCpu &  epfc1 &  epfc2 & !epOe &  epStop
         # !bmsk8 & !eDisCpu & !epfc0 &  epfc1 & !epOe &  epStop
         # !bmsk8 & !eDisCpu &  epfc0 & !epfc1 & !epOe &  epStop;

-- Node name is 'nenLowByteO' 
-- Equation name is 'nenLowByteO', location is LC152, type is output.
 nenLowByteO = LCELL( _EQ057 $  VCC);
  _EQ057 = !eDisCpu &  epfc1 &  epfc2 & !epOe &  epStop
         # !eDisCpu & !epfc0 &  epfc1 & !epOe &  epStop
         # !eDisCpu &  epfc0 & !epfc1 & !epOe &  epStop;

-- Node name is 'nenpba' 
-- Equation name is 'nenpba', location is LC131, type is output.
 nenpba  = LCELL( isoep $  GND);

-- Node name is 'nenpbd' 
-- Equation name is 'nenpbd', location is LC157, type is output.
 nenpbd  = LCELL( _EQ058 $  VCC);
  _EQ058 =  epfc0 &  epfc1 & !epfc2 & !isoep
         # !epfc0 & !epfc1 & !isoep
         # !epAs & !epStop & !isoep
         #  eDisCpu & !isoep;

-- Node name is 'nentas' 
-- Equation name is 'nentas', location is LC115, type is output.
 nentas  = LCELL( _EQ059 $  GND);
  _EQ059 = !cpenas & !eDisCpu &  epfc1 & !exRdy & !iac & !nmhere &  _X031
         # !cpenas & !eDisCpu &  epfc0 & !epfc1 & !exRdy & !iac & !nmhere
         #  brkAck & !eDisCpu &  epfc0 &  epfc1 &  epfc2
         # !cpenas & !eDisCpu & !emuspace &  epfc1 &  _X031
         # !cpenas & !eDisCpu & !emuspace &  epfc0 & !epfc1;
  _X031  = EXP( epfc0 & !epfc2);

-- Node name is 'nenTcs' 
-- Equation name is 'nenTcs', location is LC113, type is output.
 nenTcs  = LCELL( _EQ060 $ !emuspace);
  _EQ060 = !emuspace &  epfc0 &  epfc1 & !epfc2
         # !emuspace & !epfc0 & !epfc1
         #  eDisCpu & !emuspace;

-- Node name is 'nentdh' 
-- Equation name is 'nentdh', location is LC158, type is output.
 nentdh  = LCELL( _EQ061 $  GND);
  _EQ061 = !bmsk8 & !eDisCpu &  epfc0 & !ninshi &  _X032
         # !bmsk8 & !eDisCpu & !epfc0 &  epfc1 & !ninshi
         # !eDisCpu & !emuspace &  epfc0 &  _X032
         # !eDisCpu & !emuspace & !epfc0 &  epfc1
         # !eDisCpu & !iac & !nmhere;
  _X032  = EXP( epfc1 & !epfc2);

-- Node name is 'nentdl' 
-- Equation name is 'nentdl', location is LC153, type is output.
 nentdl  = LCELL( _EQ062 $ !eDisCpu);
  _EQ062 = !eDisCpu &  emuspace &  ninshi &  ninslow &  _X033
         # !eDisCpu &  epfc0 &  epfc1 & !epfc2 &  _X033
         # !bmsk8 & !eDisCpu &  emuspace &  ninslow &  _X033
         # !eDisCpu & !epfc0 & !epfc1 &  _X033;
  _X033  = EXP(!iac & !nmhere);

-- Node name is 'nentoe' 
-- Equation name is 'nentoe', location is LC121, type is output.
 nentoe  = LCELL( _EQ063 $  GND);
  _EQ063 = !cpends & !eDisCpu &  epfc1 & !exRdy & !iac & !nmhere &  _X031
         # !cpends & !eDisCpu &  epfc0 & !epfc1 & !exRdy & !iac & !nmhere
         #  brkAck & !eDisCpu &  epfc0 &  epfc1 &  epfc2
         # !cpends & !eDisCpu & !emuspace &  epfc1 &  _X031
         # !cpends & !eDisCpu & !emuspace &  epfc0 & !epfc1;
  _X031  = EXP( epfc0 & !epfc2);

-- Node name is 'nentweh' 
-- Equation name is 'nentweh', location is LC120, type is output.
 nentweh = LCELL( _EQ064 $  VCC);
  _EQ064 =  emuspace &  nRdOnly &  _X034 &  _X035
         #  epfc0 &  epfc1 & !epfc2
         #  cpends &  nRdOnly &  _X035
         # !epfc0 & !epfc1
         #  _X036;
  _X034  = EXP(!exRdy & !iac & !nmhere);
  _X035  = EXP( brkAck &  epfc0 &  epfc1);
  _X036  = EXP(!bmsk8 & !eDisCpu);

-- Node name is 'nentwel' 
-- Equation name is 'nentwel', location is LC118, type is output.
 nentwel = LCELL( _EQ065 $  VCC);
  _EQ065 =  emuspace &  nRdOnly &  _X034 &  _X035
         #  epfc0 &  epfc1 & !epfc2
         #  cpends &  nRdOnly &  _X035
         # !epfc0 & !epfc1
         #  eDisCpu;
  _X034  = EXP(!exRdy & !iac & !nmhere);
  _X035  = EXP( brkAck &  epfc0 &  epfc1);

-- Node name is 'nerd' 
-- Equation name is 'nerd', location is LC117, type is output.
 nerd    = LCELL( epOe $  GND);

-- Node name is 'newr' 
-- Equation name is 'newr', location is LC179, type is output.
 newr    = LCELL( _EQ066 $  epWel);
  _EQ066 = !bmsk8 & !epWeh &  epWel;

-- Node name is 'nFHalt' 
-- Equation name is 'nFHalt', location is LC129, type is output.
 nFHalt  = LCELL( _EQ067 $  GND);
  _EQ067 = !cHaltPin &  nFReset;

-- Node name is 'nmemreq' 
-- Equation name is 'nmemreq', location is LC126, type is output.
 nmemreq = LCELL( _EQ068 $  iac);
  _EQ068 = !eDisCpu & !emuspace &  epfc0 & !epfc1 & !iac
         # !eDisCpu & !emuspace & !epfc0 &  epfc1 & !iac
         #  epfc0 &  epfc1 &  epfc2 & !iac;

-- Node name is 'nselepfc' 
-- Equation name is 'nselepfc', location is LC182, type is output.
 nselepfc = LCELL( _EQ069 $  GND);
  _EQ069 = !eDisCpu &  epfc0 &  epfc1 &  epfc2 &  iceBrk;

-- Node name is 'nstrobe' 
-- Equation name is 'nstrobe', location is LC181, type is output.
 nstrobe = LCELL( _EQ070 $  GND);
  _EQ070 = !bmsk8 &  epOe &  epWeh &  epWel
         #  bmsk8 &  epOe &  epWel;

-- Node name is 'nstrobeDly' from file "hd302lc1.tdf" line 145, column 1
-- Equation name is 'nstrobeDly', location is LC156, type is buried.
nstrobeDly = DFFE( _EQ071 $  GND, GLOBAL( iceClk),  VCC,  VCC,  VCC);
  _EQ071 = !bmsk8 &  epOe &  epWeh &  epWel
         #  bmsk8 &  epOe &  epWel;

-- Node name is 'nstsvalid' 
-- Equation name is 'nstsvalid', location is LC123, type is output.
 nstsvalid = LCELL( _EQ072 $  GND);
  _EQ072 =  _LC132 &  _LC186 &  Qual;

-- Node name is 'wct0' from file "hd302lc1.tdf" line 153, column 4
-- Equation name is 'wct0', location is LC175, type is buried.
wct0     = TFFE( VCC, GLOBAL( iceClk), !_EQ073,  VCC,  VCC);
  _EQ073 =  _X037 &  _X038 &  _X039;
  _X037  = EXP(!epOe &  nCsActive_I);
  _X038  = EXP(!bmsk8 & !epWeh &  nCsActive_I);
  _X039  = EXP(!epWel &  nCsActive_I);

-- Node name is 'wct1' from file "hd302lc1.tdf" line 153, column 4
-- Equation name is 'wct1', location is LC176, type is buried.
wct1     = TFFE( wct0, GLOBAL( iceClk), !_EQ074,  VCC,  VCC);
  _EQ074 =  _X037 &  _X038 &  _X039;
  _X037  = EXP(!epOe &  nCsActive_I);
  _X038  = EXP(!bmsk8 & !epWeh &  nCsActive_I);
  _X039  = EXP(!epWel &  nCsActive_I);

-- Node name is 'wct2' from file "hd302lc1.tdf" line 153, column 4
-- Equation name is 'wct2', location is LC163, type is buried.
wct2     = TFFE( _EQ075, GLOBAL( iceClk), !_EQ076,  VCC,  VCC);
  _EQ075 =  wct0 &  wct1;
  _EQ076 =  _X037 &  _X038 &  _X039;
  _X037  = EXP(!epOe &  nCsActive_I);
  _X038  = EXP(!bmsk8 & !epWeh &  nCsActive_I);
  _X039  = EXP(!epWel &  nCsActive_I);

-- Node name is 'wct3' from file "hd302lc1.tdf" line 153, column 4
-- Equation name is 'wct3', location is LC167, type is buried.
wct3     = TFFE( _EQ077, GLOBAL( iceClk), !_EQ078,  VCC,  VCC);
  _EQ077 =  wct0 &  wct1 &  wct2;
  _EQ078 =  _X037 &  _X038 &  _X039;
  _X037  = EXP(!epOe &  nCsActive_I);
  _X038  = EXP(!bmsk8 & !epWeh &  nCsActive_I);
  _X039  = EXP(!epWel &  nCsActive_I);

-- Node name is 'wct4' from file "hd302lc1.tdf" line 153, column 4
-- Equation name is 'wct4', location is LC168, type is buried.
wct4     = TFFE( _EQ079, GLOBAL( iceClk), !_EQ080,  VCC,  VCC);
  _EQ079 =  wct0 &  wct1 &  wct2 &  wct3;
  _EQ080 =  _X037 &  _X038 &  _X039;
  _X037  = EXP(!epOe &  nCsActive_I);
  _X038  = EXP(!bmsk8 & !epWeh &  nCsActive_I);
  _X039  = EXP(!epWel &  nCsActive_I);

-- Node name is '|DVALID:SDvalid|:1' 
-- Equation name is '_LC186', type is buried 
_LC186   = DFFE( _EQ081 $  VCC,  _EQ082,  VCC, !epAs,  VCC);
  _EQ081 = !epDtack &  _LC186;
  _EQ082 = !iceClk &  _X040 &  _X041;
  _X040  = EXP( bmsk8 &  epWel);
  _X041  = EXP( epWeh &  epWel);

-- Node name is '|DVALID:SDvalid|:17' 
-- Equation name is '_LC148', type is buried 
_LC148   = DFFE( GND $  VCC, GLOBAL( iceClk), !epOe,  VCC,  VCC);

-- Node name is '|DVALID:SDvalid|:21' 
-- Equation name is '_LC132', type is buried 
_LC132   = DFFE( _EQ083 $  VCC, GLOBAL(!iceClk),  VCC,  _LC148,  VCC);
  _EQ083 = !epDtack &  _LC132;

-- Node name is '|DVALID:SDvalid|:37' 
-- Equation name is '_LC138', type is buried 
_LC138   = DFFE( _EQ084 $  VCC, GLOBAL( iceClk), !epAs,  VCC,  VCC);
  _EQ084 =  _LC132 &  _LC186;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X013 occurs in LABs --CDE----J--
--    _X014 occurs in LABs --CDE----J--
--    _X026 occurs in LABs ----------KL




Project Information                                    d:\hdlc302\hd302lc1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:02
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:03
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:11


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,035K
