













                         PPR RESULTS FOR DESIGN XLCW
                            From PPR Version 5.2.0

                             1998/06/22 09:15:25
















                                 Xilinx, Inc.
















                  (c) Copyright 1998.  All Rights Reserved.

    PPR RESULTS FOR DESIGN XLCW                                      Page   i

    Table of Contents
    -----------------
    
    List of Warnings .................................................   1
    
    Device Utilization ...............................................   3
    
    Implementation Options ...........................................   4
    
    Xact Performance Summary .........................................   5
    
    Chip Pinout Description ..........................................   7
    
    Routing Summary ..................................................  13
    
    Guided Placement Summary .........................................  18
    
    Guided Routing  Summary ..........................................  19
    
    Unguided Blocks from Input Design ................................  20
    
    Unguided Signals from Input Design ...............................  34
    
    Information in Other Reports .....................................  40
    

    PPR RESULTS FOR DESIGN XLCW                                      Page   1

    List of Warnings
    ----------------

      *** PPR: WARNING 7026: 
            Encountered P2P specification(s) as well as From-To specification(s)
            of a similar kind.  Mixing the two kinds of specifications is not an
            error.  However, use of From-To syntax only gives you better control
            over path specifications.

      *** PPR: WARNING 7013: 
            Specification TS25: P2P EPUDS ED*   60.0 ns;
            does not apply to any paths.

      *** PPR: WARNING 7030: 
            In categories of paths with one or more timing specifications, the
            design has 657 path end-point pairs that are not controlled by any
            timing specification and 412 that are controlled by more than one
            timing specification.  The end-point pairs are listed in file
            xlcw.tsi.  Note that there may be multiple paths between any listed
            pair of end-points.  To limit the number of paths reported in each
            category, set PPR parameter show_tsi_paths = <value>.
            
            

      *** PPR: WARNING 7034: 
            In categories of paths that have NO timing specifications, the
            design has 991 path end-point pairs.  Note that there may be
            multiple paths between any listed pair of end-points.  To limit the
            number of paths reported in each category, set PPR parameter
            show_tsi_paths = <value>.
            

    *** PPR: WARNING 7015: 
          For the specification 'TS11: FROM_TO   35.0 ns;', at least 1 of 16
          path endpoints will apparently not meet the specified delay.  The
          allowable delay for all paths covered by this specification will be
          increased to  51.5 ns.  Although PPR will miss your original
          specification, it is likely to produce a result significantly better
          than the new, relaxed specification.
          
          If some paths in this specification need not run at the speed
          originally specified, you could exclude these from the above
          specification and add a new specification to control these slower
          paths.

    *** PPR: WARNING 7028: 
          The design has flip-flops with asynchronous set/reset controls (PRE/SD
          or CLR/RD pins).  When PPR analyzes design timing, it does not trace
          paths through the asynchronous set/reset input and on through the Q
          output.
          
          If you want PPR to control the delay on paths through asynchronous
          set/reset pins, you must split the delay requirement into two
          segments: one ending at the set/reset input, and the other beginning
          at the flip-flop output.
          If you want PPR not to analyze paths that lead to asynchronous
          set/reset pins, attach an IGNORE specification to the pin(s) or
          signal(s).
          
          By default, XDelay reports all paths through asynchronous set/reset
          pins. To prevent XDelay from showing these paths, use FlagBlk
          CLB_Disable_SR_Q on the appropriate flip-flops.

    *** PPR: WARNING 7029: 
          The design has RAM elements.  When PPR analyzes design timing, it does

    PPR RESULTS FOR DESIGN XLCW                                      Page   2

          not trace paths through the data or write-enable inputs and on through
          the RAM output.  Such paths are normally of interest only when the RAM
          is being read during a write operation.
          
          If you want PPR to control the delay on paths through the D or WE
          inputs, you must split the delay requirement into two segments: one
          ending at the RAM input pin, and the other beginning at the RAM
          output.
          
          By default, XDelay does not report paths through D or WE pins either.
          To allow XDelay to show these paths, use FlagBlk CLB_Enable_WE and/or
          FlagBlk CLB_Enable_DIN on the appropriate RAMs.

    *** PPR: WARNING 10604: 
          A .LCA file already exists.  The old .LCA file will be saved as
          'xlcw.lcb'.

    PPR RESULTS FOR DESIGN XLCW                                      Page   3

    Device Utilization
    ------------------
    
    Partitioned Design Utilization Using Part 4005PQ160-5
    
    -----------------------------------------------------------------
                                     No. Used   Max Available   %Used
    -----------------------------------------------------------------
    
      Occupied CLBs                       188         196          95%
      Bonded I/O Pins                     99          112          88%
      F and G Function Generators (*)     242         392          61%
      H  Function Generators              63          196          32%
      CLB Flip Flops                      85          392          21%
      IOB Input Flip Flops                10          112          8%
      IOB Output Flip Flops               0           112          0%
      3-State Buffers                     121         448          27%
      3-State Half Longlines              32          56           57%
      Edge Decode Inputs                  44          168          26%
      Edge Decode Half Longlines          16          32           50%
      
      (*) If RAM/ROM elements are present in the design, this count
      includes the function generators used for them. A 16x1 memory uses 1
      function generator; a 32x1 uses two.
      
      ----------------------------------------------------------------
      
      
    CPU Times
    
      CPU time taken for Partition:   0 hrs  0 mins  8 secs
      CPU time taken for Placement:   0 hrs  6 mins 33 secs
      
      

    PPR RESULTS FOR DESIGN XLCW                                      Page   4

    Implementation Options
    ----------------------
    
    
    PPR Parameters
    
      Design               = xlcw.xtf
      Logfile              = ppr.log
      Outfile              = <design name>
      Estimate             = FALSE
      
      
    Additional Specified or Non-Default Parameters
    
      placer_effort        = 5
      guide                = g.lca
      parttype             = 4005PQ160-5
      seed                 = 898506112
      
      

    PPR RESULTS FOR DESIGN XLCW                                      Page   5

    Xact Performance Summary
    ------------------------
    
    Parttype Used      : 4005PQ160
    
    Speed Grade        : -5
    
    
                        End-
       Limit  Actual  Points
       (ns)   * (ns)  Missed   Specification
      ------  ------  -------  -------------
      <auto>    69.2    0/30   <default> pad to pad
        70.0    62.3    0/16   TS22=pad to pad:
        55.0    47.8    0/16   TS23=pad to pad:
        45.0    31.2    0/16   TS24=pad to pad:
        60.0    (x)     0/0    TS25=pad to pad:
        30.0    21.3    0/1    TS02=FROM:FLOP:TO:ICEBRK
        45.0    39.7    0/416  TS10=FROM:EP:TO:MEM
    *   35.0    37.4    4/16   TS11=FROM:MEM:TO:ED
        70.0    54.5    0/2    TS20=FROM:EAES:TO:INSERT
        60.0    33.1    0/1    TS21=FROM:EAES:TO:QUAL
        70.0    47.2    0/29   TS12=FROM:EAES:TO:FFS
      <auto>    56.8    0/149  DEFAULT_FROM_FFS_TO_FFS=FROM:ffs:TO:ffs
    
    (*) Note: the actual path delays computed by PPR indicate that 1 of 9
    timing specifications you provided was not met.  To confirm this
    result, please use the -FailedSpec and/or -TSMaxpaths options of the
    Xdelay-TimeSpec command, accessible through the XDE or XDelay program.
    
    
    Note: The design contains flip-flops clocked by opposite edges of the
    same signal.  Default specs generated automatically by PPR will not
    properly control paths between opposite-edge flip-flops.  The delays
    on such paths will be properly controlled ONLY if: (1) the flip-flops
    are grouped by clock edge using RISING and FALLING TIMEGRP statements,
    and these subgroups are used in TIMESPEC statements with the
    appropriate High and Low clock times; or (2) a C2S-style TIMESPEC
    statement with the appropriate High clock time is attached to the
    clock signal.
    
    Note: The design contains more than one clock signal (NCPWR, CLRBRKF,
    CPIOPORT/OUTPUT/CNFEND, NEMVALID, ICECLK, LOGIC/EMS7, LOGIC/EMS8,
    XSSI, XPAD/XINPAD/CPINPAD/CPCLK). Default specs generated
    automatically by PPR will not control each clock at its own best
    possible frequency; clocks which could run faster may be controlled at
    a slower frequency. If you have specified no TIMESPEC requirements (or
    only a generic `FROM:FFS:TO:FFS' requirement), the design performance
    may not have been optimized by PPR. For best results, supply
    individual TIMESPECs for the flip-flops on each clock signal that you
    care about.
    
    (x) These specifications did not apply to any paths in the design.
    
        *** PPR: WARNING 7028:
    The design has flip-flops with asynchronous set/reset controls (PRE/SD
    or CLR/RD pins).  When PPR analyzes design timing, it does not trace
    paths through the asynchronous set/reset input and on through the Q
    output.
    

    PPR RESULTS FOR DESIGN XLCW                                      Page   6

    If you want PPR to control the delay on paths through asynchronous
    set/reset pins, you must split the delay requirement into two
    segments: one ending at the set/reset input, and the other beginning
    at the flip-flop output. If you want PPR not to analyze paths that
    lead to asynchronous set/reset pins, attach an IGNORE specification to
    the pin(s) or signal(s).
    
    By default, XDelay reports all paths through asynchronous set/reset
    pins. To prevent XDelay from showing these paths, use FlagBlk
    CLB_Disable_SR_Q on the appropriate flip-flops.
    
        *** PPR: WARNING 7029:
    The design has RAM elements.  When PPR analyzes design timing, it does
    not trace paths through the data or write-enable inputs and on through
    the RAM output.  Such paths are normally of interest only when the RAM
    is being read during a write operation.
    
    If you want PPR to control the delay on paths through the D or WE
    inputs, you must split the delay requirement into two segments: one
    ending at the RAM input pin, and the other beginning at the RAM
    output.
    
    By default, XDelay does not report paths through D or WE pins either.
    To allow XDelay to show these paths, use FlagBlk CLB_Enable_WE and/or
    FlagBlk CLB_Enable_DIN on the appropriate RAMs.
    

    PPR RESULTS FOR DESIGN XLCW                                      Page   7

    Chip Pinout Description
    -----------------------
    
    This chapter describes where your design's pins were placed in terms
    of the package pins. Generally there are four sections for this
    chapter. The first section is a list showing signal name and the
    package pin location, sorted by the signal name. The second section is
    a list showing the package pin names and signal names sorted by the
    package pin names. Next section appears only if your design uses
    special pads. This will a table showing the special pad names and the
    signal names, sorted by special pad name. The last section is a series
    of CST file statements, which if copied into a text file, can be used
    as constraints for a  subsequent ppr run for locking IOs at their
    current locations.
    
    Sorted by Signal Names:
    
    Pin Name              Package Pin Location
    --------              --------------------
    BMSK8                : P52
    BRKACK               : P24
    CPAD0                : P117
    CPAD1                : P113
    CPAD2                : P106
    CPAD3                : P102
    CPAD4                : P98
    CPAD5                : P94
    CPAD6                : P87
    CPAD7                : P83
    CPALE                : P124
    CPCLK                : P84
    DISNRDYF             : P92
    EA0                  : P158
    EA1                  : P157
    EA2                  : P156
    EA3                  : P155
    EA4                  : P154
    EA5                  : P150
    EA6                  : P149
    EA7                  : P148
    EA8                  : P147
    EA9                  : P146
    EA10                 : P145
    EA11                 : P144
    EA12                 : P143
    EA13                 : P140
    EA14                 : P139
    EA15                 : P138
    EA16                 : P137
    EA17                 : P135
    EA18                 : P134
    EA19                 : P133
    EA20                 : P57
    EA21                 : P58
    EA22                 : P62
    EA23                 : P63
    EA24                 : P64
    EA25                 : P65
    EA26                 : P66
    EA27                 : P67

    PPR RESULTS FOR DESIGN XLCW                                      Page   8

    Pin Name              Package Pin Location (continued)
    --------              --------------------
    EA28                 : P68
    EA29                 : P69
    EA30                 : P73
    EA31                 : P74
    ED0                  : P3
    ED1                  : P4
    ED2                  : P6
    ED3                  : P7
    ED4                  : P12
    ED5                  : P13
    ED6                  : P15
    ED7                  : P16
    ED8                  : P22
    ED9                  : P23
    ED10                 : P25
    ED11                 : P26
    ED12                 : P28
    ED13                 : P32
    ED14                 : P34
    ED15                 : P35
    EMON                 : P115
    EMUSPACE             : P109
    EPLDS                : P18
    EPSTOP               : P27
    EPUDS                : P21
    ES0                  : P45
    ES1                  : P46
    ES2                  : P47
    ES4                  : P53
    ES5                  : P54
    ES6                  : P55
    ES7                  : P56
    FLAGNOTRDY           : P107
    GOEP                 : P97
    HLDC                 : P75
    ICEBRK               : P125
    ICECLK               : P37
    ICERDY               : P77
    NADVALID             : P159
    NCODCOVGE            : P88
    NCPRD                : P116
    NEMFC0               : P86
    NEMFC1               : P85
    NEMVALID             : P78
    NENNMI               : P108
    NEPRUN               : P44
    NINSHI               : P11
    NINSLOW              : P5
    NMCS2H0              : P95
    NMCS2H1              : P127
    NRBWBRK              : P128
    NSTROBE              : P43
    NTRIGBRK             : P126
    NVIOLBRK             : P132
    NWR                  : P123
    QUAL                 : P99
    SSO                  : P17
    XSSI                 : P14

    PPR RESULTS FOR DESIGN XLCW                                      Page   9

    Pin Name              Package Pin Location (continued)
    --------              --------------------
    
    Sorted by Package Pin Locations:
    
    Package Pin Location   Pin Name
    --------------------   --------
    P3                   : ED0
    P4                   : ED1
    P5                   : NINSLOW
    P6                   : ED2
    P7                   : ED3
    P11                  : NINSHI
    P12                  : ED4
    P13                  : ED5
    P14                  : XSSI
    P15                  : ED6
    P16                  : ED7
    P17                  : SSO
    P18                  : EPLDS
    P21                  : EPUDS
    P22                  : ED8
    P23                  : ED9
    P24                  : BRKACK
    P25                  : ED10
    P26                  : ED11
    P27                  : EPSTOP
    P28                  : ED12
    P32                  : ED13
    P34                  : ED14
    P35                  : ED15
    P37                  : ICECLK
    P43                  : NSTROBE
    P44                  : NEPRUN
    P45                  : ES0
    P46                  : ES1
    P47                  : ES2
    P52                  : BMSK8
    P53                  : ES4
    P54                  : ES5
    P55                  : ES6
    P56                  : ES7
    P57                  : EA20
    P58                  : EA21
    P62                  : EA22
    P63                  : EA23
    P64                  : EA24
    P65                  : EA25
    P66                  : EA26
    P67                  : EA27
    P68                  : EA28
    P69                  : EA29
    P73                  : EA30
    P74                  : EA31
    P75                  : HLDC
    P77                  : ICERDY
    P78                  : NEMVALID
    P83                  : CPAD7
    P84                  : CPCLK
    P85                  : NEMFC1

    PPR RESULTS FOR DESIGN XLCW                                      Page  10

    Package Pin Location   Pin Name (continued)
    --------------------   --------
    P86                  : NEMFC0
    P87                  : CPAD6
    P88                  : NCODCOVGE
    P92                  : DISNRDYF
    P94                  : CPAD5
    P95                  : NMCS2H0
    P97                  : GOEP
    P98                  : CPAD4
    P99                  : QUAL
    P102                 : CPAD3
    P106                 : CPAD2
    P107                 : FLAGNOTRDY
    P108                 : NENNMI
    P109                 : EMUSPACE
    P113                 : CPAD1
    P115                 : EMON
    P116                 : NCPRD
    P117                 : CPAD0
    P123                 : NWR
    P124                 : CPALE
    P125                 : ICEBRK
    P126                 : NTRIGBRK
    P127                 : NMCS2H1
    P128                 : NRBWBRK
    P132                 : NVIOLBRK
    P133                 : EA19
    P134                 : EA18
    P135                 : EA17
    P137                 : EA16
    P138                 : EA15
    P139                 : EA14
    P140                 : EA13
    P143                 : EA12
    P144                 : EA11
    P145                 : EA10
    P146                 : EA9
    P147                 : EA8
    P148                 : EA7
    P149                 : EA6
    P150                 : EA5
    P154                 : EA4
    P155                 : EA3
    P156                 : EA2
    P157                 : EA1
    P158                 : EA0
    P159                 : NADVALID
    
    CST File Format (location constraints file):
    
    
    place instance XPAD/XINPAD/EAESPAD/PES3_pad : P52 ;
    place instance XPAD/XOUTPAD/$U44_O2_pad : P24 ;
    place instance XPAD/XBPAD/CDBUS/CPAD0_pad : P117 ;
    place instance XPAD/XBPAD/CDBUS/CPAD1_pad : P113 ;
    place instance XPAD/XBPAD/CDBUS/CPAD2_pad : P106 ;
    place instance XPAD/XBPAD/CDBUS/CPAD3_pad : P102 ;
    place instance XPAD/XBPAD/CDBUS/CPAD4_pad : P98 ;
    place instance XPAD/XBPAD/CDBUS/CPAD5_pad : P94 ;

    PPR RESULTS FOR DESIGN XLCW                                      Page  11

     (continued)
    
    place instance XPAD/XBPAD/CDBUS/CPAD6_pad : P87 ;
    place instance XPAD/XBPAD/CDBUS/CPAD7_pad : P83 ;
    place instance XPAD/XINPAD/CPINPAD/$U90_IPAD_pad : P124 ;
    place instance XPAD/XINPAD/CPINPAD/$U88_IPAD_pad : P84 ;
    place instance XPAD/XOUTPAD/$U522_O_pad : P92 ;
    place instance XPAD/XINPAD/EAESPAD/PEA0_pad : P158 ;
    place instance XPAD/XINPAD/EAESPAD/PEA1_pad : P157 ;
    place instance XPAD/XINPAD/EAESPAD/PEA2_pad : P156 ;
    place instance XPAD/XINPAD/EAESPAD/PEA3_pad : P155 ;
    place instance XPAD/XINPAD/EAESPAD/PEA4_pad : P154 ;
    place instance XPAD/XINPAD/EAESPAD/PEA5_pad : P150 ;
    place instance XPAD/XINPAD/EAESPAD/PEA6_pad : P149 ;
    place instance XPAD/XINPAD/EAESPAD/PEA7_pad : P148 ;
    place instance XPAD/XINPAD/EAESPAD/PEA8_pad : P147 ;
    place instance XPAD/XINPAD/EAESPAD/PEA9_pad : P146 ;
    place instance XPAD/XINPAD/EAESPAD/PEA10_pad : P145 ;
    place instance XPAD/XINPAD/EAESPAD/PEA11_pad : P144 ;
    place instance XPAD/XINPAD/EAESPAD/PEA12_pad : P143 ;
    place instance XPAD/XINPAD/EAESPAD/PEA13_pad : P140 ;
    place instance XPAD/XINPAD/EAESPAD/PEA14_pad : P139 ;
    place instance XPAD/XINPAD/EAESPAD/PEA15_pad : P138 ;
    place instance XPAD/XINPAD/EAESPAD/PEA16_pad : P137 ;
    place instance XPAD/XINPAD/EAESPAD/PEA17_pad : P135 ;
    place instance XPAD/XINPAD/EAESPAD/PEA18_pad : P134 ;
    place instance XPAD/XINPAD/EAESPAD/PEA19_pad : P133 ;
    place instance XPAD/XINPAD/EAESPAD/PEA20_pad : P57 ;
    place instance XPAD/XINPAD/EAESPAD/PEA21_pad : P58 ;
    place instance XPAD/XINPAD/EAESPAD/PEA22_pad : P62 ;
    place instance XPAD/XINPAD/EAESPAD/PEA23_pad : P63 ;
    place instance XPAD/XINPAD/EAESPAD/PEA24_pad : P64 ;
    place instance XPAD/XINPAD/EAESPAD/PEA25_pad : P65 ;
    place instance XPAD/XINPAD/EAESPAD/PEA26_pad : P66 ;
    place instance XPAD/XINPAD/EAESPAD/PEA27_pad : P67 ;
    place instance XPAD/XINPAD/EAESPAD/PEA28_pad : P68 ;
    place instance XPAD/XINPAD/EAESPAD/PEA29_pad : P69 ;
    place instance XPAD/XINPAD/EAESPAD/PEA30_pad : P73 ;
    place instance XPAD/XINPAD/EAESPAD/PEA31_pad : P74 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O0_pad : P3 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O1_pad : P4 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O2_pad : P6 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O3_pad : P7 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O4_pad : P12 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O5_pad : P13 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O6_pad : P15 ;
    place instance XPAD/XBPAD/EDBUS/$U1_O7_pad : P16 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O0_pad : P22 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O1_pad : P23 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O2_pad : P25 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O3_pad : P26 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O4_pad : P28 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O5_pad : P32 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O6_pad : P34 ;
    place instance XPAD/XBPAD/EDBUS/$U3_O7_pad : P35 ;
    place instance XPAD/XOUTPAD/$U40_O2_pad : P115 ;
    place instance XPAD/XOUTPAD/$U40_O3_pad : P109 ;
    place instance XPAD/XINPAD/EAESPAD/$U135_IPAD_pad : P18 ;
    place instance XPAD/XOUTPAD/$U40_O5_pad : P27 ;
    place instance XPAD/XINPAD/EAESPAD/$U136_IPAD_pad : P21 ;

    PPR RESULTS FOR DESIGN XLCW                                      Page  12

     (continued)
    
    place instance XPAD/XINPAD/EAESPAD/PES0_pad : P45 ;
    place instance XPAD/XINPAD/EAESPAD/PES1_pad : P46 ;
    place instance XPAD/XINPAD/EAESPAD/PES2_pad : P47 ;
    place instance XPAD/XINPAD/EAESPAD/PES4_pad : P53 ;
    place instance XPAD/XINPAD/EAESPAD/PES5_pad : P54 ;
    place instance XPAD/XINPAD/EAESPAD/PES6_pad : P55 ;
    place instance XPAD/XINPAD/EAESPAD/PES7_pad : P56 ;
    place instance XPAD/XINPAD/EAESPAD/$U138_IPAD_pad : P107 ;
    place instance XPAD/XOUTPAD/$U523_O_pad : P97 ;
    place instance XPAD/XINPAD/CPINPAD/$U89_IPAD_pad : P75 ;
    place instance XPAD/XOUTPAD/$U40_O0_pad : P125 ;
    place instance XPAD/XINPAD/$U77_IPAD_pad : P37 ;
    place instance XPAD/XOUTPAD/$U40_O6_pad : P77 ;
    place instance XPAD/XINPAD/$U78_IPAD_pad : P159 ;
    place instance XPAD/XOUTPAD/$U43_O2_pad : P88 ;
    place instance XPAD/XINPAD/CPINPAD/$U86_IPAD_pad : P116 ;
    place instance XPAD/XOUTPAD/$U44_O0_pad : P86 ;
    place instance XPAD/XOUTPAD/$U44_O1_pad : P85 ;
    place instance XPAD/XINPAD/$U76_IPAD_pad : P78 ;
    place instance XPAD/XOUTPAD/$U40_O1_pad : P108 ;
    place instance XPAD/XOUTPAD/$U43_O3_pad : P44 ;
    place instance XPAD/XOUTPAD/$U43_O1_pad : P11 ;
    place instance XPAD/XOUTPAD/$U43_O0_pad : P5 ;
    place instance XPAD/XINPAD/CPINPAD/$U84_IPAD_pad : P95 ;
    place instance XPAD/XINPAD/CPINPAD/$U85_IPAD_pad : P127 ;
    place instance XPAD/XINPAD/$U72_IPAD_pad : P128 ;
    place instance XPAD/XINPAD/$U75_IPAD_pad : P43 ;
    place instance XPAD/XINPAD/$U71_IPAD_pad : P126 ;
    place instance XPAD/XINPAD/$U73_IPAD_pad : P132 ;
    place instance XPAD/XINPAD/CPINPAD/$U87_IPAD_pad : P123 ;
    place instance XPAD/XOUTPAD/$U45_O_pad : P99 ;
    place instance XPAD/XOUTPAD/$U40_O4_pad : P17 ;
    place instance XPAD/XINPAD/$U74_IPAD_pad : P14 ;

    PPR RESULTS FOR DESIGN XLCW                                      Page  13

    Routing Summary
    ---------------
    
    Number of unrouted connections :  0
    
    CPU time taken for Routing     :  0 hrs  5 mins 52 secs
    
    
    Split Nets:
    
    The list below identifies those signals which were routed through CLBs
    or other blocks. In XDE and XDelay reports, these signals will have
    two or more segments. An underscore (_) and a number will be added to
    the end of the original signal name to identify the different
    segments. To analyze all segments of a signal in XDelay or QueryNet
    reports, append the original name with "_*" when prompted for a signal
    name.
    
    PPR may route signals through CLBs or other blocks in any of the
    following situations:
    
    * The delay on a signal might be reduced by routing it through a CLB,
    given the extra flexibility in routing resources and the reduced
    capacitive loading on the signal. PPR takes this into consideration.
    
    * The delay on a signal might be reduced by sourcing it from two block
    outputs instead of one, which is possible in some block
    configurations. PPR will do this where possible.
    
    * A signal on a global buffer may not be able to connect directly to a
    load pin, given the placement of that load pin and the other global
    resources which are used. PPR will pass the signal through another CLB
    and route the load pin using general-purpose interconnect.
    
    * In an XC4000 design, A BUFGP can be sourced only from an IOB. If the
    design indicates that a BUFGP is driven from an internal source, PPR
    will route the signal through the output path of the IOB in order to
    access the BUFGP input.
    
    Segments   Original Signal Name
    --------   -------------------------------------------------------
    
      2           CDO6
    
      3           EPSTOP
    
      2           CDO2
    
      2           CDO1
    
      2           FLAGNOTRDY
    
      2           NSTROBE
    
      4           NDMA
    
      2           emon
    
      3           CPIOPORT/PORT0
    

    PPR RESULTS FOR DESIGN XLCW                                      Page  14

     (continued)
    Split Nets:
    
      3           NCPRD
    
      3           CPIOPORT/PORT1
    
      5           CPIOPORT/PORT2
    
      2           NCPWR
    
      4           CDI1
    
      3           CDI3
    
      2           ENQUAL
    
      3           CDI4
    
      2           CDI6
    
      3           RELOC
    
      4           CDI7
    
      3           ENSWBP
    
      2           ENSSI
    
      3           SEMS5
    
      2           SJS0
    
      2           SJS3
    
      3           ENALINE
    
      2           NCNFOK
    
      4           CA0
    
      2           EDO7
    
      2           EDO5
    
      2           EDO4
    
      2           LOGIC/ALINE/$U324_O
    
      2           NINSHI
    
      2           EDO8
    
      9           LOGIC/EMS5
    
      2           LOGIC/CANRAM/RA1
    
      5           NMCS2H0
    
      2           EA1

    PPR RESULTS FOR DESIGN XLCW                                      Page  15

     (continued)
    Split Nets:
    
    
      3           EA2
    
      2           LOGIC/CANRAM/RA3
    
      3           EA3
    
      2           EA4
    
      2           LOGIC/CANRAM/RA5
    
      2           EA5
    
      2           CA7
    
      5           CA6
    
      3           EA6
    
      5           EA7
    
      2           LOGIC/CANRAM/CANCNT/$U395_O
    
      3           LOGIC/CANRAM/HCANWR0
    
      2           LOGIC/CANRAM/LCANWR1
    
      2           LOGIC/CANRAM/NLCPCRD0
    
      2           LOGIC/CANRAM/NHCPCRD1
    
      2           emuspace
    
      2           LOGIC/RDI0
    
      2           LOGIC/RDI1
    
      2           LOGIC/RDI2
    
      2           LOGIC/RDI3
    
      2           LOGIC/RDI4
    
      2           LOGIC/RDI6
    
      3           LOGIC/RDI8
    
      3           LOGIC/RDI10
    
      2           LOGIC/RDI11
    
      2           LOGIC/RDI12
    
      2           LOGIC/RDI13
    
      3           LOGIC/RDI15
    

    PPR RESULTS FOR DESIGN XLCW                                      Page  16

     (continued)
    Split Nets:
    
      2           LOGIC/CANRAM/LRDO7
    
      2           EDO2
    
      2           LOGIC/CANRAM/LRDO1
    
      2           EDO0
    
      2           LOGIC/CANRAM/HRDO5
    
      2           LOGIC/CANRAM/LRDO15
    
      2           EDO14
    
      2           LOGIC/CANRAM/LRDO14
    
      2           LOGIC/CANRAM/LRDO11
    
      2           LOGIC/CANRAM/LRDO10
    
      2           LOGIC/CANRAM/HRDO14
    
      2           LOGIC/CANRAM/HRDO13
    
      2           LOGIC/CANRAM/HRDO12
    
      2           LOGIC/CANRAM/HRDO11
    
      2           LOGIC/CANRAM/HRDO10
    
      2           EPFC0
    
      2           EPFC1
    
      2           EPFC2
    
      4           XPAD/EPOE
    
      2           EA9
    
      2           LOGIC/EDGE/EXBP2T
    
      3           NINSLOW
    
      2           LOGIC/EDGE/$U609_Q
    
      2           LOGIC/WRITE
    
      2           BRKACK
    
      3           LOGIC/EMSTATE/EMS2
    
      3           LOGIC/EMS7
    
      3           LOGIC/TRAMEN
    
      4           LOGIC/EMS8

    PPR RESULTS FOR DESIGN XLCW                                      Page  17

     (continued)
    Split Nets:
    
    
      2           LOGIC/EMS3
    
      2           LOGIC/EMS4
    
      2           NRBWBRK
    
      2           LOGIC/EMSTATE/ICEBRK/$U466_Q
    
      3           XSSI
    
      2           LOGIC/GOEP/$U171_Q
    
      2           LOGIC/SPOON/SPADD/TCA0
    
      2           LOGIC/SPOON/SPADD/TCA2
    
      2           LOGIC/SPOON/SPA3
    
      2           LOGIC/SPOON/SPA2
    
      2           LOGIC/SPOON/SPDO7
    
      2           LOGIC/SPOON/SPDO6
    
      2           LOGIC/SPOON/SPDO4
    
      2           LOGIC/SPOON/SPDO9
    
      2           LOGIC/SPOON/SPWRITE/$U230_O
    
      2           LOGIC/SPOON/SPWRITE0
    
      2           NUDS

    PPR RESULTS FOR DESIGN XLCW                                      Page  18

    Guided Placement Summary
    ------------------------
    
    
    The following table summarizes the guided placement process. For each
    type of LCA block, this table shows (1) how many blocks of that type
    exist in the input design file; (2) how many of these blocks were
    matched to blocks in the guide file; and (3) how many of the matched
    blocks were used to guide the placement of the input design.
    
    A matched block will not be used to guide placement if any one of the
    following is true:
    * The guide_blks option is set to ROUTED_ONLY and the matched block
    does not have any routing connected to it in the guide LCA file.
    * The matched block is placed elsewhere by a constraint in the input
    design or the CST file.
    * A different block is placed in the matched block's guide location by
    a constraint in the input design or the CST file.
    * The matched block is part of an RLOC set and other blocks in that
    set were not matched. A partially-matched RLOC set will be guided only
    if there is space available for the unmatched blocks AND if the
    structure of the RLOC set can be respected.
    * A pin on a matched block does not have any routing connected to it
    in the guide LCA file, so the pin was swapped with another pin on that
    CLB to improve the routing of the associated signal(s). For example,
    the X and Y flip-flops may be swapped if their output pins are not
    routed.
    
    
    Block Type             In Design   Matched in Guide   Placement Guided
    ----------------       ---------   ----------------   ---------------
    CLB flip-flop              85              0                  0
    CLB function generator    305              0                  0
    CLB carry logic             0              0                  0
    Edge decoder input         44             44                 44
    3-state buffer            121              0                  0
    I/O pad                    99             57                 57
    
    If there are blocks in the input design which could not be matched in
    the guide file they will be listed in the "Unguided Blocks" chapter
    below.
    
    

    PPR RESULTS FOR DESIGN XLCW                                      Page  19

    Guided Routing  Summary
    ------------------------
    
    
    The following signal counts represent only signals outside of CLBs and
    IOBs.
    
    367 signals in input design file were matched in guide file
    ----------------------------------------------------------
    26 signals routed using all routing information from guide file
    14 signals routed using some routing information from guide file (*)
    327 signals routed using no routing information from guide file (*)
    
    4 signals in input design were not found in guide file
    
    (*) These signals are listed in the "Unguided Signals" chapter below
    

    PPR RESULTS FOR DESIGN XLCW                                      Page  20

    Unguided Blocks from Input Design
    ---------------------------------
    
    
    The following lists show which blocks in the input design were not
    matched to blocks in the guide file and therefore were NOT guided
    during the placement process.
    
    CLB flip flops driving following Q output signals:
    -----------------------------------------------------------
    INSTEP
    CLRBRKF
    CLRRUNF
    FORCERDY
    ENQUAL
    FORCEBRK
    RELOC
    ENSWBP
    DISINT
    ENSSI
    ESCSSI
    ENSSO
    ENBP1
    ENBP2
    SEMS0
    SEMS5
    SJS0
    SJS3
    ENALINE
    FLINE
    CPIOPORT/OUTPUT/CNFEND
    CPIOPORT/BUSCTEST
    NCNFOK
    CPIOPORT/BUSCYCOK
    EXBP2F
    EXBP1F
    LOGIC/EDGE/$U603_Q
    LOGIC/EDGE/$U604_Q
    LOGIC/EDGE/$U607_Q
    LOGIC/EDGE/$U609_Q
    LOGIC/EMSTATE/CANEND/CANES0
    LOGIC/EMSTATE/CANEND/CANES1
    emon
    BRKACK
    LOGIC/EMSTATE/EMON/$U512_Q
    LOGIC/TRAMEN
    LOGIC/EMSTATE/EMS0
    LOGIC/EMSTATE/EMSI/EMS1
    LOGIC/EMSTATE/EMS2
    LOGIC/EMS3
    LOGIC/EMS4
    LOGIC/EMS5
    LOGIC/EMS6
    LOGIC/EMS7
    LOGIC/EMS8
    LOGIC/EMSTATE/EMUSPACE/DEXT0
    LOGIC/EMSTATE/EMUSPACE/DEXT1
    LOGIC/EMSTATE/EMUSPACE/DEXT2
    LOGIC/EMSTATE/EMUSPACE/SEXT0
    LOGIC/EMSTATE/EMUSPACE/SEXT1

    PPR RESULTS FOR DESIGN XLCW                                      Page  21

    LOGIC/EMSTATE/EMUSPACE/SEXT2
    LOGIC/EN28RCOM
    LOGIC/EMSTATE/EN28R/EXS0
    LOGIC/EMSTATE/EN28R/EXS1
    LOGIC/EMSTATE/EN28R/EXS2
    LOGIC/FORCE2AR
    EXBPF
    LOGIC/EMSTATE/EN28R/EXS3
    LOGIC/EMSTATE/EN28R/EXS5
    LOGIC/EMSTATE/ICEBRK/$U448_Q
    LOGIC/EMSTATE/ICEBRK/$U449_Q
    LOGIC/EMSTATE/ICEBRK/$U451_Q
    TRBRKF
    LOGIC/EMSTATE/ICEBRK/$U456_Q
    LOGIC/EMSTATE/ICEBRK/$U462_Q
    LOGIC/EMSTATE/ICEBRK/$U465_Q
    LOGIC/EMSTATE/ICEBRK/$U466_Q
    LOGIC/EMSTATE/ICEBRK/INSTEPBRK
    LOGIC/GOEP/$U164_Q
    LOGIC/SSI
    LOGIC/GOEP/$U168_Q
    LOGIC/GOEP/$U171_Q
    RUNUSER
    LOGIC/JMPHERE/JS0
    LOGIC/JMPHERE/JS1
    LOGIC/JMPHERE/JS2
    LOGIC/JMPHERE/JS3
    RUNCAN
    LOGIC/WRITE
    LOGIC/READ
    LOGIC/SPOON/SPADD/TCA0
    LOGIC/SPOON/SPADD/TCA1
    LOGIC/SPOON/SPADD/TCA2
    LOGIC/SPOON/SPWRITE/$U238_Q
    LOGIC/SPOON/SPWRITE/$U239_Q
    
    CLB function generators driving following output signals:
    ------------------------------------------------------------
    LOGIC/EMSTATE/EN28R/EXS4/EXSD4
    NINSLOW
    LOGIC/NHBUSMAT
    LOGIC/CANRAM/NHEPCRD
    LOGIC/CANRAM/CANCNT/NEPCRD1
    LOGIC/CANRAM/NLEPCRD
    LOGIC/CANRAM/CANCNT/NEPCRD0
    NCPWR
    $FGDECOMP0671_XPAD/XBPAD/EDBUS/NEDHI
    XPAD/XBPAD/EDBUS/NEDHI
    $FGDECOMP0672_XPAD/XBPAD/EDBUS/NEDLOW
    XPAD/XBPAD/EDBUS/NEDLOW
    XPAD/XBPAD/CDBUS/NENCDB
    LOGIC/SPOON/SPWRITE/EPCWRQ
    LOGIC/NXEWR1
    LOGIC/NXEWR0
    $FGDECOMP0673_LOGIC/SPOON/SPWRITE/$U234_O
    LOGIC/SPOON/SPWRITE/$U234_O
    LOGIC/SPOON/SPWRITE/$U237_O
    LOGIC/SPOON/SPWRITE/$U235_O
    LOGIC/SPOON/SPWRITE1
    $FGDECOMP0674_LOGIC/SPOON/SPWRITE/$U230_O

    PPR RESULTS FOR DESIGN XLCW                                      Page  22

    LOGIC/SPOON/SPWRITE/$U230_O
    LOGIC/SPOON/SPWRITE/$U233_O
    LOGIC/SPOON/SPWRITE/$U231_O
    LOGIC/SPOON/SPWRITE0
    $FGDECOMP0675_LOGIC/SPOON/SPDBUF/$U250_O
    LOGIC/SPOON/SPDBUF/$U250_O
    $FGDECOMP0676_LOGIC/SPOON/SPDBUF/$U249_O
    LOGIC/SPOON/SPDBUF/$U249_O
    $FGDECOMP0677_LOGIC/SPOON/SPDBUF/$U248_O
    LOGIC/SPOON/SPDBUF/$U248_O
    LOGIC/SPOON/SPADD/$U216_O
    LOGIC/SPOON/SPADD/U220/$U3_O
    LOGIC/SPOON/SPA1
    LOGIC/SPOON/SPADD/$U215_O
    LOGIC/SPOON/SPADD/U219/$U3_O
    LOGIC/SPOON/SPA2
    LOGIC/SPOON/SPADD/U218/$U3_O
    LOGIC/SPOON/SPADD/U218/$U2_O
    LOGIC/SPOON/SPA3
    LOGIC/SPOON/SPA4
    LOGIC/SPOON/SPADD/$U213_O
    LOGIC/SPOON/SPADD/CNT8RD/$U228_O
    LOGIC/SPOON/SPADD/CNT8RD/$U227_O
    LOGIC/SPOON/SPADD/CNT8RD/$U226_O
    LOGIC/SPACE/$U576_O
    LOGIC/FETCH
    LOGIC/SPACE/$U158_O
    LOGIC/DATASP
    ICERDY
    LOGIC/READY/$U162_O
    DISNRDYF
    EPSTOP
    LOGIC/JMPHERE/$U207_O
    LOGIC/JMPHERE/$U199_O
    LOGIC/JMPHERE/$U196_O
    LOGIC/JMPHERE/$U195_O
    LOGIC/JMPHERE/U191/$U3_O
    LOGIC/JMPHERE/U191/$U2_O
    LOGIC/JMPHERE/$U190_O
    LOGIC/JMPHERE/$U189_O
    LOGIC/JMPHERE/$U186_O
    LOGIC/JMPHERE/$U185_O
    LOGIC/JMPHERE/$U183_O
    $FGDECOMP0679_LOGIC/JMPHERE/$U178_O
    $FGDECOMP0678_LOGIC/JMPHERE/$U178_O
    LOGIC/JMPHERE/$U178_O
    LOGIC/GOEP/$U176_O
    LOGIC/GOEP/$U173_O
    SSO
    NEPRUN
    goep
    icebrk
    LOGIC/EMSTATE/ICEBRK/$U468_O
    LOGIC/EMSTATE/ICEBRK/XEXBRK
    LOGIC/EMSTATE/ICEBRK/$U461_O
    RBWBRKF
    LOGIC/EMSTATE/ICEBRK/$U458_O
    LOGIC/EMSTATE/ICEBRK/$U457_O
    NENNMI
    LOGIC/EMSTATE/ICEBRK/$U452_O

    PPR RESULTS FOR DESIGN XLCW                                      Page  23

    LOGIC/EMSTATE/ICEBRK/$U446_O
    LOGIC/EMSTATE/ICEBRK/$U445_O
    LOGIC/EMSTATE/IACK
    LOGIC/EMSTATE/EN28R/$U437_O
    LOGIC/EMSTATE/EN28R/$U436_O
    LOGIC/EMSTATE/EN28R/$U433_O
    LOGIC/EMSTATE/EN28R/$U432_O
    LOGIC/EMSTATE/EN28R/$U429_O
    $FGDECOMP0680_LOGIC/EMSTATE/EN28R/$U421_O
    LOGIC/EMSTATE/EN28R/$U426_O
    LOGIC/EMSTATE/EN28R/$U424_O
    LOGIC/EMSTATE/EN28R/$U423_O
    LOGIC/EMSTATE/EN28R/$U422_O
    LOGIC/EMSTATE/EN28R/$U420_O
    LOGIC/EMSTATE/EN28R/$U419_O
    LOGIC/EMSTATE/EN28R/BUSMAT
    LOGIC/EMSTATE/EN28R/$U414_O
    emuspace
    LOGIC/EMSTATE/EMUSPACE/$U490_O
    LOGIC/EMSTATE/EMUSPACE/$U489_O
    LOGIC/EMSTATE/EMUSPACE/$U488_O
    LOGIC/EMSTATE/EMUSPACE/ETRIG1
    LOGIC/EMSTATE/EMUSPACE/$U477_O
    LOGIC/EMSTATE/EMUSPACE/$U476_O
    LOGIC/EMSTATE/EMUSPACE/$U475_O
    LOGIC/EMSTATE/EMUSPACE/ETRIG0
    LOGIC/EMSTATE/EMSI/$U590_O
    LOGIC/EMSTATE/EMSI/$U589_O
    LOGIC/EMSTATE/EMSI/$U412_O
    LOGIC/EMSTATE/EMSI/$U403_O
    LOGIC/EMSTATE/EMSI/SEMS
    LOGIC/EMSTATE/EMON/$U588_O
    LOGIC/EMSTATE/EMON/$U587_O
    LOGIC/EMSTATE/EMON/$U516_O
    LOGIC/EMSTATE/NEMON
    LOGIC/EMSTATE/CANENDS
    $FGDECOMP0681_LOGIC/EMSTATE/CANEND/CANTR
    LOGIC/EMSTATE/CANEND/CANTR
    LOGIC/EMSTATE/CANEND/$U505_O
    LOGIC/EMSTATE/CANEND/$U502_O
    LOGIC/EDGE/$U259_O
    LOGIC/EDGE/$U257_O
    LOGIC/EDGE/$U254_O
    LOGIC/EDGE/$U253_O
    LOGIC/READ28
    QUAL
    $FGDECOMP0682_LOGIC/JMPHERE6E
    LOGIC/EDGE/JHCOM/$U570_O
    LOGIC/JMPHERE6E
    LOGIC/EDGE/JHCOM/$U568_O
    $FGDECOMP0683_LOGIC/JMPHERE6A
    LOGIC/EDGE/JHCOM/$U298_O
    LOGIC/JMPHERE6A
    LOGIC/EDGE/JHCOM/$U304_O
    LOGIC/CODCOVGE/NCODRD
    LOGIC/CODCOVGE/CODWE
    LOGIC/CODCOVGE/$U331_O
    LOGIC/CODCOVGE/$U330_O
    LOGIC/CODCOVGE/$U329_O
    LOGIC/CODCOVGE/$U328_O

    PPR RESULTS FOR DESIGN XLCW                                      Page  24

    LOGIC/RDI15
    LOGIC/RDI14
    LOGIC/RDI13
    LOGIC/RDI12
    LOGIC/RDI11
    LOGIC/RDI10
    LOGIC/RDI9
    LOGIC/RDI8
    LOGIC/RDI7
    LOGIC/RDI6
    LOGIC/RDI5
    LOGIC/RDI4
    LOGIC/RDI3
    LOGIC/RDI2
    LOGIC/RDI1
    LOGIC/RDI0
    LOGIC/CANRAM/NEPINP
    LOGIC/CANRAM/CANCNT/$U395_O
    LOGIC/CANRAM/NHCPCRD1
    LOGIC/CANRAM/NLCPCRD1
    LOGIC/CANRAM/NHCPCRD0
    LOGIC/CANRAM/NLCPCRD0
    LOGIC/CANRAM/CANCNT/$U390_O
    LOGIC/CANRAM/CANCNT/$U375_O
    LOGIC/CANRAM/CANCNT/$U378_O
    LOGIC/CANRAM/HCANWR1
    LOGIC/CANRAM/CANCNT/$U372_O
    LOGIC/CANRAM/CANCNT/$U377_O
    LOGIC/CANRAM/LCANWR1
    LOGIC/CANRAM/CANCNT/$U371_O
    LOGIC/CANRAM/CANCNT/$U376_O
    LOGIC/CANRAM/HCANWR0
    LOGIC/CANRAM/CANCNT/$U368_O
    LOGIC/CANRAM/CANCNT/$U367_O
    LOGIC/CANRAM/LCANWR0
    LOGIC/CANRAM/RA5
    LOGIC/CANRAM/RA4
    LOGIC/CANRAM/RA3
    LOGIC/CANRAM/RA2
    LOGIC/CANRAM/RA1
    NINSHI
    LOGIC/ALINE/$U324_O
    CPIOPORT/PORT2
    CPIOPORT/PORT1
    CPIOPORT/PORT0
    INTRIGS
    NRDTCON
    CPIOPORT/INPORT/$U155_O
    CPIOPORT/INPORT/$U154_O
    CPIOPORT/INPORT/$U153_O
    NCODCOVGE
    LOGIC/SPOON/SPDO2
    LOGIC/SPOON/SPDO3
    LOGIC/SPOON/SPDO1
    LOGIC/SPOON/SPDO0
    LOGIC/SPOON/SPDO6
    LOGIC/SPOON/SPDO7
    LOGIC/SPOON/SPDO5
    LOGIC/SPOON/SPDO4
    LOGIC/SPOON/SPDO10

    PPR RESULTS FOR DESIGN XLCW                                      Page  25

    LOGIC/SPOON/SPDO11
    LOGIC/SPOON/SPDO9
    LOGIC/SPOON/SPDO8
    LOGIC/SPOON/SPDO14
    LOGIC/SPOON/SPDO15
    LOGIC/SPOON/SPDO13
    LOGIC/SPOON/SPDO12
    RAM32x1_LOGIC/CANRAM/LRDO4/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO4/MFG4/G
    LOGIC/CANRAM/LRDO4
    RAM32x1_LOGIC/CANRAM/LRDO5/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO5/MFG4/G
    LOGIC/CANRAM/LRDO5
    RAM32x1_LOGIC/CANRAM/LRDO6/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO6/MFG4/G
    LOGIC/CANRAM/LRDO6
    RAM32x1_LOGIC/CANRAM/LRDO7/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO7/MFG4/G
    LOGIC/CANRAM/LRDO7
    RAM32x1_LOGIC/CANRAM/LRDO3/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO3/MFG4/G
    LOGIC/CANRAM/LRDO3
    RAM32x1_LOGIC/CANRAM/LRDO2/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO2/MFG4/G
    LOGIC/CANRAM/LRDO2
    RAM32x1_LOGIC/CANRAM/LRDO1/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO1/MFG4/G
    LOGIC/CANRAM/LRDO1
    RAM32x1_LOGIC/CANRAM/LRDO0/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO0/MFG4/G
    LOGIC/CANRAM/LRDO0
    RAM32x1_LOGIC/CANRAM/HRDO4/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO4/MFG4/G
    LOGIC/CANRAM/HRDO4
    RAM32x1_LOGIC/CANRAM/HRDO5/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO5/MFG4/G
    LOGIC/CANRAM/HRDO5
    RAM32x1_LOGIC/CANRAM/HRDO6/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO6/MFG4/G
    LOGIC/CANRAM/HRDO6
    RAM32x1_LOGIC/CANRAM/HRDO7/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO7/MFG4/G
    LOGIC/CANRAM/HRDO7
    RAM32x1_LOGIC/CANRAM/HRDO3/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO3/MFG4/G
    LOGIC/CANRAM/HRDO3
    RAM32x1_LOGIC/CANRAM/HRDO2/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO2/MFG4/G
    LOGIC/CANRAM/HRDO2
    RAM32x1_LOGIC/CANRAM/HRDO1/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO1/MFG4/G
    LOGIC/CANRAM/HRDO1
    RAM32x1_LOGIC/CANRAM/HRDO0/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO0/MFG4/G
    LOGIC/CANRAM/HRDO0
    RAM32x1_LOGIC/CANRAM/LRDO12/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO12/MFG4/G
    LOGIC/CANRAM/LRDO12
    RAM32x1_LOGIC/CANRAM/LRDO13/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO13/MFG4/G

    PPR RESULTS FOR DESIGN XLCW                                      Page  26

    LOGIC/CANRAM/LRDO13
    RAM32x1_LOGIC/CANRAM/LRDO14/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO14/MFG4/G
    LOGIC/CANRAM/LRDO14
    RAM32x1_LOGIC/CANRAM/LRDO15/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO15/MFG4/G
    LOGIC/CANRAM/LRDO15
    RAM32x1_LOGIC/CANRAM/LRDO11/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO11/MFG4/G
    LOGIC/CANRAM/LRDO11
    RAM32x1_LOGIC/CANRAM/LRDO10/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO10/MFG4/G
    LOGIC/CANRAM/LRDO10
    RAM32x1_LOGIC/CANRAM/LRDO9/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO9/MFG4/G
    LOGIC/CANRAM/LRDO9
    RAM32x1_LOGIC/CANRAM/LRDO8/MFG4/F
    RAM32x1_LOGIC/CANRAM/LRDO8/MFG4/G
    LOGIC/CANRAM/LRDO8
    RAM32x1_LOGIC/CANRAM/HRDO12/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO12/MFG4/G
    LOGIC/CANRAM/HRDO12
    RAM32x1_LOGIC/CANRAM/HRDO13/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO13/MFG4/G
    LOGIC/CANRAM/HRDO13
    RAM32x1_LOGIC/CANRAM/HRDO14/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO14/MFG4/G
    LOGIC/CANRAM/HRDO14
    RAM32x1_LOGIC/CANRAM/HRDO15/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO15/MFG4/G
    LOGIC/CANRAM/HRDO15
    RAM32x1_LOGIC/CANRAM/HRDO11/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO11/MFG4/G
    LOGIC/CANRAM/HRDO11
    RAM32x1_LOGIC/CANRAM/HRDO10/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO10/MFG4/G
    LOGIC/CANRAM/HRDO10
    RAM32x1_LOGIC/CANRAM/HRDO9/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO9/MFG4/G
    LOGIC/CANRAM/HRDO9
    RAM32x1_LOGIC/CANRAM/HRDO8/MFG4/F
    RAM32x1_LOGIC/CANRAM/HRDO8/MFG4/G
    LOGIC/CANRAM/HRDO8
    
    3-state buffer with input and output signals as follows:
    -------------------------------------------------------------
    I signal=icebrk
    O signal=CDO7
    
    I signal=EPSTOP
    O signal=CDO6
    
    I signal=CPIOPORT/INPORT/$U153_O
    O signal=CDO5
    
    I signal=RBWBRKF
    O signal=CDO4
    
    I signal=TRBRKF
    O signal=CDO3

    PPR RESULTS FOR DESIGN XLCW                                      Page  27

    
    I signal=EXBP2F
    O signal=CDO2
    
    I signal=EXBP1F
    O signal=CDO1
    
    I signal=EXBPF
    O signal=CDO0
    
    I signal=FLAGNOTRDY
    O signal=CDO6
    
    I signal=NSTROBE
    O signal=CDO5
    
    I signal=CPIOPORT/BUSCYCOK
    O signal=CDO4
    
    I signal=NDMA
    O signal=CDO3
    
    I signal=RUNCAN
    O signal=CDO2
    
    I signal=RUNUSER
    O signal=CDO1
    
    I signal=emon
    O signal=CDO0
    
    I signal=CPIOPORT/$U141_P
    O signal=EDO7
    
    I signal=FLINE
    O signal=EDO6
    
    I signal=CPIOPORT/$U141_P
    O signal=EDO5
    
    I signal=FLINE
    O signal=EDO4
    
    I signal=LOGIC/EMS5
    O signal=EDO8
    
    I signal=LOGIC/CANRAM/LRDO7
    O signal=EDO7
    
    I signal=LOGIC/CANRAM/LRDO6
    O signal=EDO6
    
    I signal=LOGIC/CANRAM/LRDO5
    O signal=EDO5
    
    I signal=LOGIC/CANRAM/LRDO4
    O signal=EDO4
    
    I signal=LOGIC/CANRAM/LRDO3
    O signal=EDO3

    PPR RESULTS FOR DESIGN XLCW                                      Page  28

    
    I signal=LOGIC/CANRAM/LRDO2
    O signal=EDO2
    
    I signal=LOGIC/CANRAM/LRDO1
    O signal=EDO1
    
    I signal=LOGIC/CANRAM/LRDO0
    O signal=EDO0
    
    I signal=LOGIC/CANRAM/HRDO7
    O signal=EDO7
    
    I signal=LOGIC/CANRAM/HRDO6
    O signal=EDO6
    
    I signal=LOGIC/CANRAM/HRDO5
    O signal=EDO5
    
    I signal=LOGIC/CANRAM/HRDO4
    O signal=EDO4
    
    I signal=LOGIC/CANRAM/HRDO3
    O signal=EDO3
    
    I signal=LOGIC/CANRAM/HRDO2
    O signal=EDO2
    
    I signal=LOGIC/CANRAM/HRDO1
    O signal=EDO1
    
    I signal=LOGIC/CANRAM/HRDO0
    O signal=EDO0
    
    I signal=LOGIC/CANRAM/LRDO15
    O signal=EDO15
    
    I signal=LOGIC/CANRAM/LRDO14
    O signal=EDO14
    
    I signal=LOGIC/CANRAM/LRDO13
    O signal=EDO13
    
    I signal=LOGIC/CANRAM/LRDO12
    O signal=EDO12
    
    I signal=LOGIC/CANRAM/LRDO11
    O signal=EDO11
    
    I signal=LOGIC/CANRAM/LRDO10
    O signal=EDO10
    
    I signal=LOGIC/CANRAM/LRDO9
    O signal=EDO9
    
    I signal=LOGIC/CANRAM/LRDO8
    O signal=EDO8
    
    I signal=LOGIC/CANRAM/HRDO15
    O signal=EDO15

    PPR RESULTS FOR DESIGN XLCW                                      Page  29

    
    I signal=LOGIC/CANRAM/HRDO14
    O signal=EDO14
    
    I signal=LOGIC/CANRAM/HRDO13
    O signal=EDO13
    
    I signal=LOGIC/CANRAM/HRDO12
    O signal=EDO12
    
    I signal=LOGIC/CANRAM/HRDO11
    O signal=EDO11
    
    I signal=LOGIC/CANRAM/HRDO10
    O signal=EDO10
    
    I signal=LOGIC/CANRAM/HRDO9
    O signal=EDO9
    
    I signal=LOGIC/CANRAM/HRDO8
    O signal=EDO8
    
    I signal=LOGIC/CANRAM/LRDO7
    O signal=CDO7
    
    I signal=LOGIC/CANRAM/LRDO6
    O signal=CDO6
    
    I signal=LOGIC/CANRAM/LRDO5
    O signal=CDO5
    
    I signal=LOGIC/CANRAM/LRDO4
    O signal=CDO4
    
    I signal=LOGIC/CANRAM/LRDO3
    O signal=CDO3
    
    I signal=LOGIC/CANRAM/LRDO2
    O signal=CDO2
    
    I signal=LOGIC/CANRAM/LRDO1
    O signal=CDO1
    
    I signal=LOGIC/CANRAM/LRDO0
    O signal=CDO0
    
    I signal=LOGIC/CANRAM/HRDO7
    O signal=CDO7
    
    I signal=LOGIC/CANRAM/HRDO6
    O signal=CDO6
    
    I signal=LOGIC/CANRAM/HRDO5
    O signal=CDO5
    
    I signal=LOGIC/CANRAM/HRDO4
    O signal=CDO4
    
    I signal=LOGIC/CANRAM/HRDO3
    O signal=CDO3

    PPR RESULTS FOR DESIGN XLCW                                      Page  30

    
    I signal=LOGIC/CANRAM/HRDO2
    O signal=CDO2
    
    I signal=LOGIC/CANRAM/HRDO1
    O signal=CDO1
    
    I signal=LOGIC/CANRAM/HRDO0
    O signal=CDO0
    
    I signal=LOGIC/CANRAM/LRDO15
    O signal=CDO7
    
    I signal=LOGIC/CANRAM/LRDO14
    O signal=CDO6
    
    I signal=LOGIC/CANRAM/LRDO13
    O signal=CDO5
    
    I signal=LOGIC/CANRAM/LRDO12
    O signal=CDO4
    
    I signal=LOGIC/CANRAM/LRDO11
    O signal=CDO3
    
    I signal=LOGIC/CANRAM/LRDO10
    O signal=CDO2
    
    I signal=LOGIC/CANRAM/LRDO9
    O signal=CDO1
    
    I signal=LOGIC/CANRAM/LRDO8
    O signal=CDO0
    
    I signal=LOGIC/CANRAM/HRDO15
    O signal=CDO7
    
    I signal=LOGIC/CANRAM/HRDO14
    O signal=CDO6
    
    I signal=LOGIC/CANRAM/HRDO13
    O signal=CDO5
    
    I signal=LOGIC/CANRAM/HRDO12
    O signal=CDO4
    
    I signal=LOGIC/CANRAM/HRDO11
    O signal=CDO3
    
    I signal=LOGIC/CANRAM/HRDO10
    O signal=CDO2
    
    I signal=LOGIC/CANRAM/HRDO9
    O signal=CDO1
    
    I signal=LOGIC/CANRAM/HRDO8
    O signal=CDO0
    
    I signal=FLAGNOTRDY
    O signal=EDO8

    PPR RESULTS FOR DESIGN XLCW                                      Page  31

    
    I signal=NCODCOVGE
    O signal=CDO0
    
    I signal=LOGIC/SPOON/SPADD/TCA0
    O signal=CDO0
    
    I signal=LOGIC/SPOON/SPADD/TCA1
    O signal=CDO1
    
    I signal=LOGIC/SPOON/SPADD/TCA2
    O signal=CDO2
    
    I signal=LOGIC/SPOON/SPDO7
    O signal=EDO7
    
    I signal=LOGIC/SPOON/SPDO6
    O signal=EDO6
    
    I signal=LOGIC/SPOON/SPDO5
    O signal=EDO5
    
    I signal=LOGIC/SPOON/SPDO4
    O signal=EDO4
    
    I signal=LOGIC/SPOON/SPDO3
    O signal=EDO3
    
    I signal=LOGIC/SPOON/SPDO2
    O signal=EDO2
    
    I signal=LOGIC/SPOON/SPDO1
    O signal=EDO1
    
    I signal=LOGIC/SPOON/SPDO0
    O signal=EDO0
    
    I signal=LOGIC/SPOON/SPDO15
    O signal=EDO15
    
    I signal=LOGIC/SPOON/SPDO14
    O signal=EDO14
    
    I signal=LOGIC/SPOON/SPDO13
    O signal=EDO13
    
    I signal=LOGIC/SPOON/SPDO12
    O signal=EDO12
    
    I signal=LOGIC/SPOON/SPDO11
    O signal=EDO11
    
    I signal=LOGIC/SPOON/SPDO10
    O signal=EDO10
    
    I signal=LOGIC/SPOON/SPDO9
    O signal=EDO9
    
    I signal=LOGIC/SPOON/SPDO8
    O signal=EDO8

    PPR RESULTS FOR DESIGN XLCW                                      Page  32

    
    I signal=LOGIC/SPOON/SPDO7
    O signal=CDO7
    
    I signal=LOGIC/SPOON/SPDO6
    O signal=CDO6
    
    I signal=LOGIC/SPOON/SPDO5
    O signal=CDO5
    
    I signal=LOGIC/SPOON/SPDO4
    O signal=CDO4
    
    I signal=LOGIC/SPOON/SPDO3
    O signal=CDO3
    
    I signal=LOGIC/SPOON/SPDO2
    O signal=CDO2
    
    I signal=LOGIC/SPOON/SPDO1
    O signal=CDO1
    
    I signal=LOGIC/SPOON/SPDO0
    O signal=CDO0
    
    I signal=LOGIC/SPOON/SPDO15
    O signal=CDO7
    
    I signal=LOGIC/SPOON/SPDO14
    O signal=CDO6
    
    I signal=LOGIC/SPOON/SPDO13
    O signal=CDO5
    
    I signal=LOGIC/SPOON/SPDO12
    O signal=CDO4
    
    I signal=LOGIC/SPOON/SPDO11
    O signal=CDO3
    
    I signal=LOGIC/SPOON/SPDO10
    O signal=CDO2
    
    I signal=LOGIC/SPOON/SPDO9
    O signal=CDO1
    
    I signal=LOGIC/SPOON/SPDO8
    O signal=CDO0
    
    
    Input/Output pads as follows:
    ------------------------------------------------------------
    XPAD/XBPAD/CDBUS/CPAD0
    XPAD/XBPAD/CDBUS/CPAD1
    XPAD/XBPAD/CDBUS/CPAD2
    XPAD/XBPAD/CDBUS/CPAD3
    XPAD/XBPAD/CDBUS/CPAD4
    XPAD/XBPAD/CDBUS/CPAD5
    XPAD/XBPAD/CDBUS/CPAD6
    XPAD/XBPAD/CDBUS/CPAD7

    PPR RESULTS FOR DESIGN XLCW                                      Page  33

    XPAD/XBPAD/EDBUS/$U1_O0
    XPAD/XBPAD/EDBUS/$U1_O1
    XPAD/XBPAD/EDBUS/$U1_O2
    XPAD/XBPAD/EDBUS/$U1_O3
    XPAD/XBPAD/EDBUS/$U1_O4
    XPAD/XBPAD/EDBUS/$U1_O5
    XPAD/XBPAD/EDBUS/$U1_O6
    XPAD/XBPAD/EDBUS/$U3_O0
    XPAD/XBPAD/EDBUS/$U3_O1
    XPAD/XBPAD/EDBUS/$U3_O2
    XPAD/XBPAD/EDBUS/$U3_O3
    XPAD/XBPAD/EDBUS/$U3_O4
    XPAD/XBPAD/EDBUS/$U3_O5
    XPAD/XBPAD/EDBUS/$U3_O6
    XPAD/XBPAD/EDBUS/$U3_O7
    XPAD/XINPAD/$U76_IPAD
    XPAD/XINPAD/$U77_IPAD
    XPAD/XINPAD/$U78_IPAD
    XPAD/XINPAD/CPINPAD/$U86_IPAD
    XPAD/XINPAD/CPINPAD/$U88_IPAD
    XPAD/XINPAD/CPINPAD/$U90_IPAD
    XPAD/XINPAD/EAESPAD/$U138_IPAD
    XPAD/XOUTPAD/$U40_O1
    XPAD/XOUTPAD/$U40_O2
    XPAD/XOUTPAD/$U40_O3
    XPAD/XOUTPAD/$U40_O4
    XPAD/XOUTPAD/$U40_O5
    XPAD/XOUTPAD/$U40_O6
    XPAD/XOUTPAD/$U43_O2
    XPAD/XOUTPAD/$U44_O0
    XPAD/XOUTPAD/$U44_O1
    XPAD/XOUTPAD/$U44_O2
    XPAD/XOUTPAD/$U45_O
    XPAD/XOUTPAD/$U522_O
    
    Other LCA Elements:
    -----------------------------------------------------------

    PPR RESULTS FOR DESIGN XLCW                                      Page  34

    Unguided Signals from Input Design
    ----------------------------------
    
    
    The following list shows which signals in the input design could not
    use ALL of the routing information specified for them in the guide
    file.
    
    Signals in the input design that do not exist in the guide file are
    not included in this list.
    
     Signal Name
    --------------------------------------------------------------
    CDO7
    icebrk
    CPIOPORT/INPORT/$U154_O
    CDO6
    EPSTOP
    CDO5
    CPIOPORT/INPORT/$U153_O
    CDO4
    RBWBRKF
    CDO3
    TRBRKF
    CDO2
    EXBP2F
    CDO1
    EXBP1F
    CDO0
    EXBPF
    FLAGNOTRDY
    CPIOPORT/INPORT/$U155_O
    NSTROBE
    CPIOPORT/BUSCYCOK
    NDMA
    RUNCAN
    RUNUSER
    emon
    NVIOLBRK
    CPIOPORT/PORT0
    NCPRD
    CPIOPORT/PORT1
    NRDTCON
    CPIOPORT/PORT2
    INSTEP
    CDI0
    NCPWR
    CLRBRKF
    CDI1
    CLRRUNF
    CDI2
    FORCERDY
    CDI3
    ENQUAL
    CDI4
    FORCEBRK
    CDI6
    RELOC
    CDI7
    ENSWBP

    PPR RESULTS FOR DESIGN XLCW                                      Page  35

    DISINT
    ENSSI
    ESCSSI
    ENSSO
    ENBP1
    CDI5
    ENBP2
    SEMS0
    SEMS5
    SJS0
    SJS3
    ENALINE
    FLINE
    CPIOPORT/OUTPUT/CNFEND
    CPIOPORT/BUSCTEST
    NCNFOK
    NEMVALID
    INTRIGS
    NMCS2H1
    CA1
    CA0
    EDO7
    LOGIC/NHBUSMAT
    EDO6
    EDO5
    EDO4
    LOGIC/ALINE/$U324_O
    LOGIC/FORCE2AR
    NINSHI
    NADVALID
    EDO8
    LOGIC/EMS5
    LOGIC/CANRAM/RA1
    NMCS2H0
    EA1
    LOGIC/CANRAM/RA2
    CA2
    EA2
    LOGIC/CANRAM/RA3
    CA3
    EA3
    LOGIC/CANRAM/RA4
    CA4
    EA4
    LOGIC/CANRAM/RA5
    CA5
    EA5
    CA7
    CA6
    EA6
    EA7
    LOGIC/NXEWR0
    LOGIC/CANRAM/CANCNT/$U395_O
    LOGIC/CANRAM/LCANWR0
    LOGIC/CANRAM/HCANWR0
    LOGIC/NXEWR1
    LOGIC/CANRAM/LCANWR1
    LOGIC/CANRAM/HCANWR1
    LOGIC/CANRAM/NLEPCRD
    LOGIC/CANRAM/NHEPCRD

    PPR RESULTS FOR DESIGN XLCW                                      Page  36

    LOGIC/CANRAM/CANCNT/$U390_O
    LOGIC/CANRAM/NLCPCRD0
    LOGIC/CANRAM/NHCPCRD0
    LOGIC/CANRAM/NLCPCRD1
    LOGIC/CANRAM/NHCPCRD1
    emuspace
    LOGIC/CANRAM/NEPINP
    LOGIC/RDI0
    EDI0
    LOGIC/RDI1
    EDI1
    LOGIC/RDI2
    EDI2
    LOGIC/RDI3
    EDI3
    LOGIC/RDI4
    EDI4
    LOGIC/RDI5
    EDI5
    LOGIC/RDI6
    EDI6
    LOGIC/RDI7
    EDI7
    LOGIC/RDI8
    EDI8
    LOGIC/RDI9
    EDI9
    LOGIC/RDI10
    EDI10
    LOGIC/RDI11
    EDI11
    LOGIC/RDI12
    EDI12
    LOGIC/RDI13
    EDI13
    LOGIC/RDI14
    EDI14
    LOGIC/RDI15
    EDI15
    LOGIC/CANRAM/LRDO7
    LOGIC/CANRAM/LRDO6
    LOGIC/CANRAM/LRDO5
    LOGIC/CANRAM/LRDO4
    EDO3
    LOGIC/CANRAM/LRDO3
    EDO2
    LOGIC/CANRAM/LRDO2
    EDO1
    LOGIC/CANRAM/LRDO1
    EDO0
    LOGIC/CANRAM/LRDO0
    LOGIC/CANRAM/HRDO7
    LOGIC/CANRAM/HRDO6
    LOGIC/CANRAM/HRDO5
    LOGIC/CANRAM/HRDO4
    LOGIC/CANRAM/HRDO3
    LOGIC/CANRAM/HRDO2
    LOGIC/CANRAM/HRDO1
    LOGIC/CANRAM/HRDO0
    EDO15

    PPR RESULTS FOR DESIGN XLCW                                      Page  37

    LOGIC/CANRAM/LRDO15
    EDO14
    LOGIC/CANRAM/LRDO14
    EDO13
    LOGIC/CANRAM/LRDO13
    EDO12
    LOGIC/CANRAM/LRDO12
    EDO11
    LOGIC/CANRAM/LRDO11
    EDO10
    LOGIC/CANRAM/LRDO10
    EDO9
    LOGIC/CANRAM/LRDO9
    LOGIC/CANRAM/LRDO8
    LOGIC/CANRAM/HRDO15
    LOGIC/CANRAM/HRDO14
    LOGIC/CANRAM/HRDO13
    LOGIC/CANRAM/HRDO12
    LOGIC/CANRAM/HRDO11
    LOGIC/CANRAM/HRDO10
    LOGIC/CANRAM/HRDO9
    LOGIC/CANRAM/HRDO8
    NCODCOVGE
    LOGIC/CODCOVGE/$U331_O
    LOGIC/CODCOVGE/$U330_O
    LOGIC/CODCOVGE/$U329_O
    LOGIC/CODCOVGE/$U328_O
    LOGIC/CODCOVGE/CODWE
    EPFC0
    EPFC1
    EPFC2
    XPAD/EPOE
    LOGIC/CODCOVGE/NCODRD
    LOGIC/EDGE/EXBP1T
    EA8
    EA9
    LOGIC/EDGE/EXBP1B
    LOGIC/EDGE/EXBP2T
    LOGIC/EDGE/EXBP2B
    LOGIC/EDGE/JHCOM/$U304_O
    LOGIC/JMPHERE6A
    LOGIC/EDGE/JHCOM/$U568_O
    LOGIC/JMPHERE6E
    LOGIC/EDGE/QUALIFY/QUALB
    LOGIC/EDGE/QUALIFY/QUALT
    QUAL
    LOGIC/EDGE/R28COM/READ28T
    LOGIC/EDGE/R28COM/READ28B
    LOGIC/EN28RCOM
    LOGIC/READ28
    LOGIC/READ
    NINSLOW
    ICECLK
    LOGIC/EMSTATE/CANEND/CANES0
    LOGIC/EMSTATE/CANEND/CANES1
    LOGIC/FETCH
    LOGIC/EMSTATE/CANEND/CANTR
    LOGIC/WRITE
    LOGIC/EMSTATE/CANENDS
    BRKACK

    PPR RESULTS FOR DESIGN XLCW                                      Page  38

    LOGIC/EMSTATE/EMON/$U512_Q
    LOGIC/EMSTATE/NEMON
    LOGIC/EMSTATE/EMS2
    LOGIC/EMS7
    LOGIC/TRAMEN
    LOGIC/EMS8
    LOGIC/EMSTATE/EMS0
    LOGIC/EMSTATE/EMSI/EMS1
    LOGIC/EMSTATE/EMSI/SEMS
    LOGIC/EMS3
    LOGIC/EMSTATE/IACK
    LOGIC/EMS4
    LOGIC/EMS6
    LOGIC/EMSTATE/EMUSPACE/ETRIG0
    LOGIC/EMSTATE/EMUSPACE/DEXT0
    LOGIC/EMSTATE/EMUSPACE/DEXT1
    LOGIC/EMSTATE/EMUSPACE/DEXT2
    LOGIC/DATASP
    LOGIC/EMSTATE/EMUSPACE/ETRIG1
    LOGIC/EMSTATE/EMUSPACE/SEXT0
    LOGIC/EMSTATE/EMUSPACE/SEXT1
    LOGIC/EMSTATE/EMUSPACE/SEXT2
    LOGIC/EMSTATE/EN28R/EXS3
    LOGIC/EMSTATE/EN28R/EXS0
    LOGIC/EMSTATE/EN28R/BUSMAT
    LOGIC/EMSTATE/EN28R/EXS5
    LOGIC/EMSTATE/EN28R/EXS1
    LOGIC/EMSTATE/EN28R/$U420_O
    LOGIC/EMSTATE/EN28R/$U422_O
    LOGIC/EMSTATE/EN28R/EXS2
    LOGIC/EMSTATE/EN28R/$U437_O
    LOGIC/EMSTATE/ICEBRK/$U448_Q
    LOGIC/EMSTATE/ICEBRK/XEXBRK
    LOGIC/EMSTATE/ICEBRK/$U449_Q
    LOGIC/EMSTATE/ICEBRK/$U451_Q
    LOGIC/EMSTATE/ICEBRK/$U452_O
    NENNMI
    LOGIC/EMSTATE/ICEBRK/$U457_O
    LOGIC/EMSTATE/ICEBRK/$U456_Q
    LOGIC/EMSTATE/ICEBRK/$U458_O
    NTRIGBRK
    NRBWBRK
    LOGIC/EMSTATE/ICEBRK/$U461_O
    LOGIC/EMSTATE/ICEBRK/$U462_Q
    LOGIC/EMSTATE/ICEBRK/$U465_Q
    LOGIC/EMSTATE/ICEBRK/$U466_Q
    LOGIC/EMSTATE/ICEBRK/INSTEPBRK
    LOGIC/GOEP/$U164_Q
    XSSI
    LOGIC/SSI
    LOGIC/GOEP/$U167_Q
    LOGIC/GOEP/$U168_Q
    goep
    NEPRUN
    LOGIC/GOEP/$U171_Q
    SSO
    LOGIC/JMPHERE/JS0
    LOGIC/JMPHERE/JS3
    LOGIC/JMPHERE/JS1
    LOGIC/JMPHERE/$U199_O

    PPR RESULTS FOR DESIGN XLCW                                      Page  39

    LOGIC/JMPHERE/JS2
    LOGIC/JMPHERE/U191/$U3_O
    DISNRDYF
    ICERDY
    LOGIC/SPACE/$U158_O
    LOGIC/SPACE/$U576_O
    LOGIC/SPOON/SPADD/TCA0
    LOGIC/SPOON/SPADD/$U213_O
    LOGIC/SPOON/SPADD/TCA1
    LOGIC/SPOON/SPADD/TCA2
    LOGIC/SPOON/SPA4
    LOGIC/SPOON/SPA3
    LOGIC/SPOON/SPA2
    LOGIC/SPOON/SPA1
    LOGIC/SPOON/SPDO7
    LOGIC/SPOON/SPDBUF/$U248_O
    LOGIC/SPOON/SPDO6
    LOGIC/SPOON/SPDO5
    LOGIC/SPOON/SPDO4
    LOGIC/SPOON/SPDO3
    LOGIC/SPOON/SPDO2
    LOGIC/SPOON/SPDO1
    LOGIC/SPOON/SPDO0
    LOGIC/SPOON/SPDO15
    LOGIC/SPOON/SPDO14
    LOGIC/SPOON/SPDO13
    LOGIC/SPOON/SPDO12
    LOGIC/SPOON/SPDO11
    LOGIC/SPOON/SPDO10
    LOGIC/SPOON/SPDO9
    LOGIC/SPOON/SPDO8
    LOGIC/SPOON/SPDBUF/$U249_O
    LOGIC/SPOON/SPDBUF/$U250_O
    LOGIC/SPOON/SPWRITE/$U230_O
    LOGIC/SPOON/SPWRITE0
    NLDS
    LOGIC/SPOON/SPWRITE/EPCWRQ
    LOGIC/SPOON/SPWRITE/$U234_O
    LOGIC/SPOON/SPWRITE1
    NUDS
    LOGIC/SPOON/SPWRITE/$U238_Q
    LOGIC/SPOON/SPWRITE/$U239_Q
    XPAD/CPALE
    XPAD/XBPAD/CDBUS/NENCDB
    XPAD/XBPAD/EDBUS/NEDLOW
    XPAD/XBPAD/EDBUS/NEDHI
    XPAD/XINPAD/CPINPAD/CPCLK
    XPAD/XINPAD/CPINPAD/$U90_IPAD
    XPAD/XINPAD/CPINPAD/$U81_Q
    XPAD/XINPAD/CPINPAD/NWR
    XPAD/XINPAD/$U75_IPAD
    XPAD/XINPAD/$U76_IPAD
    XPAD/XINPAD/$U77_IPAD
    XPAD/XINPAD/$U78_IPAD

    PPR RESULTS FOR DESIGN XLCW                                      Page  40

    Information in Other Reports
    ----------------------------
    
    
    Since not all pertinent design information is listed in this PPR
    report file, this section describes where additional information can
    be found.
    
    
    Information                                  Report File  Created By
    -----------------------------------------    -----------  ----------
    
    
    Connection of signals between levels of      design.mrg   XNFMERGE
    design hierarchy
    
    Resolution of relative location (RLOC)       design.mrg   XNFMERGE
    constraints through design hierarchy
    
    X-BLOX designs: design rule check for        design.prx   XNFPREP
    pre-expanded design
    
    X-BLOX designs: results of optimization      design.blx   XBLOX
    and module expansion in X-BLOX
    
    Design rule check for invalid and/or         design.prp   XNFPREP
    inefficient use of LCA architecture
    
    Unused or disabled logic removed from        design.prp   XNFPREP
    design, due to sourceless or loadless
    signals and VCC or ground connections
    
    XC3000A/L designs: Mapping of design         design.crf   XNFMAP
    logic into each CLB or IOB
    
    XC3000A/L designs: Summary of guided         design.crf   XNFMAP
    partitioning results
    
    ========== End of Report ==========
