Project Information                             d:\orcad\3vea7032\3vea7032.rpt

MAX+plus II Compiler Report File
Version 2.20 08/17/92



***** Project compiled without errors




** DEVICE SUMMARY **

Chip/                   Input   Output   Bidir         Shareable
POF       Device        Pins    Pins     Pins     MCs    EXPs     % Utilized

3VEA7032  EPM7032LC44-1  22       13       0      27      4           84 %



Project Information                             d:\orcad\3vea7032\3vea7032.rpt

** PIN/MC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

3VEA7032@19                       BUFNICEBRK
3VEA7032@4                        BUF0
3VEA7032@38                       ECTL3
3VEA7032@33                       EMPTY
3VEA7032@8                        EPSGN3
3VEA7032@28                       EPSGN4
3VEA7032@9                        EPSGN8
3VEA7032@13                       EPS0
3VEA7032@14                       EPS1
3VEA7032@16                       EPS2
3VEA7032@17                       EPS3
3VEA7032@21                       EPS6
3VEA7032@20                       EPS7
3VEA7032@1                        EPT4
3VEA7032@11                       EPT5
3VEA7032@29                       ESGN7
3VEA7032@34                       ESGN8
3VEA7032@36                       ESGN9
3VEA7032@37                       ESGN10
3VEA7032@24                       ES0
3VEA7032@25                       ES1
3VEA7032@26                       ES2
3VEA7032@27                       ES3
3VEA7032@7                        ETB2
3VEA7032@43                       GICECLK
3VEA7032@44                       ICECLK1
3VEA7032@2                        NEPRES
3VEA7032@40                       NERD
3VEA7032@41                       NEWR
3VEA7032@18                       NICEBRK
3VEA7032@12                       NICERES
3VEA7032@31                       NONCEDRV
3VEA7032@32                       NPOWERUP
3VEA7032@39                       NSTROBE
3VEA7032@5                        QSMD


Project Information                             d:\orcad\3vea7032\3vea7032.rpt

** FILE HIERARCHY **



|74174:36|
|7474:47|
|7474:46|
|7474:45|
|7474:44|
|7474:43|
|7474:42|
|7474:41|
|7474:40|
|7474:39|
|7474:38|
|7474:37|


3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

***** Logic for device '3VEA7032' compiled without errors

           


Device: EPM7032LC44-1
Turbo: ON
Security: OFF
                                                 
                                                 
                R                                
                E                 I  G           
                S           N     C  I           
                E           E     E  C           
                R  Q  B     P  E  C  E     N  N  
                V  S  U  V  R  P  L  C  G  E  E  
                E  M  F  C  E  T  K  L  N  W  R  
                D  D  0  C  S  4  1  K  D  R  D  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
      ETB2 |  7                                39 | NSTROBE 
    EPSGN3 |  8                                38 | ECTL3 
    EPSGN8 |  9                                37 | ESGN10 
       GND | 10                                36 | ESGN9 
      EPT5 | 11                                35 | VCC 
   NICERES | 12         EPM7032LC44-1          34 | ESGN8 
      EPS0 | 13                                33 | EMPTY 
      EPS1 | 14                                32 | NPOWERUP 
       VCC | 15                                31 | NONCEDRV 
      EPS2 | 16                                30 | GND 
      EPS3 | 17                                29 | ESGN7 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                N  B  E  E  G  V  E  E  E  E  E  
                I  U  P  P  N  C  S  S  S  S  P  
                C  F  S  S  D  C  0  1  2  3  S  
                E  N  7  6                    G  
                B  I                          N  
                R  C                          4  
                K  E                             
                   B                             
                   R                             
                   K                             


3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

** RESOURCE USAGE **                                                  

                                                Shareable     External
Logic Array Block     Macrocells    I/O Pins    Expanders   Interconnect

A:     MC1 - MC16    16/16(100%)  15/16( 93%)   2/16( 12%)  27/36( 75%) 
B:    MC17 - MC32    11/16( 68%)  16/16(100%)   2/16( 12%)  22/36( 61%) 


Total dedicated input pins used:                 4/  4 (100%)
Total I/O pins used:                            31/ 32 ( 96%)
Total macrocells used:                          27/ 32 ( 84%)
Total shareable expanders used:                  4/ 32 ( 12%)
Total turbo macrocells used:                    27/ 32 ( 84%)
Total shareable expanders not available (n/a):   0/ 32 (  0%)

Total input pins required:                      22
Total output pins required:                     13
Total bidirectional pins required:               0
Total macrocells required:                      27
Total shareable expanders in database:           4

Synthesized macrocells:                          0/ 32 (  0%)



3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

** INPUTS **                                                          

                                     Shareable
                                     Expanders     Fan-In
 Pin  MCell  LAB  Primitive      Total Shared n/a  INP  FBK  Name
   4    (1)  (A)      INPUT         0      0   0   0    0  BUF0
  38   (20)  (B)      INPUT         0      0   0   0    0  ECTL3
   8    (5)  (A)      INPUT         0      0   0   0    0  EPSGN3
  28   (28)  (B)      INPUT         0      0   0   0    0  EPSGN4
  13    (9)  (A)      INPUT         0      0   0   0    0  EPS0
  14   (10)  (A)      INPUT         0      0   0   0    0  EPS1
  16   (11)  (A)      INPUT         0      0   0   0    0  EPS2
  17   (12)  (A)      INPUT         0      0   0   0    0  EPS3
  21   (16)  (A)      INPUT         0      0   0   0    0  EPS6
  20   (15)  (A)      INPUT         0      0   0   0    0  EPS7
   1      -   -       INPUT         0      0   0   0    0  EPT4
  11    (7)  (A)      INPUT         0      0   0   0    0  EPT5
  24   (32)  (B)      INPUT         0      0   0   0    0  ES0
  25   (31)  (B)      INPUT         0      0   0   0    0  ES1
  26   (30)  (B)      INPUT         0      0   0   0    0  ES2
  27   (29)  (B)      INPUT         0      0   0   0    0  ES3
  43      -   -       INPUT         0      0   0   0    0  GICECLK
  44      -   -       INPUT         0      0   0   0    0  ICECLK1
   2      -   -       INPUT         0      0   0   0    0  NEPRES
  18   (13)  (A)      INPUT         0      0   0   0    0  NICEBRK
  12    (8)  (A)      INPUT         0      0   0   0    0  NICERES
  32   (25)  (B)      INPUT         0      0   0   0    0  NPOWERUP


3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

** OUTPUTS **                                                         

                                     Shareable
                                     Expanders     Fan-In
 Pin  MCell  LAB  Primitive      Total Shared n/a  INP  FBK  Name
  19     14    A       DFFE   t     0      0   0   2    0  BUFNICEBRK
  33     24    B       DFFE   t     0      0   0   1    1  EMPTY
   9      6    A     OUTPUT   t     0      0   0   2    1  EPSGN8
  29     27    B     OUTPUT   t     0      0   0   5    0  ESGN7
  34     23    B       DFFE   t     1      0   0   5    1  ESGN8
  36     22    B     OUTPUT   t     0      0   0   0    2  ESGN9
  37     21    B       DFFE   t     0      0   0   4    2  ESGN10
   7      4    A     OUTPUT   t     0      0   0   1    2  ETB2
  40     18    B     OUTPUT   t     0      0   0   1    1  NERD
  41     17    B     OUTPUT   t     0      0   0   2    1  NEWR
  31     26    B       DFFE   t     1      0   0   3    1  NONCEDRV
  39     19    B       DFFE   t     0      0   0   1    1  NSTROBE
   5      2    A       DFFE   t     0      0   0   3    0  QSMD


3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

** BURIED LOGIC **                                                    

                                     Shareable
                                     Expanders     Fan-In
 Pin  MCell  LAB  Primitive      Total Shared n/a  INP  FBK  Name
 (16)    11    A       DFFE   t     0      0   0   5    0  |U5|1Q
 (13)     9    A       DFFE   t     0      0   0   4    1  |U9|1Q
  (8)     5    A       DFFE   t     0      0   0   2    2  |U21|1Q
 (14)    10    A       DFFE   t     1      1   0   5    2  |U21|2Q
 (21)    16    A       DFFE   t     1      1   0   1    2  |U28|1Q
  (4)     1    A       DFFE   t     0      0   0   1    1  |U29|:9
 (17)    12    A       DFFE   t     0      0   0   1    1  |U29|:10
 (18)    13    A       DFFE   t     0      0   0   1    1  |U29|:11
  (6)     3    A       DFFE   t     0      0   0   2    0  |U29|:12
 (11)     7    A       DFFE   t     1      1   0   8    1  |U43|1Q
 (20)    15    A       DFFE   t     1      1   0   6    1  |U43|2Q
 (12)     8    A       DFFE   t     0      0   0   2    1  |U48|1Q
 (26)    30    B       DFFE   t     0      0   0   4    0  |U58|1Q
 (27)    29    B       DFFE   t     0      0   0   1    1  |U58|2Q


3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

** MACROCELL INTERCONNECTIONS **                                      

Logic Array Block 'A':

        M M M M M M M M M M M M M M M M 
        C C C C C C C C C C C C C C C C 
        1 6 4 2 1 9 5 1 1 1 1 1 3 7 1 8 
        4 | | | 1 | | 0 6 | 2 3 | | 5 | 
MCELL   | | | | | | | | | | | | | | | | | A B | Name
MC5  -> - - - - - - - * * - - - - - - - | * - | |U21|1Q
MC10 -> - - - - - - * - - - - - - - - - | * * | |U21|2Q
MC16 -> - - - - - - - * - - - - - - - - | * - | |U28|1Q
MC1  -> - - * - - - - - - - * - - - - - | * - | |U29|:9
MC12 -> - - - - - - - - - - - * - - - - | * - | |U29|:10
MC13 -> - - * - - - - - - - - - - - - - | * - | |U29|:11
MC3  -> - - - - - - - - - * - - - - - - | * - | |U29|:12
MC7  -> - - - - - - - - - - - - - - * - | * - | |U43|1Q
MC15 -> - * - - - - - - - - - - - * - - | * - | |U43|2Q

Pin
4    -> - * - - - - - - - - - - * * - - | * - | BUF0
38   -> - * - - - - - - - - - - - * - - | * - | ECTL3
8    -> - - * - - - - - - - - - - * - - | * - | EPSGN3
13   -> - - - - * * - * - - - - - * * - | * * | EPS0
14   -> - - - - * * - * - - - - - * * - | * * | EPS1
16   -> - - - - * * - * - - - - - * * - | * * | EPS2
17   -> - - - - * * - * - - - - - * * - | * * | EPS3
21   -> - - - - - - - - - - - - - - - * | * - | EPS6
20   -> - - - - - - - - - - - - - - - * | * - | EPS7
1    -> - - - * - - - - - - - - - - - - | * - | EPT4
11   -> - - - - - - * * * - - - - * * - | * - | EPT5
43   -> - - - - * - - - - * * * * - * - | * * | GICECLK
44   -> * - - - - - * - - - - - - - - - | * * | ICECLK1
2    -> - - - * - - - - - - - - - - - - | * * | NEPRES
18   -> * - - - - - - - - - - - - - - - | * - | NICEBRK
12   -> - - - * - - - - - - - - - - - - | * * | NICERES
MC23 -> - - - - - * - - * - - - - - - - | * * | ESGN8
MC19 -> - - - - - - * - - - - - - - - * | * * | NSTROBE


3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

** MACROCELL INTERCONNECTIONS **                                      

Logic Array Block 'B':

        M M M M M M M M M M M 
        C C C C C C C C C C C 
        2 2 2 2 2 1 1 2 1 3 2 
        4 7 3 2 1 8 7 6 9 0 9 
MCELL   | | | | | | | | | | | | A B | Name
MC23 -> - - - - * - - - - - - | * * | ESGN8
MC19 -> - - - * * * * - - - - | * * | NSTROBE
MC30 -> - - - - - - - - - - * | - * | |U58|1Q
MC29 -> - - - - - - - * - - - | - * | |U58|2Q

Pin
28   -> - * - - - - - - - - - | - * | EPSGN4
13   -> - - * - * - - - - - - | * * | EPS0
14   -> - - * - * - - - - - - | * * | EPS1
16   -> - - * - * - - - - - - | * * | EPS2
17   -> - - * - * - - - - - - | * * | EPS3
1    -> - - - - - - - - - - - | * - | EPT4
24   -> - * - - - - * - - - - | - * | ES0
25   -> - * - - - * * - - - - | - * | ES1
26   -> - * - - - - - - - - - | - * | ES2
27   -> - * - - - - - - - - - | - * | ES3
43   -> * - - - - - - - * * * | * * | GICECLK
44   -> - - * - - - - - - - - | * * | ICECLK1
2    -> - - - - - - - * - * - | * * | NEPRES
12   -> - - - - - - - * - * - | * * | NICERES
32   -> - - - - - - - * - * - | - * | NPOWERUP
MC11 -> - - - - - - - - * - - | - * | |U5|1Q
MC9  -> - - * - - - - - - - - | - * | |U9|1Q
MC10 -> - - - * - - - - - - - | * * | |U21|2Q
MC8  -> * - - - - - - - - - - | - * | |U48|1Q


3VEA7032                                        d:\orcad\3vea7032\3vea7032.rpt

** EQUATIONS **                                                       

BUF0     : INPUT;
ECTL3    : INPUT;
EPSGN3   : INPUT;
EPSGN4   : INPUT;
EPS0     : INPUT;
EPS1     : INPUT;
EPS2     : INPUT;
EPS3     : INPUT;
EPS6     : INPUT;
EPS7     : INPUT;
EPT4     : INPUT;
EPT5     : INPUT;
ES0      : INPUT;
ES1      : INPUT;
ES2      : INPUT;
ES3      : INPUT;
GICECLK  : INPUT;
ICECLK1  : INPUT;
NEPRES   : INPUT;
NICEBRK  : INPUT;
NICERES  : INPUT;
NPOWERUP : INPUT;

% BUFNICEBRK = |U57|1Q %
BUFNICEBRK =  _MC014;
 _MC014  = DFFE(  NICEBRK $  GND,  ICECLK1,  VCC,  VCC,  VCC );

% EMPTY    = |U48|2Q %
EMPTY    =  _MC024;
 _MC024  = DFFE(  _MC008 $  GND,  GICECLK,  VCC,  VCC,  VCC );

EPSGN8   =  _MC006;
 _MC006  = MCELL(  _EQ001 $  BUF0 );
  _EQ001 = !BUF0 &  ECTL3 &  _MC015;

ESGN7    =  _MC027;
 _MC027  = MCELL(  _EQ002 $  VCC );
  _EQ002 =  EPSGN4 & !ES0 &  ES2 &  ES3
         #  EPSGN4 & !ES1 &  ES2 &  ES3;

% ESGN8    = |U9|2Q %
ESGN8    =  _MC023;
 _MC023  = DFFE( !_MC009 $  GND,  ICECLK1, !_EQ003, !_EQ004,  VCC );
  _EQ003 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ004 = !_MC009 &  _X001;
  _X001  = EXP(  EPS0 &  EPS1 &  EPS2 &  EPS3 );

ESGN9    =  _MC022;
 _MC022  = MCELL(  _EQ005 $  VCC );
  _EQ005 = !_MC010 & !_MC019;

% ESGN10   = |U13|1Q %
ESGN10   =  _MC021;
 _MC021  = DFFE(  GND $  GND, !_MC023,  VCC, !_EQ006,  VCC );
  _EQ006 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  _MC019;

ETB2     =  _MC004;
 _MC004  = MCELL(  _EQ007 $  GND );
  _EQ007 =  EPSGN3 &  _MC001 &  _MC013;

NERD     =  _MC018;
 _MC018  = MCELL(  _EQ008 $  VCC );
  _EQ008 = !ES1 & !_MC019;

NEWR     =  _MC017;
 _MC017  = MCELL(  _EQ009 $  VCC );
  _EQ009 = !ES0 &  ES1 & !_MC019;

% NONCEDRV = |U50|1Q %
NONCEDRV =  _MC026;
 _MC026  = DFFE(  GND $  VCC,  _MC029, !_EQ010,  VCC,  VCC );
  _EQ010 =  _X002;
  _X002  = EXP(  NEPRES &  NICERES &  NPOWERUP );

% NSTROBE  = |U5|2Q %
NSTROBE  =  _MC019;
 _MC019  = DFFE(  _MC011 $  GND, !GICECLK,  VCC,  VCC,  VCC );

% QSMD     = |U54|1Q %
QSMD     =  _MC002;
 _MC002  = DFFE( !EPT4 $  GND,  _EQ011,  VCC,  VCC,  VCC );
  _EQ011 =  NEPRES &  NICERES;

%  |U5|1Q  % 
_MC011   = DFFE(  _EQ012 $ !EPS3,  GICECLK,  VCC, !_EQ013,  VCC );
  _EQ012 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ013 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

%  |U9|1Q  % 
_MC009   = DFFE(  GND $  GND,  GND, !_EQ014, !_MC023,  VCC );
  _EQ014 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

%  |U21|1Q  % 
_MC005   = DFFE(  _EQ015 $  GND, !ICECLK1, !EPT5,  VCC,  VCC );
  _EQ015 = !_MC010 & !_MC019;

%  |U21|2Q  % 
_MC010   = DFFE(  GND $  GND,  GND, !_EQ016, !_EQ017,  VCC );
  _EQ016 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  _MC016;
  _EQ017 =  _X003;
  _X003  = EXP( !EPT5 & !_MC005 );

%  |U28|1Q  % 
_MC016   = DFFE(  GND $  VCC, !_MC023, !_EQ018,  VCC,  VCC );
  _EQ018 =  _X003;

%  |U29|:9  % 
_MC001   = DFFE(  _MC003 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U29|:10  % 
_MC012   = DFFE(  _MC001 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U29|:11  % 
_MC013   = DFFE(  _MC012 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U29|:12  % 
_MC003   = DFFE(  BUF0 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U43|1Q  % 
_MC007   = DFFE(  _EQ019 $ !BUF0, !EPSGN3,  VCC, !_EQ020,  VCC );
  _EQ019 = !BUF0 &  ECTL3 &  _MC015;
  _EQ020 =  _X004;
  _X004  = EXP(  EPS0 &  EPS1 &  EPS2 &  EPS3 & !EPT5 );

%  |U43|2Q  % 
_MC015   = DFFE(  _MC007 $  GND,  GICECLK,  VCC, !_EQ021,  VCC );
  _EQ021 =  _X004;

%  |U48|1Q  % 
_MC008   = DFFE(  GND $  GND,  _MC019,  VCC, !_EQ022,  VCC );
  _EQ022 = !EPS6 &  EPS7;

%  |U58|1Q  % 
_MC030   = DFFE(  _EQ023 $  GND,  GICECLK,  VCC,  VCC,  VCC );
  _EQ023 =  NEPRES &  NICERES &  NPOWERUP;

%  |U58|2Q  % 
_MC029   = DFFE(  _MC030 $  GND,  GICECLK,  VCC,  VCC,  VCC );


%
    Shareable Expanders that are Duplicated in Multiple LABs:
    (none)
%
