Project Information                   c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt

MAX+plus II Compiler Report File
Version 3.30 9/15/93
Compiled: 05/05/95 15:23:44



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

3VEA7032  EPM7032LC44-1    22       13       0      28      3           87 %

User Pins:                 22       13       0  



Project Information                   c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.


Project Information                   c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

3VEA7032@19                       BUFNICEBRK
3VEA7032@4                        BUF0
3VEA7032@38                       ECTL3
3VEA7032@33                       EMPTY
3VEA7032@8                        EPSGN3
3VEA7032@28                       EPSGN4
3VEA7032@9                        EPSGN8
3VEA7032@13                       EPS0
3VEA7032@14                       EPS1
3VEA7032@16                       EPS2
3VEA7032@17                       EPS3
3VEA7032@21                       EPS6
3VEA7032@20                       EPS7
3VEA7032@1                        EPT4
3VEA7032@11                       EPT5
3VEA7032@29                       ESGN7
3VEA7032@34                       ESGN8
3VEA7032@36                       ESGN9
3VEA7032@37                       ESGN10
3VEA7032@24                       ES0
3VEA7032@25                       ES1
3VEA7032@26                       ES2
3VEA7032@27                       ES3
3VEA7032@7                        ETB2
3VEA7032@43                       GICECLK
3VEA7032@44                       ICECLK1
3VEA7032@2                        NEPRES
3VEA7032@40                       NERD
3VEA7032@41                       NEWR
3VEA7032@18                       NICEBRK
3VEA7032@12                       NICERES
3VEA7032@31                       NONCEDRV
3VEA7032@32                       NPOWERUP
3VEA7032@39                       NSTROBE
3VEA7032@5                        QSMD


Project Information                   c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt

** FILE HIERARCHY **



|7474:U58|
|7474:U57|
|7474:U54|
|7474:U50|
|7474:U48|
|7474:U43|
|7474:U28|
|7474:U21|
|7474:U13|
|7474:U9|
|7474:U5|
|74174:U29|


Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

***** Logic for device '3VEA7032' compiled without errors.




Device: EPM7032LC44-1
Turbo: ON
Security: OFF
                                                 
                                                 
                R                                
                E                 I  G           
                S           N     C  I           
                E           E     E  C           
                R  Q  B     P  E  C  E     N  N  
                V  S  U  V  R  P  L  C  G  E  E  
                E  M  F  C  E  T  K  L  N  W  R  
                D  D  0  C  S  4  1  K  D  R  D  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
      ETB2 |  7                                39 | NSTROBE 
    EPSGN3 |  8                                38 | ECTL3 
    EPSGN8 |  9                                37 | ESGN10 
       GND | 10                                36 | ESGN9 
      EPT5 | 11                                35 | VCC 
   NICERES | 12         EPM7032LC44-1          34 | ESGN8 
      EPS0 | 13                                33 | EMPTY 
      EPS1 | 14                                32 | NPOWERUP 
       VCC | 15                                31 | NONCEDRV 
      EPS2 | 16                                30 | GND 
      EPS3 | 17                                29 | ESGN7 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                N  B  E  E  G  V  E  E  E  E  E  
                I  U  P  P  N  C  S  S  S  S  P  
                C  F  S  S  D  C  0  1  2  3  S  
                E  N  7  6                    G  
                B  I                          N  
                R  C                          4  
                K  E                             
                   B                             
                   R                             
                   K                             


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.


Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    15/16( 93%)  15/16( 93%)   2/16( 12%)  24/36( 66%) 
B:    LC17 - LC32    13/16( 81%)  16/16(100%)   1/16(  6%)  23/36( 63%) 


Total dedicated input pins used:                 4/   4 (100%)
Total I/O pins used:                            31/  32 ( 96%)
Total logic cells used:                         28/  32 ( 87%)
Total shareable expanders used:                  3/  32 (  9%)
Total Turbo logic cells used:                   28/  32 ( 87%)
Total shareable expanders not available (n/a):   0/  32 (  0%)

Total input pins required:                      22
Total output pins required:                     13
Total bidirectional pins required:               0
Total logic cells required:                     28
Total flipflops required:                       22
Total shareable expanders in database:           3

Synthesized logic cells:                         0/  32 (  0%)



Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

** INPUTS **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
   4    (1)  (A)      INPUT         0      0   0    0    0  BUF0
  38   (20)  (B)      INPUT         0      0   0    0    0  ECTL3
   8    (5)  (A)      INPUT         0      0   0    0    0  EPSGN3
  28   (28)  (B)      INPUT         0      0   0    0    0  EPSGN4
  13    (9)  (A)      INPUT         0      0   0    0    0  EPS0
  14   (10)  (A)      INPUT         0      0   0    0    0  EPS1
  16   (11)  (A)      INPUT         0      0   0    0    0  EPS2
  17   (12)  (A)      INPUT         0      0   0    0    0  EPS3
  21   (16)  (A)      INPUT         0      0   0    0    0  EPS6
  20   (15)  (A)      INPUT         0      0   0    0    0  EPS7
   1      -   -       INPUT         0      0   0    0    0  EPT4
  11    (7)  (A)      INPUT         0      0   0    0    0  EPT5
  24   (32)  (B)      INPUT         0      0   0    0    0  ES0
  25   (31)  (B)      INPUT         0      0   0    0    0  ES1
  26   (30)  (B)      INPUT         0      0   0    0    0  ES2
  27   (29)  (B)      INPUT         0      0   0    0    0  ES3
  43      -   -       INPUT         0      0   0    0    0  GICECLK
  44      -   -       INPUT         0      0   0    0    0  ICECLK1
   2      -   -       INPUT         0      0   0    0    0  NEPRES
  18   (13)  (A)      INPUT         0      0   0    0    0  NICEBRK
  12    (8)  (A)      INPUT         0      0   0    0    0  NICERES
  32   (25)  (B)      INPUT         0      0   0    0    0  NPOWERUP


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

** OUTPUTS **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
  19     14    A         FF   t     0      0   0    2    0  BUFNICEBRK (|7474:U57|:9)
  33     24    B         FF   t     0      0   0    1    1  EMPTY (|7474:U48|:10)
   9      6    A     OUTPUT   t     0      0   0    2    1  EPSGN8
  29     27    B     OUTPUT   t     0      0   0    5    0  ESGN7
  34     23    B         FF   t     1      0   0    5    1  ESGN8 (|7474:U9|:10)
  36     22    B     OUTPUT   t     0      0   0    0    2  ESGN9
  37     21    B         FF   t     0      0   0    4    2  ESGN10 (|7474:U13|:9)
   7      4    A     OUTPUT   t     0      0   0    1    2  ETB2
  40     18    B     OUTPUT   t     0      0   0    1    1  NERD
  41     17    B     OUTPUT   t     0      0   0    2    1  NEWR
  31     26    B         FF   t     0      0   0    0    2  NONCEDRV (|7474:U50|:9)
  39     19    B         FF   t     0      0   0    1    1  NSTROBE (|7474:U5|:10)
   5      2    A         FF   t     0      0   0    3    0  QSMD (|7474:U54|:9)


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

** BURIED LOGIC **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
 (20)    15    A       DFFE   t     0      0   0    2    0  BUFQ1_3 (|74174:U29|:12)
 (11)     7    A       DFFE   t     0      0   0    1    1  BUFQ2_3 (|74174:U29|:11)
  (8)     5    A       DFFE   t     0      0   0    1    1  BUFQ3_3 (|74174:U29|:10)
 (25)    31    B       DFFE   t     0      0   0    1    1  BUFQ4_3 (|74174:U29|:9)
 (12)     8    A       DFFE   t     1      1   0    1    2  ENRDNDT_2 (|7474:U28|:9)
 (38)    20    B       DFFE   t     0      0   0    2    1  FLUSH_4 (|7474:U48|:9)
 (17)    12    A       DFFE   t     0      0   0    5    0  ICEACTIVE_2 (|7474:U5|:9)
  (4)     1    A       DFFE   t     1      1   0    6    1  ICEHOLD_4 (|7474:U43|:10)
 (28)    28    B       DFFE   t     0      0   0    2    2  ICEVALID_2 (|7474:U21|:9)
  (6)     3    A       DFFE   t     1      1   0    8    1  NEPHOLDQ_4 (|7474:U43|:9)
 (13)     9    A       DFFE   t     0      0   0    4    1  NESGN8Q_2 (|7474:U9|:9)
 (14)    10    A       DFFE   t     0      0   0    1    1  NRESDLY_3 (|7474:U58|:10)
 (18)    13    A       DFFE   t     0      0   0    4    0  NSYSRES_3 (|7474:U50|:10)
 (26)    30    B       DFFE   t     0      0   0    1    1  N00036 (|7474:U58|:9)
 (16)    11    A       DFFE   t     1      1   0    5    2  PRTNDTVL_2 (|7474:U21|:10)


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

        +----------------------------- LC14 BUFNICEBRK
        | +--------------------------- LC15 BUFQ1_3
        | | +------------------------- LC7 BUFQ2_3
        | | | +----------------------- LC5 BUFQ3_3
        | | | | +--------------------- LC8 ENRDNDT_2
        | | | | | +------------------- LC6 EPSGN8
        | | | | | | +----------------- LC4 ETB2
        | | | | | | | +--------------- LC12 ICEACTIVE_2
        | | | | | | | | +------------- LC1 ICEHOLD_4
        | | | | | | | | | +----------- LC3 NEPHOLDQ_4
        | | | | | | | | | | +--------- LC9 NESGN8Q_2
        | | | | | | | | | | | +------- LC10 NRESDLY_3
        | | | | | | | | | | | | +----- LC13 NSYSRES_3
        | | | | | | | | | | | | | +--- LC11 PRTNDTVL_2
        | | | | | | | | | | | | | | +- LC2 QSMD
        | | | | | | | | | | | | | | | 
LC      | | | | | | | | | | | | | | | | A B | Name
LC7  -> - - - - - - * - - - - - - - - | * - | BUFQ2_3
LC5  -> - - * - - - - - - - - - - - - | * - | BUFQ3_3
LC8  -> - - - - - - - - - - - - - * - | * - | ENRDNDT_2
LC1  -> - - - - - * - - - * - - - - - | * - | ICEHOLD_4
LC3  -> - - - - - - - - * - - - - - - | * - | NEPHOLDQ_4

Pin
4    -> - * - - - * - - - * - - - - - | * - | BUF0
38   -> - - - - - * - - - * - - - - - | * - | ECTL3
8    -> - - - - - - * - - * - - - - - | * - | EPSGN3
13   -> - - - - - - - * * * * - - * - | * * | EPS0
14   -> - - - - - - - * * * * - - * - | * * | EPS1
16   -> - - - - - - - * * * * - - * - | * * | EPS2
17   -> - - - - - - - * * * * - - * - | * * | EPS3
1    -> - - - - - - - - - - - - - - * | * - | EPT4
11   -> - - - - * - - - * * - - - * - | * * | EPT5
43   -> - * * * - - - * * - - * * - - | * * | GICECLK
44   -> * - - - - - - - - - - - - - - | * * | ICECLK1
2    -> - - - - - - - - - - - - * - * | * - | NEPRES
18   -> * - - - - - - - - - - - - - - | * - | NICEBRK
12   -> - - - - - - - - - - - - * - * | * - | NICERES
32   -> - - - - - - - - - - - - * - - | * - | NPOWERUP
LC31 -> - - - * - - * - - - - - - - - | * - | BUFQ4_3
LC23 -> - - - - * - - - - - * - - - - | * * | ESGN8
LC28 -> - - - - * - - - - - - - - * - | * - | ICEVALID_2
LC30 -> - - - - - - - - - - - * - - - | * - | N00036


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

        +------------------------- LC31 BUFQ4_3
        | +----------------------- LC24 EMPTY
        | | +--------------------- LC27 ESGN7
        | | | +------------------- LC23 ESGN8
        | | | | +----------------- LC22 ESGN9
        | | | | | +--------------- LC21 ESGN10
        | | | | | | +------------- LC20 FLUSH_4
        | | | | | | | +----------- LC28 ICEVALID_2
        | | | | | | | | +--------- LC18 NERD
        | | | | | | | | | +------- LC17 NEWR
        | | | | | | | | | | +----- LC26 NONCEDRV
        | | | | | | | | | | | +--- LC19 NSTROBE
        | | | | | | | | | | | | +- LC30 N00036
        | | | | | | | | | | | | | 
LC      | | | | | | | | | | | | | | A B | Name
LC23 -> - - - - - * - - - - - - - | * * | ESGN8
LC20 -> - * - - - - - - - - - - - | - * | FLUSH_4
LC19 -> - - - - * * * * * * - - - | - * | NSTROBE

Pin
28   -> - - * - - - - - - - - - - | - * | EPSGN4
13   -> - - - * - * - - - - - - - | * * | EPS0
14   -> - - - * - * - - - - - - - | * * | EPS1
16   -> - - - * - * - - - - - - - | * * | EPS2
17   -> - - - * - * - - - - - - - | * * | EPS3
21   -> - - - - - - * - - - - - - | - * | EPS6
20   -> - - - - - - * - - - - - - | - * | EPS7
1    -> - - - - - - - - - - - - - | * - | EPT4
11   -> - - - - - - - * - - - - - | * * | EPT5
24   -> - - * - - - - - - * - - - | - * | ES0
25   -> - - * - - - - - * * - - - | - * | ES1
26   -> - - * - - - - - - - - - - | - * | ES2
27   -> - - * - - - - - - - - - - | - * | ES3
43   -> * * - - - - - - - - - * * | * * | GICECLK
44   -> - - - * - - - * - - - - - | * * | ICECLK1
2    -> - - - - - - - - - - - - - | * - | NEPRES
LC15 -> * - - - - - - - - - - - - | - * | BUFQ1_3
LC12 -> - - - - - - - - - - - * - | - * | ICEACTIVE_2
LC9  -> - - - * - - - - - - - - - | - * | NESGN8Q_2
LC10 -> - - - - - - - - - - * - - | - * | NRESDLY_3
LC13 -> - - - - - - - - - - * - * | - * | NSYSRES_3
LC11 -> - - - - * - - * - - - - - | - * | PRTNDTVL_2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:          c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt
3VEA7032

** EQUATIONS **

BUF0     : INPUT;
ECTL3    : INPUT;
EPSGN3   : INPUT;
EPSGN4   : INPUT;
EPS0     : INPUT;
EPS1     : INPUT;
EPS2     : INPUT;
EPS3     : INPUT;
EPS6     : INPUT;
EPS7     : INPUT;
EPT4     : INPUT;
EPT5     : INPUT;
ES0      : INPUT;
ES1      : INPUT;
ES2      : INPUT;
ES3      : INPUT;
GICECLK  : INPUT;
ICECLK1  : INPUT;
NEPRES   : INPUT;
NICEBRK  : INPUT;
NICERES  : INPUT;
NPOWERUP : INPUT;

% BUFNICEBRK = _LC014 %
% BUFNICEBRK = |7474:U57|1Q %
 BUFNICEBRK = DFFE( NICEBRK $  GND,  ICECLK1,  VCC,  VCC,  VCC);

% BUFQ1_3  = _LC015 %
BUFQ1_3  = DFFE( BUF0 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% BUFQ2_3  = _LC007 %
BUFQ2_3  = DFFE( BUFQ3_3 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% BUFQ3_3  = _LC005 %
BUFQ3_3  = DFFE( BUFQ4_3 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% BUFQ4_3  = _LC031 %
BUFQ4_3  = DFFE( BUFQ1_3 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% EMPTY    = _LC024 %
% EMPTY    = |7474:U48|2Q %
 EMPTY   = DFFE( FLUSH_4 $  GND,  GICECLK,  VCC,  VCC,  VCC);

% ENRDNDT_2 = _LC008 %
ENRDNDT_2 = DFFE( GND $  VCC, !ESGN8, !_EQ001,  VCC,  VCC);
  _EQ001 =  _X001;
  _X001  = EXP(!EPT5 & !ICEVALID_2);

 EPSGN8  = LCELL( _EQ002 $  BUF0);
  _EQ002 = !BUF0 &  ECTL3 &  ICEHOLD_4;

 ESGN7   = LCELL( _EQ003 $  VCC);
  _EQ003 =  EPSGN4 & !ES0 &  ES2 &  ES3
         #  EPSGN4 & !ES1 &  ES2 &  ES3;

% ESGN8    = _LC023 %
% ESGN8    = |7474:U9|2Q %
 ESGN8   = DFFE(!NESGN8Q_2 $  GND,  ICECLK1, !_EQ004, !_EQ005,  VCC);
  _EQ004 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ005 = !NESGN8Q_2 &  _X002;
  _X002  = EXP( EPS0 &  EPS1 &  EPS2 &  EPS3);

 ESGN9   = LCELL( _EQ006 $  VCC);
  _EQ006 = !NSTROBE & !PRTNDTVL_2;

% ESGN10   = _LC021 %
% ESGN10   = |7474:U13|1Q %
 ESGN10  = DFFE( GND $  GND, !ESGN8,  VCC, !_EQ007,  VCC);
  _EQ007 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  NSTROBE;

 ETB2    = LCELL( _EQ008 $  GND);
  _EQ008 =  BUFQ2_3 &  BUFQ4_3 &  EPSGN3;

% FLUSH_4  = _LC020 %
FLUSH_4  = DFFE( GND $  GND,  NSTROBE,  VCC, !_EQ009,  VCC);
  _EQ009 = !EPS6 &  EPS7;

% ICEACTIVE_2 = _LC012 %
ICEACTIVE_2 = DFFE( _EQ010 $ !EPS3,  GICECLK,  VCC, !_EQ011,  VCC);
  _EQ010 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ011 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

% ICEHOLD_4 = _LC001 %
ICEHOLD_4 = DFFE( NEPHOLDQ_4 $  GND,  GICECLK,  VCC, !_EQ012,  VCC);
  _EQ012 =  _X003;
  _X003  = EXP( EPS0 &  EPS1 &  EPS2 &  EPS3 & !EPT5);

% ICEVALID_2 = _LC028 %
ICEVALID_2 = DFFE( _EQ013 $  GND, !ICECLK1, !EPT5,  VCC,  VCC);
  _EQ013 = !NSTROBE & !PRTNDTVL_2;

% NEPHOLDQ_4 = _LC003 %
NEPHOLDQ_4 = DFFE( _EQ014 $ !BUF0, !EPSGN3,  VCC, !_EQ015,  VCC);
  _EQ014 = !BUF0 &  ECTL3 &  ICEHOLD_4;
  _EQ015 =  _X003;

 NERD    = LCELL( _EQ016 $  VCC);
  _EQ016 = !ES1 & !NSTROBE;

% NESGN8Q_2 = _LC009 %
NESGN8Q_2 = DFFE( GND $  GND,  GND, !_EQ017, !ESGN8,  VCC);
  _EQ017 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

 NEWR    = LCELL( _EQ018 $  VCC);
  _EQ018 = !ES0 &  ES1 & !NSTROBE;

% NONCEDRV = _LC026 %
% NONCEDRV = |7474:U50|1Q %
 NONCEDRV = DFFE( GND $  VCC,  NRESDLY_3,  NSYSRES_3,  VCC,  VCC);

% NRESDLY_3 = _LC010 %
NRESDLY_3 = DFFE( N00036 $  GND,  GICECLK,  VCC,  VCC,  VCC);

% NSTROBE  = _LC019 %
% NSTROBE  = |7474:U5|2Q %
 NSTROBE = DFFE( ICEACTIVE_2 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% NSYSRES_3 = _LC013 %
NSYSRES_3 = DFFE( _EQ019 $  GND,  GICECLK,  VCC,  VCC,  VCC);
  _EQ019 =  NEPRES &  NICERES &  NPOWERUP;

% N00036   = _LC030 %
N00036   = DFFE( NSYSRES_3 $  GND,  GICECLK,  VCC,  VCC,  VCC);

% PRTNDTVL_2 = _LC011 %
PRTNDTVL_2 = DFFE( GND $  GND,  GND, !_EQ020, !_EQ021,  VCC);
  _EQ020 =  ENRDNDT_2 &  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ021 =  _X001;

% QSMD     = _LC002 %
% QSMD     = |7474:U54|1Q %
 QSMD    = DFFE(!EPT4 $  GND,  _EQ022,  VCC,  VCC,  VCC);
  _EQ022 =  NEPRES &  NICERES;


%
    Shareable expanders that are duplicated in multiple LABs:
    (none)
%


Project Information                   c:\orcad4.04\orcad\ea7032v2\3vea7032.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                          = off

Logic Synthesis:

   Default Synthesis Style             = Normal

      Logic option settings in 'Normal' style for 'MAX7000' family

      minimization                     = full
      parallel_expanders               = off
      soft_buffer_insertion            = on
      turbo_bit                        = on
      xor_synthesis                    = on

   Other logic synthesis settings:

      Automatic Global Clock           = off
      Automatic Global Clear           = off
      Automatic Global Preset          = off
      Automatic Global Output Enable   = off
      Automatic Peripheral Registers   = off

Functional SNF Extractor               = off

Linked SNF Extractor                   = off
Timing SNF Extractor                   = on
Optimize Timing SNF                    = off
Ignore Previous Fit                    = on
Automatic LCELL Insertion              = off
Generate JEDEC Files                   = off
Total Recompile                        = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                    = off
Verilog Netlist Writer                 = off
VHDL Netlist Writer                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor          00:00:30
   Database Builder                    00:00:10
   Logic Synthesizer                   00:00:05
   Partitioner                         00:00:01
   Fitter                              00:00:10
   Timing SNF Extractor                00:00:03
   Assembler                           00:00:02
   --------------------------          --------
   Total Time                          00:01:01

