Project Information                               d:\orcad\fyeb7032\eb7032.rpt

MAX+plus II Compiler Report File
Version 2.20 08/17/92



***** Project compiled without errors




** DEVICE SUMMARY **

Chip/                   Input   Output   Bidir         Shareable
POF       Device        Pins    Pins     Pins     MCs    EXPs     % Utilized

EB7032    EPM7032LC44-1  22       13       0      25      4           78 %



Project Information                               d:\orcad\fyeb7032\eb7032.rpt

** PIN/MC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

EB7032@39                         BUFNICEBRK
EB7032@4                          BUF0
EB7032@7                          ECTL3
EB7032@32                         EMPTY
EB7032@6                          EPSGN3
EB7032@28                         EPSGN4
EB7032@8                          EPSGN8
EB7032@11                         EPS0
EB7032@12                         EPS1
EB7032@13                         EPS2
EB7032@14                         EPS3
EB7032@38                         EPS6
EB7032@37                         EPS7
EB7032@9                          EPT5
EB7032@29                         ESGN7
EB7032@33                         ESGN8
EB7032@34                         ESGN9
EB7032@36                         ESGN10
EB7032@24                         ES0
EB7032@25                         ES1
EB7032@26                         ES2
EB7032@27                         ES3
EB7032@5                          ETB2
EB7032@43                         GICECLK
EB7032@44                         ICECLK1
EB7032@16                         NEPRES
EB7032@40                         NERD
EB7032@41                         NEWR
EB7032@2                          NICEBRK
EB7032@17                         NICERES
EB7032@20                         NONCEDRV
EB7032@21                         NPOWERUP
EB7032@19                         NRESDLY
EB7032@31                         NSTROBE
EB7032@18                         NSYSRES


Project Information                               d:\orcad\fyeb7032\eb7032.rpt

** FILE HIERARCHY **



|74174:36|
|7474:45|
|7474:44|
|7474:43|
|7474:42|
|7474:41|
|7474:40|
|7474:39|
|7474:38|
|7474:37|


EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

***** Logic for device 'EB7032' compiled without errors

             


Device: EPM7032LC44-1
Turbo: ON
Security: ON
                                                 
                                                 
                                                 
                            N     I  G           
                E           I     C  I           
                P           C     E  C           
                S  E  B     E     C  E     N  N  
                G  T  U  V  B  G  L  C  G  E  E  
                N  B  F  C  R  N  K  L  N  W  R  
                3  2  0  C  K  D  1  K  D  R  D  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
     ECTL3 |  7                                39 | BUFNICEBRK 
    EPSGN8 |  8                                38 | EPS6 
      EPT5 |  9                                37 | EPS7 
       GND | 10                                36 | ESGN10 
      EPS0 | 11                                35 | VCC 
      EPS1 | 12         EPM7032LC44-1          34 | ESGN9 
      EPS2 | 13                                33 | ESGN8 
      EPS3 | 14                                32 | EMPTY 
       VCC | 15                                31 | NSTROBE 
    NEPRES | 16                                30 | GND 
   NICERES | 17                                29 | ESGN7 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                N  N  N  N  G  V  E  E  E  E  E  
                S  R  O  P  N  C  S  S  S  S  P  
                Y  E  N  O  D  C  0  1  2  3  S  
                S  S  C  W                    G  
                R  D  E  E                    N  
                E  L  D  R                    4  
                S  Y  R  U                       
                      V  P                       
                                                 
                                                 


EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

** RESOURCE USAGE **                                                  

                                                Shareable     External
Logic Array Block     Macrocells    I/O Pins    Expanders   Interconnect

A:     MC1 - MC16    16/16(100%)  16/16(100%)   3/16( 18%)  27/36( 75%) 
B:    MC17 - MC32     9/16( 56%)  16/16(100%)   1/16(  6%)  18/36( 50%) 


Total dedicated input pins used:                 3/  4 ( 75%)
Total I/O pins used:                            32/ 32 (100%)
Total macrocells used:                          25/ 32 ( 78%)
Total shareable expanders used:                  4/ 32 ( 12%)
Total turbo macrocells used:                    25/ 32 ( 78%)
Total shareable expanders not available (n/a):   0/ 32 (  0%)

Total input pins required:                      22
Total output pins required:                     13
Total bidirectional pins required:               0
Total macrocells required:                      25
Total shareable expanders in database:           4

Synthesized macrocells:                          0/ 32 (  0%)



EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

** INPUTS **                                                          

                                     Shareable
                                     Expanders     Fan-In
 Pin  MCell  LAB  Primitive      Total Shared n/a  INP  FBK  Name
   4    (1)  (A)      INPUT         0      0   0   0    0  BUF0
   7    (4)  (A)      INPUT         0      0   0   0    0  ECTL3
   6    (3)  (A)      INPUT         0      0   0   0    0  EPSGN3
  28   (28)  (B)      INPUT         0      0   0   0    0  EPSGN4
  11    (7)  (A)      INPUT         0      0   0   0    0  EPS0
  12    (8)  (A)      INPUT         0      0   0   0    0  EPS1
  13    (9)  (A)      INPUT         0      0   0   0    0  EPS2
  14   (10)  (A)      INPUT         0      0   0   0    0  EPS3
  38   (20)  (B)      INPUT         0      0   0   0    0  EPS6
  37   (21)  (B)      INPUT         0      0   0   0    0  EPS7
   9    (6)  (A)      INPUT         0      0   0   0    0  EPT5
  24   (32)  (B)      INPUT         0      0   0   0    0  ES0
  25   (31)  (B)      INPUT         0      0   0   0    0  ES1
  26   (30)  (B)      INPUT         0      0   0   0    0  ES2
  27   (29)  (B)      INPUT         0      0   0   0    0  ES3
  43      -   -       INPUT         0      0   0   0    0  GICECLK
  44      -   -       INPUT         0      0   0   0    0  ICECLK1
  16   (11)  (A)      INPUT         0      0   0   0    0  NEPRES
   2      -   -       INPUT         0      0   0   0    0  NICEBRK
  17   (12)  (A)      INPUT         0      0   0   0    0  NICERES
  21   (16)  (A)      INPUT         0      0   0   0    0  NPOWERUP
  19   (14)  (A)      INPUT         0      0   0   0    0  NRESDLY


EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

** OUTPUTS **                                                         

                                     Shareable
                                     Expanders     Fan-In
 Pin  MCell  LAB  Primitive      Total Shared n/a  INP  FBK  Name
  39     19    B       DFFE   t     0      0   0   2    0  BUFNICEBRK
  32     25    B       DFFE   t     0      0   0   1    1  EMPTY
   8      5    A     OUTPUT   t     0      0   0   2    1  EPSGN8
  29     27    B     OUTPUT   t     0      0   0   5    0  ESGN7
  33     24    B       DFFE   t     1      0   0   5    1  ESGN8
  34     23    B     OUTPUT   t     0      0   0   0    2  ESGN9
  36     22    B       DFFE   t     0      0   0   4    2  ESGN10
   5      2    A     OUTPUT   t     0      0   0   1    2  ETB2
  40     18    B     OUTPUT   t     0      0   0   1    1  NERD
  41     17    B     OUTPUT   t     0      0   0   2    1  NEWR
  20     15    A       DFFE   t     1      0   0   4    0  NONCEDRV
  31     26    B       DFFE   t     0      0   0   1    1  NSTROBE
  18     13    A     OUTPUT   t     0      0   0   3    0  NSYSRES


EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

** BURIED LOGIC **                                                    

                                     Shareable
                                     Expanders     Fan-In
 Pin  MCell  LAB  Primitive      Total Shared n/a  INP  FBK  Name
 (12)     8    A       DFFE   t     0      0   0   5    0  |U5|1Q
 (16)    11    A       DFFE   t     0      0   0   4    1  |U9|1Q
 (21)    16    A       DFFE   t     0      0   0   2    2  |U21|1Q
  (6)     3    A       DFFE   t     1      1   0   5    2  |U21|2Q
  (4)     1    A       DFFE   t     1      1   0   1    2  |U28|1Q
  (9)     6    A       DFFE   t     0      0   0   1    1  |U29|:9
 (11)     7    A       DFFE   t     0      0   0   1    1  |U29|:10
  (7)     4    A       DFFE   t     0      0   0   1    1  |U29|:11
 (19)    14    A       DFFE   t     0      0   0   2    0  |U29|:12
 (17)    12    A       DFFE   t     1      1   0   8    1  |U43|1Q
 (14)    10    A       DFFE   t     1      1   0   6    1  |U43|2Q
 (13)     9    A       DFFE   t     0      0   0   2    1  |U48|1Q


EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

** MACROCELL INTERCONNECTIONS **                                      

Logic Array Block 'A':

        M M M M M M M M M M M M M M M M 
        C C C C C C C C C C C C C C C C 
        5 2 1 1 8 1 1 3 1 6 7 4 1 1 1 9 
        | | 5 3 | 1 6 | | | | | 4 2 0 | 
MCELL   | | | | | | | | | | | | | | | | | A B | Name
MC16 -> - - - - - - - * * - - - - - - - | * - | |U21|1Q
MC3  -> - - - - - - * - - - - - - - - - | * * | |U21|2Q
MC1  -> - - - - - - - * - - - - - - - - | * - | |U28|1Q
MC6  -> - * - - - - - - - - * - - - - - | * - | |U29|:9
MC7  -> - - - - - - - - - - - * - - - - | * - | |U29|:10
MC4  -> - * - - - - - - - - - - - - - - | * - | |U29|:11
MC14 -> - - - - - - - - - * - - - - - - | * - | |U29|:12
MC12 -> - - - - - - - - - - - - - - * - | * - | |U43|1Q
MC10 -> * - - - - - - - - - - - - * - - | * - | |U43|2Q

Pin
4    -> * - - - - - - - - - - - * * - - | * - | BUF0
7    -> * - - - - - - - - - - - - * - - | * - | ECTL3
6    -> - * - - - - - - - - - - - * - - | * - | EPSGN3
11   -> - - - - * * - * - - - - - * * - | * * | EPS0
12   -> - - - - * * - * - - - - - * * - | * * | EPS1
13   -> - - - - * * - * - - - - - * * - | * * | EPS2
14   -> - - - - * * - * - - - - - * * - | * * | EPS3
38   -> - - - - - - - - - - - - - - - * | * - | EPS6
37   -> - - - - - - - - - - - - - - - * | * - | EPS7
9    -> - - - - - - * * * - - - - * * - | * - | EPT5
43   -> - - - - * - - - - * * * * - * - | * * | GICECLK
44   -> - - - - - - * - - - - - - - - - | * * | ICECLK1
16   -> - - * * - - - - - - - - - - - - | * - | NEPRES
2    -> - - - - - - - - - - - - - - - - | - * | NICEBRK
17   -> - - * * - - - - - - - - - - - - | * - | NICERES
21   -> - - * * - - - - - - - - - - - - | * - | NPOWERUP
19   -> - - * - - - - - - - - - - - - - | * - | NRESDLY
MC24 -> - - - - - * - - * - - - - - - - | * * | ESGN8
MC26 -> - - - - - - * - - - - - - - - * | * * | NSTROBE


EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

** MACROCELL INTERCONNECTIONS **                                      

Logic Array Block 'B':

        M M M M M M M M M 
        C C C C C C C C C 
        1 2 2 2 2 2 1 1 2 
        9 5 7 4 3 2 8 7 6 
MCELL   | | | | | | | | | | A B | Name
MC24 -> - - - - - * - - - | * * | ESGN8
MC26 -> - - - - * * * * - | * * | NSTROBE

Pin
28   -> - - * - - - - - - | - * | EPSGN4
11   -> - - - * - * - - - | * * | EPS0
12   -> - - - * - * - - - | * * | EPS1
13   -> - - - * - * - - - | * * | EPS2
14   -> - - - * - * - - - | * * | EPS3
24   -> - - * - - - - * - | - * | ES0
25   -> - - * - - - * * - | - * | ES1
26   -> - - * - - - - - - | - * | ES2
27   -> - - * - - - - - - | - * | ES3
43   -> - * - - - - - - * | * * | GICECLK
44   -> * - - * - - - - - | * * | ICECLK1
2    -> * - - - - - - - - | - * | NICEBRK
MC8  -> - - - - - - - - * | - * | |U5|1Q
MC11 -> - - - * - - - - - | - * | |U9|1Q
MC3  -> - - - - * - - - - | * * | |U21|2Q
MC9  -> - * - - - - - - - | - * | |U48|1Q


EB7032                                            d:\orcad\fyeb7032\eb7032.rpt

** EQUATIONS **                                                       

BUF0     : INPUT;
ECTL3    : INPUT;
EPSGN3   : INPUT;
EPSGN4   : INPUT;
EPS0     : INPUT;
EPS1     : INPUT;
EPS2     : INPUT;
EPS3     : INPUT;
EPS6     : INPUT;
EPS7     : INPUT;
EPT5     : INPUT;
ES0      : INPUT;
ES1      : INPUT;
ES2      : INPUT;
ES3      : INPUT;
GICECLK  : INPUT;
ICECLK1  : INPUT;
NEPRES   : INPUT;
NICEBRK  : INPUT;
NICERES  : INPUT;
NPOWERUP : INPUT;
NRESDLY  : INPUT;

% BUFNICEBRK = |U53|1Q %
BUFNICEBRK =  _MC019;
 _MC019  = DFFE(  NICEBRK $  GND,  ICECLK1,  VCC,  VCC,  VCC );

% EMPTY    = |U48|2Q %
EMPTY    =  _MC025;
 _MC025  = DFFE(  _MC009 $  GND,  GICECLK,  VCC,  VCC,  VCC );

EPSGN8   =  _MC005;
 _MC005  = MCELL(  _EQ001 $  BUF0 );
  _EQ001 = !BUF0 &  ECTL3 &  _MC010;

ESGN7    =  _MC027;
 _MC027  = MCELL(  _EQ002 $  VCC );
  _EQ002 =  EPSGN4 & !ES0 &  ES2 &  ES3
         #  EPSGN4 & !ES1 &  ES2 &  ES3;

% ESGN8    = |U9|2Q %
ESGN8    =  _MC024;
 _MC024  = DFFE( !_MC011 $  GND,  ICECLK1, !_EQ003, !_EQ004,  VCC );
  _EQ003 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ004 = !_MC011 &  _X001;
  _X001  = EXP(  EPS0 &  EPS1 &  EPS2 &  EPS3 );

ESGN9    =  _MC023;
 _MC023  = MCELL(  _EQ005 $  VCC );
  _EQ005 = !_MC003 & !_MC026;

% ESGN10   = |U13|1Q %
ESGN10   =  _MC022;
 _MC022  = DFFE(  GND $  GND, !_MC024,  VCC, !_EQ006,  VCC );
  _EQ006 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  _MC026;

ETB2     =  _MC002;
 _MC002  = MCELL(  _EQ007 $  GND );
  _EQ007 =  EPSGN3 &  _MC004 &  _MC006;

NERD     =  _MC018;
 _MC018  = MCELL(  _EQ008 $  VCC );
  _EQ008 = !ES1 & !_MC026;

NEWR     =  _MC017;
 _MC017  = MCELL(  _EQ009 $  VCC );
  _EQ009 = !ES0 &  ES1 & !_MC026;

% NONCEDRV = |U50|1Q %
NONCEDRV =  _MC015;
 _MC015  = DFFE(  GND $  VCC,  NRESDLY, !_EQ010,  VCC,  VCC );
  _EQ010 =  _X002;
  _X002  = EXP(  NEPRES &  NICERES &  NPOWERUP );

% NSTROBE  = |U5|2Q %
NSTROBE  =  _MC026;
 _MC026  = DFFE(  _MC008 $  GND, !GICECLK,  VCC,  VCC,  VCC );

NSYSRES  =  _MC013;
 _MC013  = MCELL(  _EQ011 $  GND );
  _EQ011 =  NEPRES &  NICERES &  NPOWERUP;

%  |U5|1Q  % 
_MC008   = DFFE(  _EQ012 $ !EPS3,  GICECLK,  VCC, !_EQ013,  VCC );
  _EQ012 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ013 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

%  |U9|1Q  % 
_MC011   = DFFE(  GND $  GND,  GND, !_EQ014, !_MC024,  VCC );
  _EQ014 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

%  |U21|1Q  % 
_MC016   = DFFE(  _EQ015 $  GND, !ICECLK1, !EPT5,  VCC,  VCC );
  _EQ015 = !_MC003 & !_MC026;

%  |U21|2Q  % 
_MC003   = DFFE(  GND $  GND,  GND, !_EQ016, !_EQ017,  VCC );
  _EQ016 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  _MC001;
  _EQ017 =  _X003;
  _X003  = EXP( !EPT5 & !_MC016 );

%  |U28|1Q  % 
_MC001   = DFFE(  GND $  VCC, !_MC024, !_EQ018,  VCC,  VCC );
  _EQ018 =  _X003;

%  |U29|:9  % 
_MC006   = DFFE(  _MC014 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U29|:10  % 
_MC007   = DFFE(  _MC006 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U29|:11  % 
_MC004   = DFFE(  _MC007 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U29|:12  % 
_MC014   = DFFE(  BUF0 $  GND, !GICECLK,  VCC,  VCC,  VCC );

%  |U43|1Q  % 
_MC012   = DFFE(  _EQ019 $ !BUF0, !EPSGN3,  VCC, !_EQ020,  VCC );
  _EQ019 = !BUF0 &  ECTL3 &  _MC010;
  _EQ020 =  _X004;
  _X004  = EXP(  EPS0 &  EPS1 &  EPS2 &  EPS3 & !EPT5 );

%  |U43|2Q  % 
_MC010   = DFFE(  _MC012 $  GND,  GICECLK,  VCC, !_EQ021,  VCC );
  _EQ021 =  _X004;

%  |U48|1Q  % 
_MC009   = DFFE(  GND $  GND,  _MC026,  VCC, !_EQ022,  VCC );
  _EQ022 = !EPS6 &  EPS7;


%
    Shareable Expanders that are Duplicated in Multiple LABs:
    (none)
%
