Project Information                     c:\orcad4.04\orcad\ec7032v3\ec7032.rpt

MAX+plus II Compiler Report File
Version 3.30 9/15/93
Compiled: 05/09/95 13:38:04



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

EC7032    EPM7032LC44-1    22       13       0      25      3           78 %

User Pins:                 22       13       0  



Project Information                     c:\orcad4.04\orcad\ec7032v3\ec7032.rpt

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

EC7032@39                         BUFNICEBRK
EC7032@4                          BUF0
EC7032@7                          ECTL3
EC7032@32                         EMPTY
EC7032@6                          EPSGN3
EC7032@28                         EPSGN4
EC7032@8                          EPSGN8
EC7032@11                         EPS0
EC7032@12                         EPS1
EC7032@13                         EPS2
EC7032@14                         EPS3
EC7032@38                         EPS6
EC7032@37                         EPS7
EC7032@9                          EPT5
EC7032@29                         ESGN7
EC7032@33                         ESGN8
EC7032@34                         ESGN9
EC7032@36                         ESGN10
EC7032@24                         ES0
EC7032@25                         ES1
EC7032@26                         ES2
EC7032@27                         ES3
EC7032@5                          ETB2
EC7032@43                         GICECLK
EC7032@44                         ICECLK1
EC7032@16                         NEPRES
EC7032@40                         NERD
EC7032@41                         NEWR
EC7032@2                          NICEBRK
EC7032@17                         NICERES
EC7032@20                         NONCEDRV
EC7032@21                         NPOWERUP
EC7032@19                         NRESDLY
EC7032@31                         NSTROBE
EC7032@18                         NSYSRES


Project Information                     c:\orcad4.04\orcad\ec7032v3\ec7032.rpt

** FILE HIERARCHY **



|7474:U53|
|7474:U50|
|7474:U48|
|7474:U43|
|7474:U28|
|7474:U21|
|7474:U13|
|7474:U9|
|7474:U5|
|74174:U29|


Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

***** Logic for device 'EC7032' compiled without errors.




Device: EPM7032LC44-1
Turbo: ON
Security: OFF
                                                 
                                                 
                                                 
                            N     I  G           
                E           I     C  I           
                P           C     E  C           
                S  E  B     E     C  E     N  N  
                G  T  U  V  B  G  L  C  G  E  E  
                N  B  F  C  R  N  K  L  N  W  R  
                3  2  0  C  K  D  1  K  D  R  D  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
     ECTL3 |  7                                39 | BUFNICEBRK 
    EPSGN8 |  8                                38 | EPS6 
      EPT5 |  9                                37 | EPS7 
       GND | 10                                36 | ESGN10 
      EPS0 | 11                                35 | VCC 
      EPS1 | 12         EPM7032LC44-1          34 | ESGN9 
      EPS2 | 13                                33 | ESGN8 
      EPS3 | 14                                32 | EMPTY 
       VCC | 15                                31 | NSTROBE 
    NEPRES | 16                                30 | GND 
   NICERES | 17                                29 | ESGN7 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                N  N  N  N  G  V  E  E  E  E  E  
                S  R  O  P  N  C  S  S  S  S  P  
                Y  E  N  O  D  C  0  1  2  3  S  
                S  S  C  W                    G  
                R  D  E  E                    N  
                E  L  D  R                    4  
                S  Y  R  U                       
                      V  P                       
                                                 
                                                 


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.


Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    16/16(100%)  16/16(100%)   2/16( 12%)  28/36( 77%) 
B:    LC17 - LC32     9/16( 56%)  16/16(100%)   1/16(  6%)  18/36( 50%) 


Total dedicated input pins used:                 3/   4 ( 75%)
Total I/O pins used:                            32/  32 (100%)
Total logic cells used:                         25/  32 ( 78%)
Total shareable expanders used:                  3/  32 (  9%)
Total Turbo logic cells used:                   25/  32 ( 78%)
Total shareable expanders not available (n/a):   0/  32 (  0%)

Total input pins required:                      22
Total output pins required:                     13
Total bidirectional pins required:               0
Total logic cells required:                     25
Total flipflops required:                       19
Total shareable expanders in database:           3

Synthesized logic cells:                         0/  32 (  0%)



Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

** INPUTS **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
   4    (1)  (A)      INPUT         0      0   0    0    0  BUF0
   7    (4)  (A)      INPUT         0      0   0    0    0  ECTL3
   6    (3)  (A)      INPUT         0      0   0    0    0  EPSGN3
  28   (28)  (B)      INPUT         0      0   0    0    0  EPSGN4
  11    (7)  (A)      INPUT         0      0   0    0    0  EPS0
  12    (8)  (A)      INPUT         0      0   0    0    0  EPS1
  13    (9)  (A)      INPUT         0      0   0    0    0  EPS2
  14   (10)  (A)      INPUT         0      0   0    0    0  EPS3
  38   (20)  (B)      INPUT         0      0   0    0    0  EPS6
  37   (21)  (B)      INPUT         0      0   0    0    0  EPS7
   9    (6)  (A)      INPUT         0      0   0    0    0  EPT5
  24   (32)  (B)      INPUT         0      0   0    0    0  ES0
  25   (31)  (B)      INPUT         0      0   0    0    0  ES1
  26   (30)  (B)      INPUT         0      0   0    0    0  ES2
  27   (29)  (B)      INPUT         0      0   0    0    0  ES3
  43      -   -       INPUT         0      0   0    0    0  GICECLK
  44      -   -       INPUT         0      0   0    0    0  ICECLK1
  16   (11)  (A)      INPUT         0      0   0    0    0  NEPRES
   2      -   -       INPUT         0      0   0    0    0  NICEBRK
  17   (12)  (A)      INPUT         0      0   0    0    0  NICERES
  21   (16)  (A)      INPUT         0      0   0    0    0  NPOWERUP
  19   (14)  (A)      INPUT         0      0   0    0    0  NRESDLY


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

** OUTPUTS **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
  39     19    B         FF   t     0      0   0    2    0  BUFNICEBRK (|7474:U53|:9)
  32     25    B         FF   t     0      0   0    1    1  EMPTY (|7474:U48|:10)
   8      5    A     OUTPUT   t     0      0   0    2    1  EPSGN8
  29     27    B     OUTPUT   t     0      0   0    5    0  ESGN7
  33     24    B         FF   t     1      0   0    5    1  ESGN8 (|7474:U9|:10)
  34     23    B     OUTPUT   t     0      0   0    0    2  ESGN9
  36     22    B         FF   t     0      0   0    4    2  ESGN10 (|7474:U13|:9)
   5      2    A     OUTPUT   t     0      0   0    1    2  ETB2
  40     18    B     OUTPUT   t     0      0   0    1    1  NERD
  41     17    B     OUTPUT   t     0      0   0    2    1  NEWR
  20     15    A         FF   t     0      0   0    1    1  NONCEDRV (|7474:U50|:9)
  31     26    B         FF   t     0      0   0    1    1  NSTROBE (|7474:U5|:10)
  18     13    A         FF   t     0      0   0    4    0  NSYSRES (|7474:U50|:10)


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

** BURIED LOGIC **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
 (17)    12    A       DFFE   t     0      0   0    2    0  BUFQ1_3 (|74174:U29|:12)
 (21)    16    A       DFFE   t     0      0   0    1    1  BUFQ2_3 (|74174:U29|:11)
 (19)    14    A       DFFE   t     0      0   0    1    1  BUFQ3_3 (|74174:U29|:10)
 (14)    10    A       DFFE   t     0      0   0    1    1  BUFQ4_3 (|74174:U29|:9)
  (9)     6    A       DFFE   t     1      1   0    1    2  ENRDNDT_2 (|7474:U28|:9)
 (13)     9    A       DFFE   t     0      0   0    2    1  FLUSH_4 (|7474:U48|:9)
  (6)     3    A       DFFE   t     0      0   0    5    0  ICEACTIVE_2 (|7474:U5|:9)
  (7)     4    A       DFFE   t     1      1   0    6    1  ICEHOLD_4 (|7474:U43|:10)
 (11)     7    A       DFFE   t     0      0   0    2    2  ICEVALID_2 (|7474:U21|:9)
  (4)     1    A       DFFE   t     1      1   0    8    1  NEPHOLDQ_4 (|7474:U43|:9)
 (16)    11    A       DFFE   t     0      0   0    4    1  NESGN8Q_2 (|7474:U9|:9)
 (12)     8    A       DFFE   t     1      1   0    5    2  PRTNDTVL_2 (|7474:U21|:10)


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

        +------------------------------- LC12 BUFQ1_3
        | +----------------------------- LC16 BUFQ2_3
        | | +--------------------------- LC14 BUFQ3_3
        | | | +------------------------- LC10 BUFQ4_3
        | | | | +----------------------- LC6 ENRDNDT_2
        | | | | | +--------------------- LC5 EPSGN8
        | | | | | | +------------------- LC2 ETB2
        | | | | | | | +----------------- LC9 FLUSH_4
        | | | | | | | | +--------------- LC3 ICEACTIVE_2
        | | | | | | | | | +------------- LC4 ICEHOLD_4
        | | | | | | | | | | +----------- LC7 ICEVALID_2
        | | | | | | | | | | | +--------- LC1 NEPHOLDQ_4
        | | | | | | | | | | | | +------- LC11 NESGN8Q_2
        | | | | | | | | | | | | | +----- LC15 NONCEDRV
        | | | | | | | | | | | | | | +--- LC13 NSYSRES
        | | | | | | | | | | | | | | | +- LC8 PRTNDTVL_2
        | | | | | | | | | | | | | | | | 
LC      | | | | | | | | | | | | | | | | | A B | Name
LC12 -> - - - * - - - - - - - - - - - - | * - | BUFQ1_3
LC16 -> - - - - - - * - - - - - - - - - | * - | BUFQ2_3
LC14 -> - * - - - - - - - - - - - - - - | * - | BUFQ3_3
LC10 -> - - * - - - * - - - - - - - - - | * - | BUFQ4_3
LC6  -> - - - - - - - - - - - - - - - * | * - | ENRDNDT_2
LC4  -> - - - - - * - - - - - * - - - - | * - | ICEHOLD_4
LC7  -> - - - - * - - - - - - - - - - * | * - | ICEVALID_2
LC1  -> - - - - - - - - - * - - - - - - | * - | NEPHOLDQ_4
LC13 -> - - - - - - - - - - - - - * - - | * - | NSYSRES
LC8  -> - - - - - - - - - - * - - - - - | * * | PRTNDTVL_2

Pin
4    -> * - - - - * - - - - - * - - - - | * - | BUF0
7    -> - - - - - * - - - - - * - - - - | * - | ECTL3
6    -> - - - - - - * - - - - * - - - - | * - | EPSGN3
11   -> - - - - - - - - * * - * * - - * | * * | EPS0
12   -> - - - - - - - - * * - * * - - * | * * | EPS1
13   -> - - - - - - - - * * - * * - - * | * * | EPS2
14   -> - - - - - - - - * * - * * - - * | * * | EPS3
38   -> - - - - - - - * - - - - - - - - | * - | EPS6
37   -> - - - - - - - * - - - - - - - - | * - | EPS7
9    -> - - - - * - - - - * * * - - - * | * - | EPT5
43   -> * * * * - - - - * * - - - - * - | * * | GICECLK
44   -> - - - - - - - - - - * - - - - - | * * | ICECLK1
16   -> - - - - - - - - - - - - - - * - | * - | NEPRES
2    -> - - - - - - - - - - - - - - - - | - * | NICEBRK
17   -> - - - - - - - - - - - - - - * - | * - | NICERES
21   -> - - - - - - - - - - - - - - * - | * - | NPOWERUP
19   -> - - - - - - - - - - - - - * - - | * - | NRESDLY
LC24 -> - - - - * - - - - - - - * - - - | * * | ESGN8
LC26 -> - - - - - - - * - - * - - - - - | * * | NSTROBE


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

        +----------------- LC19 BUFNICEBRK
        | +--------------- LC25 EMPTY
        | | +------------- LC27 ESGN7
        | | | +----------- LC24 ESGN8
        | | | | +--------- LC23 ESGN9
        | | | | | +------- LC22 ESGN10
        | | | | | | +----- LC18 NERD
        | | | | | | | +--- LC17 NEWR
        | | | | | | | | +- LC26 NSTROBE
        | | | | | | | | | 
LC      | | | | | | | | | | A B | Name
LC24 -> - - - - - * - - - | * * | ESGN8
LC26 -> - - - - * * * * - | * * | NSTROBE

Pin
28   -> - - * - - - - - - | - * | EPSGN4
11   -> - - - * - * - - - | * * | EPS0
12   -> - - - * - * - - - | * * | EPS1
13   -> - - - * - * - - - | * * | EPS2
14   -> - - - * - * - - - | * * | EPS3
24   -> - - * - - - - * - | - * | ES0
25   -> - - * - - - * * - | - * | ES1
26   -> - - * - - - - - - | - * | ES2
27   -> - - * - - - - - - | - * | ES3
43   -> - * - - - - - - * | * * | GICECLK
44   -> * - - * - - - - - | * * | ICECLK1
2    -> * - - - - - - - - | - * | NICEBRK
LC9  -> - * - - - - - - - | - * | FLUSH_4
LC3  -> - - - - - - - - * | - * | ICEACTIVE_2
LC11 -> - - - * - - - - - | - * | NESGN8Q_2
LC8  -> - - - - * - - - - | * * | PRTNDTVL_2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:            c:\orcad4.04\orcad\ec7032v3\ec7032.rpt
EC7032

** EQUATIONS **

BUF0     : INPUT;
ECTL3    : INPUT;
EPSGN3   : INPUT;
EPSGN4   : INPUT;
EPS0     : INPUT;
EPS1     : INPUT;
EPS2     : INPUT;
EPS3     : INPUT;
EPS6     : INPUT;
EPS7     : INPUT;
EPT5     : INPUT;
ES0      : INPUT;
ES1      : INPUT;
ES2      : INPUT;
ES3      : INPUT;
GICECLK  : INPUT;
ICECLK1  : INPUT;
NEPRES   : INPUT;
NICEBRK  : INPUT;
NICERES  : INPUT;
NPOWERUP : INPUT;
NRESDLY  : INPUT;

% BUFNICEBRK = _LC019 %
% BUFNICEBRK = |7474:U53|1Q %
 BUFNICEBRK = DFFE( NICEBRK $  GND,  ICECLK1,  VCC,  VCC,  VCC);

% BUFQ1_3  = _LC012 %
BUFQ1_3  = DFFE( BUF0 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% BUFQ2_3  = _LC016 %
BUFQ2_3  = DFFE( BUFQ3_3 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% BUFQ3_3  = _LC014 %
BUFQ3_3  = DFFE( BUFQ4_3 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% BUFQ4_3  = _LC010 %
BUFQ4_3  = DFFE( BUFQ1_3 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% EMPTY    = _LC025 %
% EMPTY    = |7474:U48|2Q %
 EMPTY   = DFFE( FLUSH_4 $  GND,  GICECLK,  VCC,  VCC,  VCC);

% ENRDNDT_2 = _LC006 %
ENRDNDT_2 = DFFE( GND $  VCC, !ESGN8, !_EQ001,  VCC,  VCC);
  _EQ001 =  _X001;
  _X001  = EXP(!EPT5 & !ICEVALID_2);

 EPSGN8  = LCELL( _EQ002 $  BUF0);
  _EQ002 = !BUF0 &  ECTL3 &  ICEHOLD_4;

 ESGN7   = LCELL( _EQ003 $  VCC);
  _EQ003 =  EPSGN4 & !ES0 &  ES2 &  ES3
         #  EPSGN4 & !ES1 &  ES2 &  ES3;

% ESGN8    = _LC024 %
% ESGN8    = |7474:U9|2Q %
 ESGN8   = DFFE(!NESGN8Q_2 $  GND,  ICECLK1, !_EQ004, !_EQ005,  VCC);
  _EQ004 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ005 = !NESGN8Q_2 &  _X002;
  _X002  = EXP( EPS0 &  EPS1 &  EPS2 &  EPS3);

 ESGN9   = LCELL( _EQ006 $  VCC);
  _EQ006 = !NSTROBE & !PRTNDTVL_2;

% ESGN10   = _LC022 %
% ESGN10   = |7474:U13|1Q %
 ESGN10  = DFFE( GND $  GND, !ESGN8,  VCC, !_EQ007,  VCC);
  _EQ007 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  NSTROBE;

 ETB2    = LCELL( _EQ008 $  GND);
  _EQ008 =  BUFQ2_3 &  BUFQ4_3 &  EPSGN3;

% FLUSH_4  = _LC009 %
FLUSH_4  = DFFE( GND $  GND,  NSTROBE,  VCC, !_EQ009,  VCC);
  _EQ009 = !EPS6 &  EPS7;

% ICEACTIVE_2 = _LC003 %
ICEACTIVE_2 = DFFE( _EQ010 $ !EPS3,  GICECLK,  VCC, !_EQ011,  VCC);
  _EQ010 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ011 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

% ICEHOLD_4 = _LC004 %
ICEHOLD_4 = DFFE( NEPHOLDQ_4 $  GND,  GICECLK,  VCC, !_EQ012,  VCC);
  _EQ012 =  _X003;
  _X003  = EXP( EPS0 &  EPS1 &  EPS2 &  EPS3 & !EPT5);

% ICEVALID_2 = _LC007 %
ICEVALID_2 = DFFE( _EQ013 $  GND, !ICECLK1, !EPT5,  VCC,  VCC);
  _EQ013 = !NSTROBE & !PRTNDTVL_2;

% NEPHOLDQ_4 = _LC001 %
NEPHOLDQ_4 = DFFE( _EQ014 $ !BUF0, !EPSGN3,  VCC, !_EQ015,  VCC);
  _EQ014 = !BUF0 &  ECTL3 &  ICEHOLD_4;
  _EQ015 =  _X003;

 NERD    = LCELL( _EQ016 $  VCC);
  _EQ016 = !ES1 & !NSTROBE;

% NESGN8Q_2 = _LC011 %
NESGN8Q_2 = DFFE( GND $  GND,  GND, !_EQ017, !ESGN8,  VCC);
  _EQ017 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

 NEWR    = LCELL( _EQ018 $  VCC);
  _EQ018 = !ES0 &  ES1 & !NSTROBE;

% NONCEDRV = _LC015 %
% NONCEDRV = |7474:U50|1Q %
 NONCEDRV = DFFE( GND $  VCC,  NRESDLY,  NSYSRES,  VCC,  VCC);

% NSTROBE  = _LC026 %
% NSTROBE  = |7474:U5|2Q %
 NSTROBE = DFFE( ICEACTIVE_2 $  GND, !GICECLK,  VCC,  VCC,  VCC);

% NSYSRES  = _LC013 %
% NSYSRES  = |7474:U50|2Q %
 NSYSRES = DFFE( _EQ019 $  GND,  GICECLK,  VCC,  VCC,  VCC);
  _EQ019 =  NEPRES &  NICERES &  NPOWERUP;

% PRTNDTVL_2 = _LC008 %
PRTNDTVL_2 = DFFE( GND $  GND,  GND, !_EQ020, !_EQ021,  VCC);
  _EQ020 =  ENRDNDT_2 &  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ021 =  _X001;


%
    Shareable expanders that are duplicated in multiple LABs:
    (none)
%


Project Information                     c:\orcad4.04\orcad\ec7032v3\ec7032.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                          = off

Logic Synthesis:

   Default Synthesis Style             = Normal

      Logic option settings in 'Normal' style for 'MAX7000' family

      minimization                     = full
      parallel_expanders               = off
      soft_buffer_insertion            = on
      turbo_bit                        = on
      xor_synthesis                    = on

   Other logic synthesis settings:

      Automatic Global Clock           = off
      Automatic Global Clear           = off
      Automatic Global Preset          = off
      Automatic Global Output Enable   = off
      Automatic Peripheral Registers   = off

Functional SNF Extractor               = off

Linked SNF Extractor                   = off
Timing SNF Extractor                   = on
Optimize Timing SNF                    = off
Ignore Previous Fit                    = on
Automatic LCELL Insertion              = off
Generate JEDEC Files                   = off
Total Recompile                        = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                    = off
Verilog Netlist Writer                 = off
VHDL Netlist Writer                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor          00:00:26
   Database Builder                    00:00:08
   Logic Synthesizer                   00:00:05
   Partitioner                         00:00:02
   Fitter                              00:00:09
   Timing SNF Extractor                00:00:03
   Assembler                           00:00:02
   --------------------------          --------
   Total Time                          00:00:55

