Project Information                     c:\x\orcad4.04\orcad\ec7032\ec7032.rpt

MAX+plus II Compiler Report File
Version 8.1 9/12/97
Compiled: 04/27/98 09:35:02

Copyright (C) 1991-1997 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

ec7032    EPM7032LC44-7    22       13       0      25      3           78 %

User Pins:                 22       13       0  



Project Information                     c:\x\orcad4.04\orcad\ec7032\ec7032.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

ec7032@39                         BUFNICEBRK
ec7032@4                          BUF0
ec7032@7                          ECTL3
ec7032@32                         EMPTY
ec7032@6                          EPSGN3
ec7032@28                         EPSGN4
ec7032@8                          EPSGN8
ec7032@11                         EPS0
ec7032@12                         EPS1
ec7032@13                         EPS2
ec7032@14                         EPS3
ec7032@38                         EPS6
ec7032@37                         EPS7
ec7032@9                          EPT5
ec7032@29                         ESGN7
ec7032@33                         ESGN8
ec7032@34                         ESGN9
ec7032@36                         ESGN10
ec7032@24                         ES0
ec7032@25                         ES1
ec7032@26                         ES2
ec7032@27                         ES3
ec7032@5                          ETB2
ec7032@43                         GICECLK
ec7032@44                         ICECLK1
ec7032@40                         NERD
ec7032@41                         NEWR
ec7032@2                          NICEBRK
ec7032@17                         NICERES
ec7032@21                         NPOWERUP
ec7032@19                         NRESDLY
ec7032@31                         NSTROBE
ec7032@18                         NSYSRES
ec7032@16                         NTRES
ec7032@20                         TARHIZ


Project Information                     c:\x\orcad4.04\orcad\ec7032\ec7032.rpt

** FILE HIERARCHY **



|74174:U29|
|7474:U5|
|7474:U9|
|7474:U13|
|7474:U21|
|7474:U28|
|7474:U43|
|7474:U48|
|7474:U50|
|7474:U53|


Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

***** Logic for device 'ec7032' compiled without errors.




Device: EPM7032LC44-7

Device Options:
    Turbo                                      = ON
    Security                                   = OFF



Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** ERROR SUMMARY **

Info: Chip 'ec7032' in device 'EPM7032LC44-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                 
                                                 
                                                 
                            N     I  G           
                E           I     C  I           
                P           C     E  C           
                S  E  B     E     C  E     N  N  
                G  T  U  V  B  G  L  C  G  E  E  
                N  B  F  C  R  N  K  L  N  W  R  
                3  2  0  C  K  D  1  K  D  R  D  
              -----------------------------------_ 
            /   6  5  4  3  2  1 44 43 42 41 40   | 
     ECTL3 |  7                                39 | BUFNICEBRK 
    EPSGN8 |  8                                38 | EPS6 
      EPT5 |  9                                37 | EPS7 
       GND | 10                                36 | ESGN10 
      EPS0 | 11                                35 | VCC 
      EPS1 | 12         EPM7032LC44-7          34 | ESGN9 
      EPS2 | 13                                33 | ESGN8 
      EPS3 | 14                                32 | EMPTY 
       VCC | 15                                31 | NSTROBE 
     NTRES | 16                                30 | GND 
   NICERES | 17                                29 | ESGN7 
           |_  18 19 20 21 22 23 24 25 26 27 28  _| 
             ------------------------------------ 
                N  N  T  N  G  V  E  E  E  E  E  
                S  R  A  P  N  C  S  S  S  S  P  
                Y  E  R  O  D  C  0  1  2  3  S  
                S  S  H  W                    G  
                R  D  I  E                    N  
                E  L  Z  R                    4  
                S  Y     U                       
                         P                       
                                                 
                                                 


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    16/16(100%)  16/16(100%)   2/16( 12%)  28/36( 77%) 
B:    LC17 - LC32     9/16( 56%)  16/16(100%)   1/16(  6%)  18/36( 50%) 


Total dedicated input pins used:                 3/4      ( 75%)
Total I/O pins used:                            32/32     (100%)
Total logic cells used:                         25/32     ( 78%)
Total shareable expanders used:                  3/32     (  9%)
Total Turbo logic cells used:                   25/32     ( 78%)
Total shareable expanders not available (n/a):   0/32     (  0%)
Average fan-in:                                  3.72
Total fan-in:                                    93

Total input pins required:                      22
Total output pins required:                     13
Total bidirectional pins required:               0
Total logic cells required:                     25
Total flipflops required:                       19
Total pterms required:                          65
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           3

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4    (1)  (A)      INPUT               0      0   0    0    0    1    2  BUF0
   7    (4)  (A)      INPUT               0      0   0    0    0    1    1  ECTL3
   6    (3)  (A)      INPUT               0      0   0    0    0    1    1  EPSGN3
  28   (28)  (B)      INPUT               0      0   0    0    0    1    0  EPSGN4
  11    (7)  (A)      INPUT               0      0   0    0    0    2    5  EPS0
  12    (8)  (A)      INPUT               0      0   0    0    0    2    5  EPS1
  13    (9)  (A)      INPUT               0      0   0    0    0    2    5  EPS2
  14   (10)  (A)      INPUT               0      0   0    0    0    2    5  EPS3
  38   (20)  (B)      INPUT               0      0   0    0    0    0    1  EPS6
  37   (21)  (B)      INPUT               0      0   0    0    0    0    1  EPS7
   9    (6)  (A)      INPUT               0      0   0    0    0    0    5  EPT5
  24   (32)  (B)      INPUT               0      0   0    0    0    2    0  ES0
  25   (31)  (B)      INPUT               0      0   0    0    0    3    0  ES1
  26   (30)  (B)      INPUT               0      0   0    0    0    1    0  ES2
  27   (29)  (B)      INPUT               0      0   0    0    0    1    0  ES3
  43      -   -       INPUT               0      0   0    0    0    3    6  GICECLK
  44      -   -       INPUT               0      0   0    0    0    2    1  ICECLK1
   2      -   -       INPUT               0      0   0    0    0    1    0  NICEBRK
  17   (12)  (A)      INPUT               0      0   0    0    0    1    0  NICERES
  21   (16)  (A)      INPUT               0      0   0    0    0    1    0  NPOWERUP
  19   (14)  (A)      INPUT               0      0   0    0    0    1    0  NRESDLY
  16   (11)  (A)      INPUT               0      0   0    0    0    1    0  NTRES


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell


Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  39     19    B         FF     t         0      0   0    2    0    0    0  BUFNICEBRK (|7474:U53|:9)
  32     25    B         FF     t         0      0   0    1    1    0    0  EMPTY (|7474:U48|:10)
   8      5    A     OUTPUT     t         0      0   0    2    1    0    0  EPSGN8
  29     27    B     OUTPUT     t         0      0   0    5    0    0    0  ESGN7
  33     24    B         FF     t         1      0   0    5    1    1    2  ESGN8 (|7474:U9|:10)
  34     23    B     OUTPUT     t         0      0   0    0    2    0    0  ESGN9
  36     22    B         FF     t         0      0   0    4    2    0    0  ESGN10 (|7474:U13|:9)
   5      2    A     OUTPUT     t         0      0   0    1    2    0    0  ETB2
  40     18    B     OUTPUT     t         0      0   0    1    1    0    0  NERD
  41     17    B     OUTPUT     t         0      0   0    2    1    0    0  NEWR
  31     26    B         FF     t         0      0   0    1    1    4    2  NSTROBE (|7474:U5|:10)
  18     13    A         FF     t         0      0   0    4    0    1    0  NSYSRES (|7474:U50|:10)
  20     15    A         FF     t !       0      0   0    1    1    0    0  TARHIZ (|7474:U50|:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell


Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (16)    11    A       DFFE     t        0      0   0    5    0    1    0  |7474:U5|1Q (|7474:U5|:9)
  (9)     6    A       DFFE     t        0      0   0    4    1    1    0  |7474:U9|1Q (|7474:U9|:9)
  (7)     4    A       DFFE     t        0      0   0    2    2    0    2  |7474:U21|1Q (|7474:U21|:9)
 (12)     8    A       DFFE     t        1      1   0    5    2    1    1  |7474:U21|2Q (|7474:U21|:10)
  (6)     3    A       DFFE     t        1      1   0    1    2    0    1  |7474:U28|1Q (|7474:U28|:9)
 (21)    16    A       DFFE     t        1      1   0    8    1    0    1  |7474:U43|1Q (|7474:U43|:9)
 (19)    14    A       DFFE     t        1      1   0    6    1    1    1  |7474:U43|2Q (|7474:U43|:10)
 (14)    10    A       DFFE     t        0      0   0    2    1    1    0  |7474:U48|1Q (|7474:U48|:9)
 (13)     9    A       DFFE     t        0      0   0    1    1    1    1  |74174:U29|4Q (|74174:U29|:9)
 (11)     7    A       DFFE     t        0      0   0    1    1    0    1  |74174:U29|3Q (|74174:U29|:10)
  (4)     1    A       DFFE     t        0      0   0    1    1    1    0  |74174:U29|2Q (|74174:U29|:11)
 (17)    12    A       DFFE     t        0      0   0    2    0    0    1  |74174:U29|1Q (|74174:U29|:12)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell


Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                         Logic cells placed in LAB 'A'
        +------------------------------- LC5 EPSGN8
        | +----------------------------- LC2 ETB2
        | | +--------------------------- LC13 NSYSRES
        | | | +------------------------- LC15 TARHIZ
        | | | | +----------------------- LC11 |7474:U5|1Q
        | | | | | +--------------------- LC6 |7474:U9|1Q
        | | | | | | +------------------- LC4 |7474:U21|1Q
        | | | | | | | +----------------- LC8 |7474:U21|2Q
        | | | | | | | | +--------------- LC3 |7474:U28|1Q
        | | | | | | | | | +------------- LC16 |7474:U43|1Q
        | | | | | | | | | | +----------- LC14 |7474:U43|2Q
        | | | | | | | | | | | +--------- LC10 |7474:U48|1Q
        | | | | | | | | | | | | +------- LC9 |74174:U29|4Q
        | | | | | | | | | | | | | +----- LC7 |74174:U29|3Q
        | | | | | | | | | | | | | | +--- LC1 |74174:U29|2Q
        | | | | | | | | | | | | | | | +- LC12 |74174:U29|1Q
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':
LC13 -> - - - * - - - - - - - - - - - - | * - | <-- NSYSRES
LC4  -> - - - - - - - * * - - - - - - - | * - | <-- |7474:U21|1Q
LC8  -> - - - - - - * - - - - - - - - - | * * | <-- |7474:U21|2Q
LC3  -> - - - - - - - * - - - - - - - - | * - | <-- |7474:U28|1Q
LC16 -> - - - - - - - - - - * - - - - - | * - | <-- |7474:U43|1Q
LC14 -> * - - - - - - - - * - - - - - - | * - | <-- |7474:U43|2Q
LC9  -> - * - - - - - - - - - - - * - - | * - | <-- |74174:U29|4Q
LC7  -> - - - - - - - - - - - - - - * - | * - | <-- |74174:U29|3Q
LC1  -> - * - - - - - - - - - - - - - - | * - | <-- |74174:U29|2Q
LC12 -> - - - - - - - - - - - - * - - - | * - | <-- |74174:U29|1Q

Pin
4    -> * - - - - - - - - * - - - - - * | * - | <-- BUF0
7    -> * - - - - - - - - * - - - - - - | * - | <-- ECTL3
6    -> - * - - - - - - - * - - - - - - | * - | <-- EPSGN3
11   -> - - - - * * - * - * * - - - - - | * * | <-- EPS0
12   -> - - - - * * - * - * * - - - - - | * * | <-- EPS1
13   -> - - - - * * - * - * * - - - - - | * * | <-- EPS2
14   -> - - - - * * - * - * * - - - - - | * * | <-- EPS3
38   -> - - - - - - - - - - - * - - - - | * - | <-- EPS6
37   -> - - - - - - - - - - - * - - - - | * - | <-- EPS7
9    -> - - - - - - * * * * * - - - - - | * - | <-- EPT5
43   -> - - * - * - - - - - * - * * * * | * * | <-- GICECLK
44   -> - - - - - - * - - - - - - - - - | * * | <-- ICECLK1
2    -> - - - - - - - - - - - - - - - - | - * | <-- NICEBRK
17   -> - - * - - - - - - - - - - - - - | * - | <-- NICERES
21   -> - - * - - - - - - - - - - - - - | * - | <-- NPOWERUP
19   -> - - - * - - - - - - - - - - - - | * - | <-- NRESDLY
16   -> - - * - - - - - - - - - - - - - | * - | <-- NTRES
LC24 -> - - - - - * - - * - - - - - - - | * * | <-- ESGN8
LC26 -> - - - - - - * - - - - * - - - - | * * | <-- NSTROBE


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC19 BUFNICEBRK
        | +--------------- LC25 EMPTY
        | | +------------- LC27 ESGN7
        | | | +----------- LC24 ESGN8
        | | | | +--------- LC23 ESGN9
        | | | | | +------- LC22 ESGN10
        | | | | | | +----- LC18 NERD
        | | | | | | | +--- LC17 NEWR
        | | | | | | | | +- LC26 NSTROBE
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC24 -> - - - - - * - - - | * * | <-- ESGN8
LC26 -> - - - - * * * * - | * * | <-- NSTROBE

Pin
28   -> - - * - - - - - - | - * | <-- EPSGN4
11   -> - - - * - * - - - | * * | <-- EPS0
12   -> - - - * - * - - - | * * | <-- EPS1
13   -> - - - * - * - - - | * * | <-- EPS2
14   -> - - - * - * - - - | * * | <-- EPS3
24   -> - - * - - - - * - | - * | <-- ES0
25   -> - - * - - - * * - | - * | <-- ES1
26   -> - - * - - - - - - | - * | <-- ES2
27   -> - - * - - - - - - | - * | <-- ES3
43   -> - * - - - - - - * | * * | <-- GICECLK
44   -> * - - * - - - - - | * * | <-- ICECLK1
2    -> * - - - - - - - - | - * | <-- NICEBRK
LC11 -> - - - - - - - - * | - * | <-- |7474:U5|1Q
LC6  -> - - - * - - - - - | - * | <-- |7474:U9|1Q
LC8  -> - - - - * - - - - | * * | <-- |7474:U21|2Q
LC10 -> - * - - - - - - - | - * | <-- |7474:U48|1Q


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:            c:\x\orcad4.04\orcad\ec7032\ec7032.rpt
ec7032

** EQUATIONS **

BUF0     : INPUT;
ECTL3    : INPUT;
EPSGN3   : INPUT;
EPSGN4   : INPUT;
EPS0     : INPUT;
EPS1     : INPUT;
EPS2     : INPUT;
EPS3     : INPUT;
EPS6     : INPUT;
EPS7     : INPUT;
EPT5     : INPUT;
ES0      : INPUT;
ES1      : INPUT;
ES2      : INPUT;
ES3      : INPUT;
GICECLK  : INPUT;
ICECLK1  : INPUT;
NICEBRK  : INPUT;
NICERES  : INPUT;
NPOWERUP : INPUT;
NRESDLY  : INPUT;
NTRES    : INPUT;

-- Node name is 'BUFNICEBRK' = '|7474:U53|1Q' 
-- Equation name is 'BUFNICEBRK', type is output 
 BUFNICEBRK = DFFE( NICEBRK $  GND,  ICECLK1,  VCC,  VCC,  VCC);

-- Node name is 'EMPTY' = '|7474:U48|2Q' 
-- Equation name is 'EMPTY', type is output 
 EMPTY   = DFFE( _LC010 $  GND,  GICECLK,  VCC,  VCC,  VCC);

-- Node name is 'EPSGN8' 
-- Equation name is 'EPSGN8', location is LC005, type is output.
 EPSGN8  = LCELL( _EQ001 $  BUF0);
  _EQ001 = !BUF0 &  ECTL3 &  _LC014;

-- Node name is 'ESGN7' 
-- Equation name is 'ESGN7', location is LC027, type is output.
 ESGN7   = LCELL( _EQ002 $  VCC);
  _EQ002 =  EPSGN4 & !ES0 &  ES2 &  ES3
         #  EPSGN4 & !ES1 &  ES2 &  ES3;

-- Node name is 'ESGN8' = '|7474:U9|2Q' 
-- Equation name is 'ESGN8', type is output 
 ESGN8   = DFFE(!_LC006 $  GND,  ICECLK1, !_EQ003, !_EQ004,  VCC);
  _EQ003 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ004 = !_LC006 &  _X001;
  _X001  = EXP( EPS0 &  EPS1 &  EPS2 &  EPS3);

-- Node name is 'ESGN9' 
-- Equation name is 'ESGN9', location is LC023, type is output.
 ESGN9   = LCELL( _EQ005 $  VCC);
  _EQ005 = !_LC008 & !NSTROBE;

-- Node name is 'ESGN10' = '|7474:U13|1Q' 
-- Equation name is 'ESGN10', type is output 
 ESGN10  = DFFE( GND $  GND, !ESGN8,  VCC, !_EQ006,  VCC);
  _EQ006 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  NSTROBE;

-- Node name is 'ETB2' 
-- Equation name is 'ETB2', location is LC002, type is output.
 ETB2    = LCELL( _EQ007 $  GND);
  _EQ007 =  EPSGN3 &  _LC001 &  _LC009;

-- Node name is 'NERD' 
-- Equation name is 'NERD', location is LC018, type is output.
 NERD    = LCELL( _EQ008 $  VCC);
  _EQ008 = !ES1 & !NSTROBE;

-- Node name is 'NEWR' 
-- Equation name is 'NEWR', location is LC017, type is output.
 NEWR    = LCELL( _EQ009 $  VCC);
  _EQ009 = !ES0 &  ES1 & !NSTROBE;

-- Node name is 'NSTROBE' = '|7474:U5|2Q' 
-- Equation name is 'NSTROBE', type is output 
 NSTROBE = DFFE( _LC011 $  GND, !GICECLK,  VCC,  VCC,  VCC);

-- Node name is 'NSYSRES' = '|7474:U50|2Q' 
-- Equation name is 'NSYSRES', type is output 
 NSYSRES = DFFE( _EQ010 $  GND,  GICECLK,  VCC,  VCC,  VCC);
  _EQ010 =  NICERES &  NPOWERUP &  NTRES;

-- Node name is 'TARHIZ' = '|7474:U50|1Q' 
-- Equation name is 'TARHIZ', type is output 
TARHIZ   = _LC015~NOT;
_LC015~NOT = DFFE( VCC $  VCC,  NRESDLY,  VCC,  NSYSRES,  VCC);

-- Node name is '|7474:U5|:9' = '|7474:U5|1Q' 
-- Equation name is '_LC011', type is buried 
_LC011   = DFFE( _EQ011 $ !EPS3,  GICECLK,  VCC, !_EQ012,  VCC);
  _EQ011 =  EPS0 &  EPS1 &  EPS2 &  EPS3;
  _EQ012 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

-- Node name is '|7474:U9|:9' = '|7474:U9|1Q' 
-- Equation name is '_LC006', type is buried 
_LC006   = DFFE( GND $  GND,  GND, !_EQ013, !ESGN8,  VCC);
  _EQ013 =  EPS0 &  EPS1 &  EPS2 &  EPS3;

-- Node name is '|7474:U21|:9' = '|7474:U21|1Q' 
-- Equation name is '_LC004', type is buried 
_LC004   = DFFE( _EQ014 $  GND, !ICECLK1, !EPT5,  VCC,  VCC);
  _EQ014 = !_LC008 & !NSTROBE;

-- Node name is '|7474:U21|:10' = '|7474:U21|2Q' 
-- Equation name is '_LC008', type is buried 
_LC008   = DFFE( GND $  GND,  GND, !_EQ015, !_EQ016,  VCC);
  _EQ015 =  EPS0 &  EPS1 &  EPS2 &  EPS3 &  _LC003;
  _EQ016 =  _X002;
  _X002  = EXP(!EPT5 & !_LC004);

-- Node name is '|7474:U28|:9' = '|7474:U28|1Q' 
-- Equation name is '_LC003', type is buried 
_LC003   = DFFE( GND $  VCC, !ESGN8, !_EQ017,  VCC,  VCC);
  _EQ017 =  _X002;
  _X002  = EXP(!EPT5 & !_LC004);

-- Node name is '|7474:U43|:9' = '|7474:U43|1Q' 
-- Equation name is '_LC016', type is buried 
_LC016   = DFFE( _EQ018 $ !BUF0, !EPSGN3,  VCC, !_EQ019,  VCC);
  _EQ018 = !BUF0 &  ECTL3 &  _LC014;
  _EQ019 =  _X003;
  _X003  = EXP( EPS0 &  EPS1 &  EPS2 &  EPS3 & !EPT5);

-- Node name is '|7474:U43|:10' = '|7474:U43|2Q' 
-- Equation name is '_LC014', type is buried 
_LC014   = DFFE( _LC016 $  GND,  GICECLK,  VCC, !_EQ020,  VCC);
  _EQ020 =  _X003;
  _X003  = EXP( EPS0 &  EPS1 &  EPS2 &  EPS3 & !EPT5);

-- Node name is '|7474:U48|:9' = '|7474:U48|1Q' 
-- Equation name is '_LC010', type is buried 
_LC010   = DFFE( GND $  GND,  NSTROBE,  VCC, !_EQ021,  VCC);
  _EQ021 = !EPS6 &  EPS7;

-- Node name is '|74174:U29|:12' = '|74174:U29|1Q' 
-- Equation name is '_LC012', type is buried 
_LC012   = DFFE( BUF0 $  GND, !GICECLK,  VCC,  VCC,  VCC);

-- Node name is '|74174:U29|:11' = '|74174:U29|2Q' 
-- Equation name is '_LC001', type is buried 
_LC001   = DFFE( _LC007 $  GND, !GICECLK,  VCC,  VCC,  VCC);

-- Node name is '|74174:U29|:10' = '|74174:U29|3Q' 
-- Equation name is '_LC007', type is buried 
_LC007   = DFFE( _LC009 $  GND, !GICECLK,  VCC,  VCC,  VCC);

-- Node name is '|74174:U29|:9' = '|74174:U29|4Q' 
-- Equation name is '_LC009', type is buried 
_LC009   = DFFE( _LC012 $  GND, !GICECLK,  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                     c:\x\orcad4.04\orcad\ec7032\ec7032.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = off
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:03
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:03
   Partitioner                            00:00:01
   Fitter                                 00:00:06
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:15


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,771K
