PALASM 4 v1.5 MACH FITR - MARKET RELEASE (7-24-92)
 (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990,91,92

 
Reading User Design (TRE File)...
 
Reading Device Database ...

*************************************************
     Mach PLD Fitter - v 1.67          EPL210
*************************************************

PAIR Analysis...

Pre-Placement & Equation Usage Checks... 
 
|> WARNING F210 - Design contains both floating & fixed placements.  





*** Timing Analysis for Signals

 Parameter   Min   Max           Signal List (Those having Max delay.)
      Tpd     1     1             ENEPWR            ETB1         EPSGN18 
                                    BUF0 
      Tsu     1     1       _7_M5_REGOUT    _7_M1_REGOUT           M1_QA 
                            _7_M6_REGOUT    _7_M8_REGOUT    _7_M4_REGOUT 
                            _7_M3_REGOUT          ECTL14 
      Tco     0     1               BUF0         EPSGN18 
      Tcr     1     1              M1_QB            ENT0           M1_QC 
                                    ENT1           M1_QD            ENT2 
                                   M1_QE          ECTL14 
.

 Key:
 Tpd - Combinatorial propagation delay, input to output
 Tsu - Combinatorial setup delay before clock
 Tco - clock to output (register output to combinatorial output)
 Tcr - Clock to register setup delay
.......(Register output thru combinatorial logic to reg input)
 All delay values are expressed in terms of array passes




*** Device Resource Checks

                Available        Used        Remaining
        Clocks:     2              2              0
          Pins:    38             35              3     ->    92%
     I/O Macro:    32             19             13
   Total Macro:    64             44             20
 Product Terms:   256             53             80     ->    68%
 
MACH-PLD Resource Checks OK!  



Partitioning Design into Blocks...

|> ERROR F740 - Resource violation in preplacement: (IO Pins) - Block A


*** Last Equations Placed in Blocks

Weakly -    _7_M6_REGOUT    _7_M5_REGOUT    _7_M8_REGOUT    _7_M4_REGOUT 
Assign -    _7_M3_REGOUT    _7_M2_REGOUT    _7_M1_REGOUT           M2_QC |> INFORMATION F085 - Intermediate Error Count: 1, Warning Count: 1
|> INFORMATION F075 - Redo Partitioning with Max Packing Flag=True 

*** Last Equations Placed in Blocks

Weakly -    _7_M6_REGOUT    _7_M5_REGOUT    _7_M8_REGOUT    _7_M4_REGOUT 
Assign -    _7_M3_REGOUT    _7_M2_REGOUT    _7_M1_REGOUT           M1_QA 


|> INFORMATION F050 - Device Utilization.............. *: 69 %



*** Block Partitioning Results

               Array   Product     # I/O    Buried    Signal    Macros
              Inputs    Terms      Macro     Logic    Fanout    Remain
   Block-> A    13        56         8*        6         6         2
   Block-> B    12        64*        7         9        10         0
   Block-> C     7        28         3         4         4         9
   Block-> D    13        28         1         6         6         9



*** Block Signal List

Blk-> A          M2_QH  1          M2_QD  1          M1_QG  1          M1_QF  1
                 M1_QE  1          M1_QD  1           ENT2  1           ENT3  1
                  ENT4  1           ENT5  1        EPSGN13  1           BUF0  2
                ENEPWR  4           ETB1  4

Blk-> B   _7_M5_REGOUT  3          M2_QC  1       _6_X13_Q  1          M2_QG  1
                 M2_QE  1          M2_QB  1          M2_QA  1          M1_QH  1
                 M1_QC  1        EPSGN16  1        EPSGN12  1           ENT7  1
                  ENT6  1           ENT8  1           ENT1  1        EPSGN18  2

Blk-> C          _6_Q6  1          M1_QA  1          M2_QF  1       _6_X12_Q  1
                 M1_QB  1           ENT0  1         ECTL14  3

Blk-> D          _6_Q7  1   _7_M1_REGOUT  2   _7_M2_REGOUT  3   _7_M3_REGOUT  3
          _7_M4_REGOUT  3   _7_M8_REGOUT  3   _7_M6_REGOUT  3



*** Block Input List

Blk-> A           BUF2  1         EPSGN4  2         ECTL18  2         ECTL17  2
                 ETB12  1         EPSGN0  1          M1_QC  2          M1_QD  2
                 M1_QE  2          M1_QF  2          M2_QC  2          M2_QG  1
              _6_X13_Q  1

Singular:           BUF2{         ENEPWR}          ETB12{           BUF0}
                  EPSGN0{           ETB1}          M2_QG{          M2_QH}
                _6_X13_Q{           BUF0}


Blk-> B           BUF2  1          ECTL2  1         ECTL16  1          M1_QB  2
                 M1_QG  2          M1_QH  2          M2_QA  2          M2_QB  2
                 M2_QD  2          M2_QF  2       _6_X12_Q  1   _7_M8_REGOUT  1
       

Singular:           BUF2{   _7_M5_REGOUT}          ECTL2{        EPSGN18}
                  ECTL16{   _7_M5_REGOUT}       _6_X12_Q{        EPSGN18}
            _7_M8_REGOUT{   _7_M5_REGOUT}


Blk-> C         ECTL13  1         ECTL16  1           _7_H  1          M1_QA  2
                 M2_QE  2          M2_QG  1   _7_M6_REGOUT  1

Singular:         ECTL13{          M1_QA}         ECTL16{         ECTL14}
                    _7_H{         ECTL14}          M2_QG{          _6_Q6}
            _7_M6_REGOUT{         ECTL14}


Blk-> D           ETB4  1         ECTL16  6          EPT21  1          ETB12  1
                 EPT22  1         TGTVCC  1           _7_G  1          M2_QH  1
          _7_M1_REGOUT  1   _7_M2_REGOUT  1   _7_M3_REGOUT  1   _7_M4_REGOUT  1
          _7_M5_REGOUT  1

Singular:           ETB4{   _7_M1_REGOUT}          EPT21{   _7_M2_REGOUT}
                   ETB12{   _7_M4_REGOUT}          EPT22{   _7_M3_REGOUT}
                  TGTVCC{   _7_M8_REGOUT}           _7_G{   _7_M6_REGOUT}
                   M2_QH{          _6_Q7}   _7_M1_REGOUT{   _7_M2_REGOUT}
            _7_M2_REGOUT{   _7_M3_REGOUT}   _7_M3_REGOUT{   _7_M4_REGOUT}
            _7_M4_REGOUT{   _7_M8_REGOUT}   _7_M5_REGOUT{   _7_M6_REGOUT}
         

|> INFORMATION F070 - Multiple Assignment Mode - Repeat Count: 4
Assigning Resources...


Flags Used:             Unplace=False        Max Packing=True 
Flags Used:        Expand Small=False         Expand All=False



*** Macro Block B

        EPSGN18 (B 10)
           ENT1 (B  0)
           ENT8 (B  2)
           ENT6 (B  4)
           ENT7 (B  6)
        EPSGN12 (B 12)
        EPSGN16 (B 14)

 Buried Logic>        _6_X13_Q           M2_QA           M2_QB           M1_QC
                         M2_QC    _7_M5_REGOUT           M2_QE           M2_QG
                         M1_QH
      Targets>   1(na)   3(na)   5(na)   7(na)   8(17)   9(na)  11(na)  13(na)
                15(na)

       _6_X13_Q (B  1) -> (A  5)
          M2_QA (B  3) -> (B  7)
          M2_QB (B  5) -> (B  9)
          M1_QC (B  7) -> (A  0)
          M2_QC (B  8) -> (A  3)
   _7_M5_REGOUT (B  9) -> (D  6)
          M2_QE (B 11) -> (C  8)
          M2_QG (B 13) -> (A 10) (C 10)
          M1_QH (B 15) -> (B  1)



*** Macro Block A

           ETB1 (A  0)
         ENEPWR (A 12)
           BUF0 (A 14)
        EPSGN13 (A  2)
           ENT5 (A  4)
           ENT4 (A  6)
           ENT3 (A  8)
           ENT2 (A 10)

 Buried Logic>           M1_QD           M2_QD           M1_QE           M1_QF
                         M1_QG           M2_QH
      Targets>   1(na)   3(na)   5(na)   7(na)   9(na)  11(na)  13(na)  15(na)
              

          M1_QD (A  1) -> (A  2)
          M2_QD (A  3) -> (B  4)
          M1_QE (A  5) -> (A  6)
          M1_QF (A  7) -> (A  8)
          M1_QG (A  9) -> (B  3)
          M2_QH (A 11) -> (D  5)



*** Macro Block D


   I/O Macros>           _6_Q7
      Targets>   2(42)   4(41)   6(40)

          _6_Q7 (D  2)  

 Buried Logic>    _7_M1_REGOUT    _7_M2_REGOUT    _7_M3_REGOUT    _7_M4_REGOUT
                  _7_M6_REGOUT    _7_M8_REGOUT
      Targets>   0(43)   1(na)   3(na)   4(41)   5(na)   6(40)   7(na)   8(39)
                 9(na)  10(38)  11(na)  12(37)  13(na)  14(36)  15(na)

   _7_M1_REGOUT (D  0) -> (D  8)
   _7_M2_REGOUT (D  1) -> (D  0)
   _7_M3_REGOUT (D  3) -> (D 12)
   _7_M4_REGOUT (D  4) -> (D  3)
   _7_M6_REGOUT (D  5) -> (C  4)
   _7_M8_REGOUT (D  6) -> (B  5)



*** Macro Block Inputs

           BUF2 (I  0) -> (A 12) (B  2)
           ETB4 (I  1) -> (D 16)
          ECTL2 (I  3) -> (B  6)
         ECTL13 (I  4) -> (C  7)
         ECTL16 (I  5) -> (B  8) (C  5) (D 13)



*** Macro Block C

           ENT0 (C  0)
         ECTL14 (C 14)

   I/O Macros>           _6_Q6
      Targets>   2(25)   4(26)   6(27)   8(28)

          _6_Q6 (C  2)  

 Buried Logic>        _6_X12_Q           M1_QA           M1_QB           M2_QF
              
      Targets>   1(na)   3(na)   4(26)   5(na)   6(27)   7(na)   8(28)   9(na)
                10(29)  11(na)  12(30)  13(na)  15(na)

       _6_X12_Q (C  1) -> (B 15)
          M1_QB (C  3) -> (B 10)
          M2_QF (C  4) -> (B  0)
          M1_QA (C  5) -> (C  1)

         EPSGN0 (D  0) -> (A  7)
         TGTVCC (D  8) -> (D  2)
         EPSGN4 (B  8) -> (A 21)
          EPT22 (D 10)?
         ECTL18 (C 10) -> (A 17)
          ETB12 (D 12) -> (A  4) (D  4)
         ECTL17 (C 12) -> (A  1)
          EPT21 (D 14) -> (D 14)
          EPT22 (D 10) ->   Blocked -> Reshuffling SwMtrx
          M2_QH -> (D 18)    Moved. -> Reshuffling SwMtrx
         ECTL16 -> (D  5)    Moved. -> Reshuffling SwMtrx
   _7_M4_REGOUT -> (D 13)    Moved.
          EPT22 -> (D  3)

       Inputs>            _7_H            _7_G
      Targets>   4(41)   6(40)

           _7_H (D  4) -> (C  0)
           _7_G (D  6) -> (D  1)





Wiring Completion:  100% -> (  0 nc)

|> INFORMATION F058 - Total Block Fanout (All Signals) *: 45 


*** Signals - Tabular Information

          Signal   #   P/N #   (Loc)      Type     Logic  # PT    Blocks
           ETB1    1     2      A  0     i/o pin    comb     2    .....
       _6_X15_Q    2     4      A  2    out pair    d-ff     1    .....
       _4_X11_Q    3     6      A  4    out pair    d-ff     1    .....
       _4_X12_Q    4     8      A  6    out pair    d-ff     1    .....
       _4_X16_Q    5    10      A  8    out pair    d-ff     1    .....
       _4_X15_Q    6    12      A 10    out pair    d-ff     1    .....
         ENEPWR    7     8      A 12     i/o pin    comb     2    .....
           BUF0    8     9      A 14     i/o pin    comb     1    .....
           BUF2    9    10      I  0       input       .     .    .AB..
           ETB4   10    11      I  1       input       .     .    ....D
         ECTL15   11    13      I  2   clock pin       .     .    .....
       _6_X11_Q   12    32      B 14    out pair    d-ff     1    .....
       _6_X16_Q   13    30      B 12    out pair    d-ff     1    .....
        EPSGN18   14    16      B 10     i/o pin    comb     1    .....
         EPSGN4   15    17      B  8       input       .     .    .A...
        _4_X9_Q   16    24      B  6    out pair    d-ff     1    .....
       _4_X10_Q   17    22      B  4    out pair    d-ff     1    .....
       _6_X14_Q   18    20      B  2    out pair    d-ff     1    .....
       _4_X13_Q   19    18      B  0    out pair    d-ff     1    .....
       _4_X14_Q   20    34      C  0    out pair    d-ff     1    .....
         ECTL18   21    29      C 10       input       .     .    .A...
         ECTL17   22    30      C 12       input       .     .    .A...
         ECTL14   23    31      C 14     i/o pin    d-ff     2    .....
          ECTL2   24    32      I  3       input       .     .    ..B..
         ECTL13   25    33      I  4       input       .     .    ...C.
         ECTL16   26    35      I  5   clock pin       .     .    ..BCD
          EPT21   27    36      D 14       input       .     .    ....D
          ETB12   28    37      D 12       input       .     .    .A..D
          EPT22   29    38      D 10       input       .     .    ....D
         TGTVCC   30    39      D  8       input       .     .    ....D
         EPSGN0   31    43      D  0       input       .     .    .A...
        EPSGN13   32     3      A  2     i/o pin    d-ff     1    .....
           ENT5   33     4      A  4     i/o pin    d-ff     1    .....
           ENT4   34     5      A  6     i/o pin    d-ff     1    .....
           ENT3   35     6      A  8     i/o pin    d-ff     1    .....
           ENT2   36     7      A 10     i/o pin    d-ff     1    .....
           ENT1   37    21      B  0     i/o pin    d-ff     1    .....
           ENT8   38    20      B  2     i/o pin    d-ff     1    .....
           ENT6   39    19      B  4     i/o pin    d-ff     1    .....
           ENT7   40    18      B  6     i/o pin    d-ff     1    .....
        EPSGN12   41    15      B 12     i/o pin    d-ff     1    .....
        EPSGN16   42    14      B 14     i/o pin    d-ff     1    .....
           ENT0   43    24      C  0     i/o pin    d-ff     1    .....
          _6_Q6   44    25      C  2     i/o pin    d-ff     1    .....
          _6_Q7   45    42      D  2     i/o pin    d-ff     1    .....
           _7_H   46    41      D  4       input       .     .    ...C.
           _7_G   47    40      D  6       input       .     .    ....D
          M1_QA   48    39      C  5      buried    d-ff     1    ...C.
          M1_QB   49    37      C  3      buried    d-ff     1    ..B..
          M1_QC   50    25      B  7      buried    d-ff     1    .A...
          M1_QD   51     3      A  1      buried    d-ff     1    .A...
          M1_QE   52     7      A  5      buried    d-ff     1    .A...
          M1_QF   53     9      A  7      buried    d-ff     1    .A...
          M1_QG   54    11      A  9      buried    d-ff     1    ..B..
          M1_QH   55    33      B 15      buried    d-ff     1    ..B..
          M2_QA   56    21      B  3      buried    d-ff     1    ..B..
          M2_QB   57    23      B  5      buried    d-ff     1    ..B..
          M2_QC   58    26      B  8      buried    d-ff     1    .A...
          M2_QD   59     5      A  3      buried    d-ff     1    ..B..
          M2_QE   60    29      B 11      buried    d-ff     1    ...C.
          M2_QF   61    38      C  4      buried    d-ff     1    ..B..
          M2_QG   62    31      B 13      buried    d-ff     1    .A.C.
          M2_QH   63    13      A 11      buried    d-ff     1    ....D
       _6_X13_Q   64    19      B  1      buried    d-ff     1    .A...
       _6_X12_Q   65    35      C  1      buried    d-ff     1    ..B..
   _7_M1_REGOUT   66    50      D  0      buried    d-ff     1    ....D
   _7_M2_REGOUT   67    51      D  1      buried    d-ff     2    ....D
   _7_M3_REGOUT   68    53      D  3      buried    d-ff     2    ....D
   _7_M4_REGOUT   69    54      D  4      buried    d-ff     2    ....D
   _7_M8_REGOUT   70    56      D  6      buried    d-ff     2    ..B..
   _7_M5_REGOUT   71    27      B  9      buried    d-ff     2    ....D
   _7_M6_REGOUT   72    55      D  5      buried    d-ff     2    ...C.
.

 Key:
 P/N # - Pin/Node Number
 .?. - Signal Unplaced
 (Loc) - Macrocell Location (Block & Cell)
 # PT - Number of used product terms in logic
 Blocks- Device blocks driven by signal
 comb - Combinatorial logic function
 d-ff - D-Type Flip-flop
 t-ff - T-Type Flip-flop
 Note: Registered input storage equations (MACH-2xx family)
 ..... are realized with 0 array product terms.


*** Signals - Equations Where Used

   Signal Source                   Fanout List

           BUF2:   _7_M5_REGOUT          ENEPWR 
               {BA}
           ETB4:   _7_M1_REGOUT 
               {D}
         EPSGN4:         ENEPWR            ETB1 
               {AA}
         ECTL18:         ENEPWR            ETB1 
               {AA}
         ECTL17:         ENEPWR            ETB1 
               {AA}
          ECTL2:        EPSGN18 
               {B}
         ECTL13:          M1_QA 
               {C}
         ECTL16:   _7_M6_REGOUT    _7_M5_REGOUT    _7_M8_REGOUT    _7_M4_REGOUT 
               :   _7_M3_REGOUT    _7_M2_REGOUT    _7_M1_REGOUT          ECTL14 
               {DBDD DDDC}

          EPT21:   _7_M2_REGOUT 
               {D}
          ETB12:   _7_M4_REGOUT            BUF0 
               {DA}
          EPT22:   _7_M3_REGOUT 
               {D}
         TGTVCC:   _7_M8_REGOUT 
               {D}
         EPSGN0:           ETB1 
               {A}
           _7_H:         ECTL14 
               {C}
           _7_G:   _7_M6_REGOUT 
               {D}
          M1_QA:          M1_QB            ENT0            ENT0 
               {CCC}
          M1_QB:          M1_QC            ENT1            ENT1 
               {BBB}
          M1_QC:          M1_QD            ENT2            ENT2 
               {AAA}
          M1_QD:          M1_QE            ENT3            ENT3 
               {AAA}
          M1_QE:          M1_QF            ENT4            ENT4 
               {AAA}
          M1_QF:          M1_QG            ENT5            ENT5 
               {AAA}
          M1_QG:          M1_QH            ENT6            ENT6 
               {BBB}
          M1_QH:          M2_QA            ENT7            ENT7 
               {BBB}
          M2_QA:          M2_QB            ENT8            ENT8 
               {BBB}
          M2_QB:       _6_X13_Q           M2_QC 
               {BB}
          M2_QC:          M2_QD         EPSGN13         EPSGN13 
               {AAA}
          M2_QD:          M2_QE         EPSGN12         EPSGN12 
               {BBB}
          M2_QE:       _6_X12_Q           M2_QF 
               {CC}
          M2_QF:          M2_QG         EPSGN16         EPSGN16 
               {BBB}
          M2_QG:          M2_QH           _6_Q6 
               {AC}
          M2_QH:          _6_Q7 
               {D}
       _6_X13_Q:           BUF0 
               {A}
       _6_X12_Q:        EPSGN18 
               {B}
   _7_M1_REGOUT:   _7_M2_REGOUT 
               {D}
   _7_M2_REGOUT:   _7_M3_REGOUT 
               {D}
   _7_M3_REGOUT:   _7_M4_REGOUT 
               {D}
   _7_M4_REGOUT:   _7_M8_REGOUT 
               {D}
   _7_M8_REGOUT:   _7_M5_REGOUT 
               {B}
   _7_M5_REGOUT:   _7_M6_REGOUT 
               {D}
   _7_M6_REGOUT:         ECTL14 
               {C}



*** Outputs with no feedback

             ETB1          ENEPWR            BUF0         EPSGN18          ECTL14 
          EPSGN13            ENT5            ENT4            ENT3            ENT2 
             ENT1            ENT8            ENT6            ENT7         EPSGN12 
          EPSGN16            ENT0           _6_Q6           _6_Q7 


*** Feedback Map - EPL210

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
         | 0|    M1_QC : 0|     |21| EPSGN4        M2_QF : 0|     |21|        
         | 1|   ECTL17 : 1|     |20|               M1_QH : 1|     |20|        
         | 2|    M1_QD : 2|     |19|                BUF2 : 2|     |19|        
         | 3|    M2_QC : 3|     |18|               M1_QG : 3|     |18|        
         | 4|    ETB12 : 4|     |17| ECTL18        M2_QD : 4|     |17|        
         | 5|  _6_X13_Q  5|     |16|             _7_M8_RE  5|     |16|        
         '--'    M1_QE : 6|     |15|               ECTL2 : 6|     |15: _6_X12_
                EPSGN0 : 7|     |14|               M2_QA : 7|     |14|        
                 M1_QF : 8|     |13|              ECTL16 : 8|     |13|        
                       | 9|     |12: BUF2          M2_QB : 9|     |12|        
K:  * Used       M2_QG :10|     |11|               M1_QB :10|     |11|        
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A         _7_H : 0|     |21|             _7_M2_RE  0|     |21|        
    0 RegIn      M1_QA : 1|     |20|                _7_G : 1|     |20|        
                       | 2|     |19|              TGTVCC : 2|     |19|        
                       | 3|     |18|               EPT22 : 3|     |18| M2_QH  
               _7_M6_RE  4|     |17|               ETB12 : 4|     |17|        
                ECTL16 : 5|     |16|              ECTL16 : 5|     |16| ETB4   
                       | 6|     |15|             _7_M5_RE  6|     |15|        
                ECTL13 : 7|     |14|                     | 7|     |14: EPT21  
                 M2_QE : 8|     |13|             _7_M1_RE  8|     |13: _7_M4_R
                       | 9|     |12|                     | 9|     |12: _7_M3_R
                 M2_QG :10|     |11|                     |10|     |11|        
                       '--+-u--u+--'                     '--+-u--u+--'        



*** Logic Map - EPL210

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
     BUF2| 0|     ETB1 | 0| 2  #|21|                ENT1 | 0| 1  #|21|        
     ETB4| 1|    M1_QD | 1| 1  #|20|             _6_X13_Q  1| 1  #|20|        
   ECTL15| 2|  EPSGN13 | 2| 1  #|19|                ENT8 | 2| 1  #|19|        
    ECTL2| 3|    M2_QD | 3| 1  #|18|               M2_QA | 3| 1  #|18|        
   ECTL13| 4|     ENT5 | 4| 1  #|17|                ENT6 | 4| 1  #|17|        
   ECTL16| 5|    M1_QE | 5| 1  #|16|               M2_QB | 5| 1  #|16|        
         '--'     ENT4 | 6| 1  .|15|                ENT7 | 6| 1  1|15| M1_QH  
                 M1_QF | 7| 1  1|14| BUF0          M1_QC | 7| 1  1|14| EPSGN16
                  ENT3 | 8| 1  .|13|               M2_QC | 8| 1  1|13| M2_QG  
                 M1_QG | 9| 1  2|12| ENEPWR      _7_M5_RE  9| 2  1|12| EPSGN12
K:  * Used        ENT2 |10| 1  1|11| M2_QH       EPSGN18 |10| 1  1|11| M2_QE  
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A         ENT0 | 0| 1  #|21|             _7_M1_RE  0| 1  #|21|        
    0 RegIn    _6_X12_Q  1| 1  #|20|             _7_M2_RE  1| 2  #|20|        
                 _6_Q6 | 2| 1  #|19|               _6_Q7 | 2| 1  #|19|        
                 M1_QB | 3| 1  #|18|             _7_M3_RE  3| 2  #|18|        
                 M2_QF | 4| 1  #|17|             _7_M4_RE  4| 2  #|17|        
                 M1_QA | 5| 1  #|16|             _7_M6_RE  5| 2  #|16|        
                       | 6| .  .|15|             _7_M8_RE  6| 2  .|15|        
                       | 7| .  2|14| ECTL14              | 7| .  .|14|        
                       | 8| .  .|13|                     | 8| .  .|13|        
                       | 9| .  .|12|                     | 9| .  .|12|        
                       |10| .  .|11|                     |10| .  .|11|        
                       '--+-u--u+--'                     '--+-u--u+--'        


*** Pin Map - EPL210
                                                                   
                                                                   
                                                                   
                                                                   
                                   ETB1                            
                             EPSGN13  |        EPSGN0              
                             ENT5  |  |        |  _6_Q7            
                          ENT4  |  |  |        |  |  _7_H          
                       ENT3  |  |  |  |        |  |  |  _7_G       
                          |  |  |  |  |        |  |  |  |          
                    .-----'--'--'--'--'--o-----'--'--'--'---.      
                    |                       4  4  4  4  4   |      
                    |     6  5  4  3  2  1  4  3  2  1  0   |      
                ENT2| 7                                   39|TGTVCC
              ENEPWR| 8                  G  V             38|EPT22 
                BUF0| 9                  n  c             37|ETB12 
                BUF2|10                  d  c             36|EPT21 
                ETB4|11                                   35|ECTL16
                Gnd |12            MACH-210               34| Gnd  
              ECTL15|13                                   33|ECTL13
             EPSGN16|14             V  G                  32|ECTL2 
             EPSGN12|15             c  n                  31|ECTL14
             EPSGN18|16             c  d                  30|ECTL17
              EPSGN4|17                                   29|ECTL18
                    |   1  1  2  2  2  2  2  2  2  2  2     |      
                    |   8  9  0  1  2  3  4  5  6  7  8     |      
                    '---.--.--.--.--------.--.--.--.--.-----'      
                        |  |  |  |        |  |  |  |  |            
                     ENT7  |  |  |        |  |  |  |  '            
                        ENT6  |  |        |  |  |  '               
                           ENT8  |        |  |  '                  
                              ENT1        |  _6_Q6                 
                                          ENT0                     
The Jedec Data is  stored in ===> Epl210.jed
The Placements are stored in ===> Epl210.plc
The Design Doc is  stored in ===> Epl210.rpt
 
%% FITR %% Error Count: 0, Warning Count: 1
%% FITR %% File Processed Successfully. - File: Epl210.pds
 
