PALASM 4 v1.5 MACH FITR - MARKET RELEASE (7-24-92)
 (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990,91,92

 
Reading User Design (TRE File)...
 
Reading Device Database ...

********************************************************************
     Mach PLD Fitter - v 1.67          MICEPack 80C186EC MACH210
********************************************************************

PAIR Analysis...

Pre-Placement & Equation Usage Checks... 
 
|> WARNING F210 - Design contains both floating & fixed placements.  





*** Timing Analysis for Signals

 Parameter   Min   Max           Signal List (Those having Max delay.)
      Tpd     1     1            EPSGN16 
      Tsu     1     1      _12_M5_REGOUT   _12_M1_REGOUT         _3_SQD0 
                           _21_M6_REGOUT   _21_M5_REGOUT   _21_M8_REGOUT 
                           _21_M4_REGOUT   _12_M8_REGOUT 
      Tco     0     1            EPSGN16 
      Tcr     1     1            _3_SQD1            ENT0         _3_SQD2 
                                    ENT1         _3_SQD3            ENT2 
                                 _3_SQD4          ECTL14 
.

 Key:
 Tpd - Combinatorial propagation delay, input to output
 Tsu - Combinatorial setup delay before clock
 Tco - clock to output (register output to combinatorial output)
 Tcr - Clock to register setup delay
.......(Register output thru combinatorial logic to reg input)
 All delay values are expressed in terms of array passes




*** Device Resource Checks

                Available        Used        Remaining
        Clocks:     2              2              0
          Pins:    38             27             11     ->    71%
     I/O Macro:    32             17             15
   Total Macro:    64             49             15
 Product Terms:   256             70             60     ->    76%
 
MACH-PLD Resource Checks OK!  



Partitioning Design into Blocks...

|> ERROR F740 - Resource violation in preplacement: (IO Pins) - Block B


*** Last Equations Placed in Blocks

Weakly -   _12_M5_REGOUT   _12_M8_REGOUT   _12_M4_REGOUT   _12_M3_REGOUT 
Assign -   _12_M2_REGOUT      _2_SPOUT13 |> INFORMATION F085 - Intermediate Error Count: 1, Warning Count: 1
|> INFORMATION F075 - Redo Partitioning with Max Packing Flag=True 

*** Last Equations Placed in Blocks

Weakly -   _12_M5_REGOUT   _12_M8_REGOUT   _12_M4_REGOUT   _12_M3_REGOUT 
Assign -   _12_M2_REGOUT 


|> INFORMATION F050 - Device Utilization.............. *: 68 %



*** Block Partitioning Results

               Array   Product     # I/O    Buried    Signal    Macros
              Inputs    Terms      Macro     Logic    Fanout    Remain
   Block-> A    13        64*        6        10        16         0
   Block-> B    14        56         7         7        10         2
   Block-> C    14        52         3        10        10         3
   Block-> D    12        24         1         5         5        10



*** Block Signal List

Blk-> A        _3_SQD9  3        _3_SQD8  3        _3_SQD7  3        _3_SQD6  3
               _3_SQD5  3        _3_SQD4  3        _3_SQD3  3        _3_SQD2  3
               _3_SQD0  3        _3_SQD1  3           ENT2  1        SPOUT10  1
                  ENT3  1           ENT4  1           ENT5  1           ENT9  1

Blk-> B     _2_SPOUT13  1       _3_SQD15  3       _3_SQD14  3       _3_SQD13  3
              _3_SDQ12  3       _3_SQD10  3       _3_SQD11  3           ENT1  1
                  ENT8  1           ENT6  1           ENT7  1           BUF1  1
               EPSGN12  1        EPSGN16  2

Blk-> C  _21_M6_REGOUT  2  _21_M5_REGOUT  2  _21_M8_REGOUT  2  _21_M4_REGOUT  2
         _21_M3_REGOUT  2  _21_M2_REGOUT  2  _21_M1_REGOUT  2     _10_M14_QH  2
         _12_M6_REGOUT  2  _12_M1_REGOUT  2           ENT0  1         ECTL14  2
               SPOUT14  1

Blk-> D  _12_M2_REGOUT  3  _12_M3_REGOUT  3  _12_M4_REGOUT  3  _12_M8_REGOUT  3
         _12_M5_REGOUT  3        SPOUT15  1



*** Block Input List

Blk-> A         ECTL13  1         ECTL16 10        _3_SQD0  1        _3_SQD1  1
               _3_SQD2  2        _3_SQD3  2        _3_SQD4  2        _3_SQD5  2
               _3_SQD6  1        _3_SQD7  1        _3_SQD8  1        _3_SQD9  1
              _3_SQD10  1

Singular:         ECTL13{        _3_SQD0}        _3_SQD0{        _3_SQD1}
                 _3_SQD1{        _3_SQD2}        _3_SQD6{        _3_SQD7}
                 _3_SQD7{        _3_SQD8}        _3_SQD8{        _3_SQD9}
                 _3_SQD9{           ENT9}       _3_SQD10{        SPOUT10}
         

Blk-> B       NPOWERUP  1         ECTL16  6        _3_SQD1  1        _3_SQD6  1
               _3_SQD7  1        _3_SQD8  1        _3_SQD9  1       _3_SQD10  1
              _3_SQD11  2       _3_SDQ12  2       _3_SQD13  2       _3_SQD14  1
              _3_SQD15  0     _2_SPOUT13  1

Singular:       NPOWERUP{        EPSGN16}        _3_SQD1{           ENT1}
                 _3_SQD6{           ENT6}        _3_SQD7{           ENT7}
                 _3_SQD8{           ENT8}        _3_SQD9{       _3_SQD10}
                _3_SQD10{       _3_SQD11}       _3_SQD14{       _3_SQD15}
              _2_SPOUT13{        EPSGN16}


Blk-> C           ETB4  1         ECTL16 11        _3_SQD0  1       _3_SQD14  1
         _12_M5_REGOUT  1  _12_M6_REGOUT  1     _10_M14_QH  1  _21_M1_REGOUT  1
         _21_M2_REGOUT  1  _21_M3_REGOUT  1  _21_M4_REGOUT  1  _21_M8_REGOUT  1
         _21_M5_REGOUT  1  _21_M6_REGOUT  1

Singular:           ETB4{  _12_M1_REGOUT}        _3_SQD0{           ENT0}
                _3_SQD14{        SPOUT14}  _12_M5_REGOUT{  _12_M6_REGOUT}
           _12_M6_REGOUT{     _10_M14_QH}     _10_M14_QH{  _21_M1_REGOUT}
           _21_M1_REGOUT{  _21_M2_REGOUT}  _21_M2_REGOUT{  _21_M3_REGOUT}
           _21_M3_REGOUT{  _21_M4_REGOUT}  _21_M4_REGOUT{  _21_M8_REGOUT}
           _21_M8_REGOUT{  _21_M5_REGOUT}  _21_M5_REGOUT{  _21_M6_REGOUT}
           _21_M6_REGOUT{         ECTL14}


Blk-> D           SINF  1         ECTL16  5          EPT21  1          ETB12  1
                  SINC  1         TGTVCC  1       _3_SQD15  1  _12_M1_REGOUT  1
         _12_M2_REGOUT  1  _12_M3_REGOUT  1  _12_M4_REGOUT  1  _12_M8_REGOUT  1
       

Singular:           SINF{  _12_M5_REGOUT}          EPT21{  _12_M2_REGOUT}
                   ETB12{  _12_M4_REGOUT}           SINC{  _12_M3_REGOUT}
                  TGTVCC{  _12_M8_REGOUT}       _3_SQD15{        SPOUT15}
           _12_M1_REGOUT{  _12_M2_REGOUT}  _12_M2_REGOUT{  _12_M3_REGOUT}
           _12_M3_REGOUT{  _12_M4_REGOUT}  _12_M4_REGOUT{  _12_M8_REGOUT}
           _12_M8_REGOUT{  _12_M5_REGOUT}


|> INFORMATION F070 - Multiple Assignment Mode - Repeat Count: 4
Assigning Resources...


Flags Used:             Unplace=False        Max Packing=True 
Flags Used:        Expand Small=False         Expand All=False



*** Macro Block A

           ENT9 (A  0)
           ENT5 (A  2)
           ENT4 (A  4)
           ENT3 (A  6)
           ENT2 (A  8)
        SPOUT10 (A 12)

 Buried Logic>         _3_SQD0         _3_SQD1         _3_SQD2         _3_SQD3
                       _3_SQD4         _3_SQD5         _3_SQD6         _3_SQD7
                       _3_SQD8         _3_SQD9
      Targets>   1(na)   3(na)   5(na)   7(na)   9(na)  10( 7)  11(na)  13(na)
                14( 9)  15(na)

        _3_SQD0 (A  1) -> (A  2) (C  2)
        _3_SQD1 (A  3) -> (A  4) (B  4)
        _3_SQD2 (A  5) -> (A  6)
        _3_SQD3 (A  7) -> (A  8)
        _3_SQD4 (A  9) -> (A  3)
        _3_SQD5 (A 10) -> (A 14)
        _3_SQD6 (A 11) -> (A  5) (B  5)
        _3_SQD7 (A 13) -> (A  7) (B  7)
        _3_SQD8 (A 14) -> (A  1) (B  1)
        _3_SQD9 (A 15) -> (A  9) (B  9)



*** Macro Block B

        EPSGN16 (B 14)
           ENT1 (B  0)
           ENT8 (B  2)
           ENT6 (B  4)
           ENT7 (B  6)
           BUF1 (B 10)
        EPSGN12 (B 12)

 Buried Logic>        _3_SQD10        _3_SQD11        _3_SDQ12        _3_SQD13
                      _3_SQD14        _3_SQD15      _2_SPOUT13
      Targets>   1(na)   3(na)   5(na)   7(na)   8(17)   9(na)  11(na)  13(na)
                15(na)

     * Retry Mapping
       _3_SQD10 (B  3) -> (A 11) (B 11)
       _3_SQD11 (B  5) -> (B 16)
       _3_SDQ12 (B  7) -> (B  0)
       _3_SQD13 (B  8) -> (B  3)
       _3_SQD14 (B  9) -> (B  6) (C  6)
       _3_SQD15 (B 11) -> (B  8) (D  8)
     _2_SPOUT13 (B 15) -> (B 17)



*** Macro Block C

           ENT0 (C  0)
        SPOUT14 (C  2)
         ECTL14 (C 14)

 Buried Logic>   _21_M1_REGOUT   _12_M1_REGOUT   _21_M2_REGOUT   _21_M3_REGOUT
                 _21_M4_REGOUT   _21_M5_REGOUT   _21_M6_REGOUT   _12_M6_REGOUT
                 _21_M8_REGOUT      _10_M14_QH
      Targets>   1(na)   3(na)   4(26)   5(na)   6(27)   7(na)   8(28)   9(na)
                10(29)  11(na)  12(30)  13(na)  15(na)

  _21_M1_REGOUT (C  1) -> (C  8)
  _12_M1_REGOUT (C  3) -> (D 10)
  _21_M2_REGOUT (C  4) -> (C  0)
  _21_M3_REGOUT (C  5) -> (C  1)
  _21_M4_REGOUT (C  6) -> (C 13)
  _21_M5_REGOUT (C  7) -> (C  3)
  _21_M6_REGOUT (C  8) -> (C 16)
  _12_M6_REGOUT (C  9) -> (C  9)
  _21_M8_REGOUT (C 10) -> (C  7)
     _10_M14_QH (C 11) -> (C 19)



*** Macro Block D

        SPOUT15 (D  2)

 Buried Logic>   _12_M2_REGOUT   _12_M3_REGOUT   _12_M4_REGOUT   _12_M5_REGOUT
                 _12_M8_REGOUT
      Targets>   0(43)   1(na)   3(na)   4(41)   5(na)   6(40)   7(na)   8(39)
                 9(na)  10(38)  11(na)  12(37)  13(na)  14(36)  15(na)

     * Retry Mapping
  _12_M2_REGOUT (D  1) -> (D  0)
  _12_M3_REGOUT (D  3) -> (D 12)
  _12_M4_REGOUT (D  4) -> (D  3)
  _12_M5_REGOUT (D  5) -> (C  4)
  _12_M8_REGOUT (D 15) -> (D  7)



*** Macro Block Inputs

           SINF (I  0) -> (D  2)
           ETB4 (I  1)?
         ECTL13 (I  4)?
         ECTL16 (I  5) -> (A 13) (B 13) (C  5) (D  5)
           ETB4 (I  1) ->   Blocked -> Reshuffling SwMtrx
  _21_M2_REGOUT -> (C 18)    Moved.
           ETB4 -> (C  0)
         ECTL13 (I  4) ->   Blocked -> Reshuffling SwMtrx
        _3_SQD1 -> (A 16)    Moved.
         ECTL13 -> (A  4)

         TGTVCC (D  8) -> (D 11)
       NPOWERUP (B  8) -> (B 21)
           SINC (D 10)?
          ETB12 (D 12) -> (D  4)
          EPT21 (D 14) -> (D 14)
           SINC (D 10) ->   Blocked -> Reshuffling SwMtrx
  _12_M4_REGOUT -> (D 18)    Moved.
           SINC -> (D  3)





Wiring Completion:  100% -> (  0 nc)

|> INFORMATION F058 - Total Block Fanout (All Signals) *: 53 


*** Signals - Tabular Information

          Signal   #   P/N #   (Loc)      Type     Logic  # PT    Blocks
           ENT9    1     2      A  0     i/o pin    d-ff     1    .....
           ENT5    2     3      A  2     i/o pin    d-ff     1    .....
           ENT4    3     4      A  4     i/o pin    d-ff     1    .....
           ENT3    4     5      A  6     i/o pin    d-ff     1    .....
       _2_M23_I    5    10      A  8    out pair    d-ff     1    .....
        SPOUT10    6     8      A 12     i/o pin    d-ff     1    .....
           SINF    7    10      I  0       input       .     .    ....D
           ETB4    8    11      I  1       input       .     .    ...C.
         ECTL15    9    13      I  2   clock pin       .     .    .....
        EPSGN16   10    14      B 14     i/o pin    comb     1    .....
        EPSGN12   11    15      B 12     i/o pin    d-ff     1    .....
           BUF1   12    16      B 10     i/o pin    d-ff     1    .....
       NPOWERUP   13    17      B  8       input       .     .    ..B..
           ENT7   14    18      B  6     i/o pin    d-ff     1    .....
           ENT6   15    19      B  4     i/o pin    d-ff     1    .....
           ENT8   16    20      B  2     i/o pin    d-ff     1    .....
       _2_M22_I   17    18      B  0    out pair    d-ff     1    .....
       _2_M21_I   18    34      C  0    out pair    d-ff     1    .....
        SPOUT14   19    25      C  2     i/o pin    d-ff     1    .....
         ECTL14   20    31      C 14     i/o pin    d-ff     1    .....
         ECTL13   21    33      I  4       input       .     .    .A...
         ECTL16   22    35      I  5   clock pin       .     .    .ABCD
          EPT21   23    36      D 14       input       .     .    ....D
          ETB12   24    37      D 12       input       .     .    ....D
           SINC   25    38      D 10       input       .     .    ....D
         TGTVCC   26    39      D  8       input       .     .    ....D
        SPOUT15   27    42      D  2     i/o pin    d-ff     1    .....
           ENT2   28     6      A  8     i/o pin    d-ff     1    .....
           ENT1   29    21      B  0     i/o pin    d-ff     1    .....
           ENT0   30    24      C  0     i/o pin    d-ff     1    .....
        _3_SQD0   31     3      A  1      buried    d-ff     2    .A.C.
        _3_SQD1   32     5      A  3      buried    d-ff     2    .AB..
        _3_SQD2   33     7      A  5      buried    d-ff     2    .A...
        _3_SQD3   34     9      A  7      buried    d-ff     2    .A...
        _3_SQD4   35    11      A  9      buried    d-ff     2    .A...
        _3_SQD5   36    12      A 10      buried    d-ff     2    .A...
        _3_SQD6   37    13      A 11      buried    d-ff     2    .AB..
        _3_SQD7   38    15      A 13      buried    d-ff     2    .AB..
        _3_SQD8   39    16      A 14      buried    d-ff     2    .AB..
        _3_SQD9   40    17      A 15      buried    d-ff     2    .AB..
       _3_SQD10   41    21      B  3      buried    d-ff     2    .AB..
       _3_SQD11   42    23      B  5      buried    d-ff     2    ..B..
       _3_SDQ12   43    25      B  7      buried    d-ff     2    ..B..
       _3_SQD13   44    26      B  8      buried    d-ff     2    ..B..
       _3_SQD14   45    27      B  9      buried    d-ff     2    ..BC.
       _3_SQD15   46    29      B 11      buried    d-ff     2    ..B.D
     _2_SPOUT13   47    33      B 15      buried    d-ff     1    ..B..
  _12_M1_REGOUT   48    37      C  3      buried    d-ff     1    ....D
  _12_M2_REGOUT   49    51      D  1      buried    d-ff     2    ....D
  _12_M3_REGOUT   50    53      D  3      buried    d-ff     2    ....D
  _12_M4_REGOUT   51    54      D  4      buried    d-ff     2    ....D
  _12_M8_REGOUT   52    65      D 15      buried    d-ff     2    ....D
  _12_M5_REGOUT   53    55      D  5      buried    d-ff     2    ...C.
  _12_M6_REGOUT   54    43      C  9      buried    d-ff     1    ...C.
     _10_M14_QH   55    45      C 11      buried    d-ff     1    ...C.
  _21_M1_REGOUT   56    35      C  1      buried    d-ff     1    ...C.
  _21_M2_REGOUT   57    38      C  4      buried    d-ff     1    ...C.
  _21_M3_REGOUT   58    39      C  5      buried    d-ff     1    ...C.
  _21_M4_REGOUT   59    40      C  6      buried    d-ff     1    ...C.
  _21_M8_REGOUT   60    44      C 10      buried    d-ff     1    ...C.
  _21_M5_REGOUT   61    41      C  7      buried    d-ff     1    ...C.
  _21_M6_REGOUT   62    42      C  8      buried    d-ff     1    ...C.
.

 Key:
 P/N # - Pin/Node Number
 .?. - Signal Unplaced
 (Loc) - Macrocell Location (Block & Cell)
 # PT - Number of used product terms in logic
 Blocks- Device blocks driven by signal
 comb - Combinatorial logic function
 d-ff - D-Type Flip-flop
 t-ff - T-Type Flip-flop
 Note: Registered input storage equations (MACH-2xx family)
 ..... are realized with 0 array product terms.


*** Signals - Equations Where Used

   Signal Source                   Fanout List

           SINF:  _12_M5_REGOUT 
               {D}
           ETB4:  _12_M1_REGOUT 
               {C}
       NPOWERUP:        EPSGN16 
               {B}
         ECTL13:        _3_SQD0 
               {A}
         ECTL16:  _21_M6_REGOUT   _21_M5_REGOUT   _21_M8_REGOUT   _21_M4_REGOUT 
               :  _21_M3_REGOUT   _21_M2_REGOUT   _21_M1_REGOUT      _10_M14_QH 
               :  _12_M6_REGOUT   _12_M5_REGOUT   _12_M8_REGOUT   _12_M4_REGOUT 
               :  _12_M3_REGOUT   _12_M2_REGOUT   _12_M1_REGOUT        _3_SQD15 
               :       _3_SQD14        _3_SQD13        _3_SDQ12        _3_SQD11 
               :       _3_SQD10         _3_SQD9         _3_SQD8         _3_SQD7 
               :        _3_SQD6         _3_SQD5         _3_SQD4         _3_SQD3 
               :        _3_SQD2         _3_SQD1         _3_SQD0          ECTL14 
               {CCCC CCCC CDDD DDCB BBBB BAAA AAAA AAAC}

          EPT21:  _12_M2_REGOUT 
               {D}
          ETB12:  _12_M4_REGOUT 
               {D}
           SINC:  _12_M3_REGOUT 
               {D}
         TGTVCC:  _12_M8_REGOUT 
               {D}
        _3_SQD0:        _3_SQD1         _3_SQD0            ENT0            ENT0 
               {AACC}
        _3_SQD1:        _3_SQD2         _3_SQD1            ENT1            ENT1 
               {AABB}
        _3_SQD2:        _3_SQD3         _3_SQD2            ENT2            ENT2 
               {AAAA}
        _3_SQD3:        _3_SQD4         _3_SQD3            ENT3 
               {AAA}
        _3_SQD4:        _3_SQD5         _3_SQD4            ENT4 
               {AAA}
        _3_SQD5:        _3_SQD6         _3_SQD5            ENT5 
               {AAA}
        _3_SQD6:        _3_SQD7         _3_SQD6            ENT6 
               {AAB}
        _3_SQD7:        _3_SQD8         _3_SQD7            ENT7 
               {AAB}
        _3_SQD8:        _3_SQD9         _3_SQD8            ENT8 
               {AAB}
        _3_SQD9:       _3_SQD10         _3_SQD9            ENT9 
               {BAA}
       _3_SQD10:       _3_SQD11        _3_SQD10         SPOUT10 
               {BBA}
       _3_SQD11:       _3_SDQ12        _3_SQD11         EPSGN12 
               {BBB}
       _3_SDQ12:       _3_SQD13        _3_SDQ12            BUF1 
               {BBB}
       _3_SQD13:     _2_SPOUT13        _3_SQD14        _3_SQD13 
               {BBB}
       _3_SQD14:       _3_SQD15        _3_SQD14         SPOUT14 
               {BBC}
       _3_SQD15:       _3_SQD15         SPOUT15 
               {BD}
     _2_SPOUT13:        EPSGN16 
               {B}
  _12_M1_REGOUT:  _12_M2_REGOUT 
               {D}
  _12_M2_REGOUT:  _12_M3_REGOUT 
               {D}
  _12_M3_REGOUT:  _12_M4_REGOUT 
               {D}
  _12_M4_REGOUT:  _12_M8_REGOUT 
               {D}
  _12_M8_REGOUT:  _12_M5_REGOUT 
               {D}
  _12_M5_REGOUT:  _12_M6_REGOUT 
               {C}
  _12_M6_REGOUT:     _10_M14_QH 
               {C}
     _10_M14_QH:  _21_M1_REGOUT 
               {C}
  _21_M1_REGOUT:  _21_M2_REGOUT 
               {C}
  _21_M2_REGOUT:  _21_M3_REGOUT 
               {C}
  _21_M3_REGOUT:  _21_M4_REGOUT 
               {C}
  _21_M4_REGOUT:  _21_M8_REGOUT 
               {C}
  _21_M8_REGOUT:  _21_M5_REGOUT 
               {C}
  _21_M5_REGOUT:  _21_M6_REGOUT 
               {C}
  _21_M6_REGOUT:         ECTL14 
               {C}



*** Outputs with no feedback

             ENT9            ENT5            ENT4            ENT3         SPOUT10 
          EPSGN16         EPSGN12            BUF1            ENT7            ENT6 
             ENT8         SPOUT14          ECTL14         SPOUT15            ENT2 
             ENT1            ENT0 


*** Feedback Map - MICEPack 80C186EC MACH210

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
         | 0|          | 0|     |21|             _3_SDQ12  0|     |21| NPOWERU
         | 1|  _3_SQD8 : 1|     |20|             _3_SQD8 : 1|     |20|        
         | 2|  _3_SQD0 : 2|     |19|                     | 2|     |19|        
         | 3|  _3_SQD4 : 3|     |18|             _3_SQD13  3|     |18|        
         | 4|   ECTL13 : 4|     |17|             _3_SQD1 : 4|     |17| _2_SPOU
         | 5|  _3_SQD6 : 5|     |16| _3_SQD1     _3_SQD6 : 5|     |16| _3_SQD1
         '--'  _3_SQD2 : 6|     |15|             _3_SQD14  6|     |15|        
               _3_SQD7 : 7|     |14: _3_SQD5     _3_SQD7 : 7|     |14|        
               _3_SQD3 : 8|     |13: ECTL16      _3_SQD15  8|     |13: ECTL16 
               _3_SQD9 : 9|     |12|             _3_SQD9 : 9|     |12|        
K:  * Used             |10|     |11: _3_SQD1             |10|     |11: _3_SQD1
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A         ETB4 : 0|     |21|             _12_M2_R  0|     |21|        
    0 RegIn    _21_M3_R  1|     |20|                     | 1|     |20|        
               _3_SQD0 : 2|     |19| _10_M14        SINF : 2|     |19|        
               _21_M5_R  3|     |18| _21_M2_        SINC : 3|     |18| _12_M4_
               _12_M5_R  4|     |17|               ETB12 : 4|     |17|        
                ECTL16 : 5|     |16| _21_M6_      ECTL16 : 5|     |16|        
               _3_SQD14  6|     |15|                     | 6|     |15|        
               _21_M8_R  7|     |14|             _12_M8_R  7|     |14: EPT21  
               _21_M1_R  8|     |13: _21_M4_     _3_SQD15  8|     |13|        
               _12_M6_R  9|     |12|                     | 9|     |12: _12_M3_
                       |10|     |11|             _12_M1_R 10|     |11: TGTVCC 
                       '--+-u--u+--'                     '--+-u--u+--'        



*** Logic Map - MICEPack 80C186EC MACH210

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
     SINF| 0|     ENT9 | 0| 1  #|21|               /ENT1 | 0| 1  #|21|        
     ETB4| 1|  _3_SQD0 | 1| 2  #|20|                     | 1| .  #|20|        
   ECTL15| 2|     ENT5 | 2| 1  #|19|                ENT8 | 2| 1  #|19|        
         | 3|  _3_SQD1 | 3| 2  #|18|             _3_SQD10  3| 2  #|18|        
   ECTL13| 4|     ENT4 | 4| 1  #|17|                ENT6 | 4| 1  #|17|        
   ECTL16| 5|  _3_SQD2 | 5| 2  #|16|             _3_SQD11  5| 2  #|16|        
         '--'     ENT3 | 6| 1  2|15| _3_SQD9        ENT7 | 6| 1  1|15| _2_SPOU
               _3_SQD3 | 7| 2  2|14| _3_SQD8     _3_SDQ12  7| 2  1|14| EPSGN16
                 /ENT2 | 8| 1  2|13| _3_SQD7     _3_SQD13  8| 2  .|13|        
               _3_SQD4 | 9| 2  1|12| SPOUT10     _3_SQD14  9| 2  1|12| EPSGN12
K:  * Used     _3_SQD5 |10| 2  2|11| _3_SQD6        BUF1 |10| 1  2|11| _3_SQD1
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A        /ENT0 | 0| 1  #|21|                     | 0| .  #|21|        
    0 RegIn    _21_M1_R  1| 1  #|20|             _12_M2_R  1| 2  #|20|        
               SPOUT14 | 2| 1  #|19|             SPOUT15 | 2| 1  #|19|        
               _12_M1_R  3| 1  #|18|             _12_M3_R  3| 2  #|18|        
               _21_M2_R  4| 1  #|17|             _12_M4_R  4| 2  #|17|        
               _21_M3_R  5| 1  #|16|             _12_M5_R  5| 2  #|16|        
               _21_M4_R  6| 1  .|15|                     | 6| .  2|15| _12_M8_
               _21_M5_R  7| 1  1|14| ECTL14              | 7| .  .|14|        
               _21_M6_R  8| 1  .|13|                     | 8| .  .|13|        
               _12_M6_R  9| 1  .|12|                     | 9| .  .|12|        
               _21_M8_R 10| 1  1|11| _10_M14             |10| .  .|11|        
                       '--+-u--u+--'                     '--+-u--u+--'        


*** Pin Map - MICEPack 80C186EC MACH210
                                                                   
                                                                   
                                                                   
                                                                   
                                   ENT9                            
                                ENT5  |        .                   
                             ENT4  |  |        |  SPOUT15          
                          ENT3  |  |  |        |  |  .             
                      /ENT2  |  |  |  |        |  |  |  .          
                          |  |  |  |  |        |  |  |  |          
                    .-----'--'--'--'--'--o-----'--'--'--'---.      
                    |                       4  4  4  4  4   |      
                    |     6  5  4  3  2  1  4  3  2  1  0   |      
                    | 7                                   39|TGTVCC
             SPOUT10| 8                  G  V             38|SINC  
                    | 9                  n  c             37|ETB12 
                SINF|10                  d  c             36|EPT21 
                ETB4|11                                   35|ECTL16
                Gnd |12            MACH-210               34| Gnd  
              ECTL15|13                                   33|ECTL13
             EPSGN16|14             V  G                  32|      
             EPSGN12|15             c  n                  31|ECTL14
                BUF1|16             c  d                  30|      
            NPOWERUP|17                                   29|      
                    |   1  1  2  2  2  2  2  2  2  2  2     |      
                    |   8  9  0  1  2  3  4  5  6  7  8     |      
                    '---.--.--.--.--------.--.--.--.--.-----'      
                        |  |  |  |        |  |  |  |  |            
                     ENT7  |  |  |        |  |  |  |  '            
                        ENT6  |  |        |  |  |  '               
                           ENT8  |        |  |  '                  
                             /ENT1        |  SPOUT14               
                                          /ENT0                    
The Jedec Data is  stored in ===> ec210.jed
The Placements are stored in ===> ec210.plc
The Design Doc is  stored in ===> ec210.rpt
 
%% FITR %% Error Count: 0, Warning Count: 1
%% FITR %% File Processed Successfully. - File: ec210.pds
 
