Project Information                           c:\orcad4.04\orcad\ovrm\ovrm.rpt

MAX+plus II Compiler Report File
Version 3.30 9/15/93
Compiled: 03/09/94 14:34:33



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

OVRM      EPM7064LC84-15   32       25       8      47      3           73 %

User Pins:                 32       25       8  



Project Information                           c:\orcad4.04\orcad\ovrm\ovrm.rpt

** PROJECT COMPILATION MESSAGES **

Design Doctor Warning: Flipflop 'NDMA_1' receives data that is synchronized by another Clock at flipflop 'ENIDCODE_7'
Design Doctor Warning: Multi-level logic drives Reset node (ID 'N00003')
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'EA20' = 0 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'N1MVLD' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'EA20' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'N1MVLD' = 1, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'EA20' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'EA19' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 0, 'EA18' = 0, 'N1MVLD' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA18' = 0, 'EA19' = 0, 'EA20' = 0, 'N1MVLD' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA18' = 0, 'EA19' = 0, 'N1MVLD' = 1, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA18' = 0, 'EA19' = 0, 'N1MVLD' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K0' contains a static 0 hazard when 'EA16' = 0, 'EA18' = 0, 'N1MVLD' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'EA19' = 0, 'EA20' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'EA19' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'EA19' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'N1MVLD' = 1, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'EA19' = 0, 'EA20' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'EA19' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'EA19' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'N1MVLD' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA18' = 1, 'EA19' = 0, 'EA20' = 0, 'N1MVLD' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA18' = 1, 'EA19' = 0, 'N1MVLD' = 1, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA18' = 1, 'EA19' = 0, 'N1MVLD' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN512K1' contains a static 0 hazard when 'EA16' = 1, 'EA18' = 1, 'N1MVLD' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN2M1' contains a static 0 hazard when <see condition list> and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Info: Conditions -- 'EA16' = 1, 'EA17' = 0, 'EA18' = 1, 'EA18' = 1, 'EA19' = 0, 'EA20' = 1, 'EA20' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 0, 'N2MVLD1' = 0
Design Doctor Warning: Logic that drives primitive 'NEN2M3' contains a static 0 hazard when <see condition list> and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Info: Conditions -- 'EA16' = 1, 'EA17' = 1, 'EA18' = 1, 'EA18' = 1, 'EA19' = 1, 'EA20' = 1, 'EA20' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 0, 'N2MVLD1' = 0
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'EA20' = 0, 'N1MVLD' = 0 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'EA20' = 0, 'N1MVLD' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'EA20' = 0, 'N1MVLD' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M0' contains a static 0 hazard when 'EA16' = 0, 'EA17' = 1, 'EA18' = 0, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 1, 'EA18' = 1, 'EA19' = 1, 'EA20' = 0, 'N1MVLD' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 1, 'EA18' = 1, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 1, 'EA18' = 1, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 1, 'EA18' = 1, 'EA19' = 1, 'EA20' = 0, 'N1MVLD' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 1, 'EA18' = 1, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD0' = 1, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN1M1' contains a static 0 hazard when 'EA16' = 1, 'EA17' = 1, 'EA18' = 1, 'EA19' = 1, 'N1MVLD' = 0, 'N2MVLD1' = 1 and primitive 'NMAX8M' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN0' = 0, 'NENEM' = 0, 'NERD' = 0, 'NBPBUS0' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NRDONLY' = 1, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN0' = 0, 'NENEM' = 0, 'NBPBUS0' = 0
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN0' = 0, 'NENEM' = 0, 'NBPBUS0' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN0' = 0, 'NENEM' = 0, 'NBPBUS0' = 0
Info: Conditions -- 'DISRDONLY_1' = 1
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN0' = 0, 'NENEM' = 0, 'NERD' = 0, 'NBPBUS0' = 0, 'NDMA_1' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NRDONLY' = 1, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN0' = 0, 'NENEM' = 0, 'NBPBUS0' = 0, 'NDMA_1' = 0
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN0' = 0, 'NENEM' = 0, 'NBPBUS0' = 0, 'NDMA_1' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE0' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN0' = 0, 'NENEM' = 0, 'NBPBUS0' = 0, 'NDMA_1' = 0, 'DISRDONLY_1' = 1
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN1' = 0, 'NENEM' = 0, 'NERD' = 0, 'NBPBUS1' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NRDONLY' = 1, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN1' = 0, 'NENEM' = 0, 'NBPBUS1' = 0
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN1' = 0, 'NENEM' = 0, 'NBPBUS1' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NEMVALID' = 0, 'NMBEN1' = 0, 'NENEM' = 0, 'NBPBUS1' = 0
Info: Conditions -- 'DISRDONLY_1' = 1
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN1' = 0, 'NENEM' = 0, 'NERD' = 0, 'NBPBUS1' = 0, 'NDMA_1' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NRDONLY' = 1, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN1' = 0, 'NENEM' = 0, 'NBPBUS1' = 0, 'NDMA_1' = 0
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN1' = 0, 'NENEM' = 0, 'NBPBUS1' = 0, 'NDMA_1' = 0
Info: Conditions -- '|7474:U148|1Q' = 0
Design Doctor Warning: Logic that drives primitive 'NWE1' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'CPS8' = 0, 'NEWE' = 0, 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN1' = 0, 'NENEM' = 0, 'NBPBUS1' = 0, 'NDMA_1' = 0, 'DISRDONLY_1' = 1
Design Doctor Warning: Logic that drives primitive 'NEMRD0' contains a static 1 hazard when 'CPS9' = 1, 'NERD' = 1 and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEMRD1' contains a static 1 hazard when 'CPS9' = 1, 'NERD' = 1 and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'NEN8B' contains a static 0 hazard when <see condition list> and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Conditions -- 'NMEMRQ' = 0, 'EMUSPACE' = 1, 'NMBEN1' = 0, 'NENEM' = 0, 'NBPBUS0' = 1, 'NBPBUS1' = 0, 'SEL8' = 1, 'NSTROBE' = 0
Info: Conditions -- '|7474:U148|1Q' = 1
Design Doctor Warning: Logic that drives primitive 'DIR' contains a static 1 hazard when 'CPS9' = 0, 'NERD' = 0 and primitive 'DIAG_1' changes -- hazard found before logic synthesis
Info: Design Doctor issued 67 warning message(s) with EPLD Rules
Info: Trying to find new partition/fit after discarding assignments by request of the user


Project Information                           c:\orcad4.04\orcad\ovrm\ovrm.rpt

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

OVRM@37          OVRM@57          CEMA17
OVRM@18          OVRM@37          CPD0
OVRM@17          OVRM@39          CPD1
OVRM@16          OVRM@56          CPD2
OVRM@15          OVRM@55          CPD3
OVRM@14          OVRM@54          CPD4
OVRM@12          OVRM@41          CPD5
OVRM@11          OVRM@40          CPD6
OVRM@10          OVRM@68          CPD7
OVRM@22          OVRM@18          CPS8
OVRM@21          OVRM@22          CPS9
OVRM@8           OVRM@74          DIR
OVRM@29          OVRM@63          EA16
OVRM@36          OVRM@46          EA17
OVRM@34          OVRM@25          EA18
OVRM@25          OVRM@27          EA19
OVRM@30          OVRM@65          EA20
OVRM@46          OVRM@4           EMUSPACE
OVRM@68          OVRM@36          INHIMAP
OVRM@70          OVRM@34          MAPCOVSEL
OVRM@6           OVRM@79          MD0
OVRM@5           OVRM@77          MD8
OVRM@55          OVRM@23          NBPBUS0
OVRM@56          OVRM@11          NBPBUS1
OVRM@2           OVRM@84          NCOVSELG
OVRM@4           OVRM@21          NCPCS8
OVRM@64          OVRM@76          NEMRD0
OVRM@65          OVRM@73          NEMRD1
OVRM@44          OVRM@16          NEMVALID
OVRM@62          OVRM@8           NENEM
OVRM@57          OVRM@71          NENEMBH
OVRM@61          OVRM@70          NENEMBL
OVRM@67          OVRM@28          NENMAP
OVRM@31          OVRM@52          NEN1M0
OVRM@23          OVRM@45          NEN1M1
OVRM@28          OVRM@58          NEN2M0
OVRM@35          OVRM@62          NEN2M1
OVRM@27          OVRM@61          NEN2M2
OVRM@33          OVRM@60          NEN2M3
OVRM@52          OVRM@69          NEN8B
OVRM@41          OVRM@50          NEN512K0
OVRM@39          OVRM@48          NEN512K1
OVRM@60          OVRM@6           NERD
OVRM@50          OVRM@51          NEWE
OVRM@73          OVRM@30          NGUARD
OVRM@80          OVRM@12          NMAX8M
OVRM@51          OVRM@31          NMBEN0
OVRM@54          OVRM@49          NMBEN1
OVRM@20          OVRM@75          NMCS2L
OVRM@48          OVRM@83          NMEMRQ
OVRM@84          OVRM@2           NRDOEG
OVRM@71          OVRM@35          NRDOEOUT
OVRM@63          OVRM@10          NRDONLY
OVRM@9           OVRM@20          NRESET
OVRM@58          OVRM@15          NSTROBE
OVRM@75          OVRM@33          NVIOLBRK
OVRM@45          OVRM@64          NWE0
OVRM@49          OVRM@67          NWE1
OVRM@76          OVRM@5           N1MVLD
OVRM@77          OVRM@1           N2MVLD0
OVRM@79          OVRM@14          N2MVLD1
OVRM@74          OVRM@29          N512KVLD
OVRM@69          OVRM@24          RESERVE
OVRM@81          OVRM@17          SEL8


Project Information                           c:\orcad4.04\orcad\ovrm\ovrm.rpt

** FILE HIERARCHY **



|7474:U163|
|7474:U159|
|7474:U149|
|7474:U148|
|7474:U147|
|7474:U57|


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

***** Logic for device 'OVRM' compiled without errors.




Device: EPM7064LC84-15
Turbo: ON
Security: OFF
                                                                               
                                                                               
                                     E           N        R  R                 
                N  N                 M        N  C        E  E                 
                B  R              N  U     N  2  O  N     S  S           N  N  
                P  D     N        1  S     R  M  V  M     E  E           E  M  
                B  O  C  E     N  M  P     D  V  S  E     R  R           M  C  
                U  N  P  N  G  E  V  A  V  O  L  E  M  G  V  V  M  V  M  R  S  
                S  L  A  E  N  R  L  C  C  E  D  L  R  N  E  E  D  C  D  D  2  
                1  Y  4  M  D  D  D  E  C  G  0  G  Q  D  D  D  0  C  8  0  L  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    NMAX8M | 12                                                              74 | DIR 
       VCC | 13                                                              73 | NEMRD1 
   N2MVLD1 | 14                                                              72 | GND 
   NSTROBE | 15                                                              71 | NENEMBH 
  NEMVALID | 16                                                              70 | NENEMBL 
      SEL8 | 17                                                              69 | NEN8B 
      CPS8 | 18                                                              68 | CPD7 
       GND | 19                                                              67 | NWE1 
    NRESET | 20                                                              66 | VCC 
    NCPCS8 | 21                                                              65 | EA20 
      CPS9 | 22                        EPM7064LC84-15                        64 | NWE0 
   NBPBUS0 | 23                                                              63 | EA16 
   RESERVE | 24                                                              62 | NEN2M1 
      EA18 | 25                                                              61 | NEN2M2 
       VCC | 26                                                              60 | NEN2M3 
      EA19 | 27                                                              59 | GND 
    NENMAP | 28                                                              58 | NEN2M0 
  N512KVLD | 29                                                              57 | CEMA17 
    NGUARD | 30                                                              56 | CPD2 
    NMBEN0 | 31                                                              55 | CPD3 
       GND | 32                                                              54 | CPD4 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                N  M  N  I  C  V  C  C  C  G  V  R  N  E  G  N  N  N  N  N  V  
                V  A  R  N  P  C  P  P  P  N  C  E  E  A  N  E  M  E  E  E  C  
                I  P  D  H  D  C  D  D  D  D  C  S  N  1  D  N  B  N  W  N  C  
                O  C  O  I  0     1  6  5        E  1  7     5  E  5  E  1     
                L  O  E  M                       R  M        1  N  1     M     
                B  V  O  A                       V  1        2  1  2     0     
                R  S  U  P                       E           K     K           
                K  E  T                          D           1     0           
                   L                                                           
                                                                               


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)  16/16(100%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32    16/16(100%)  16/16(100%)   2/16( 12%)  20/36( 55%) 
C:    LC33 - LC48    16/16(100%)  15/16( 93%)   4/16( 25%)  11/36( 30%) 
D:    LC49 - LC64    15/16( 93%)  14/16( 87%)   3/16( 18%)  22/36( 61%) 


Total dedicated input pins used:                 4/   4 (100%)
Total I/O pins used:                            61/  64 ( 95%)
Total logic cells used:                         47/  64 ( 73%)
Total shareable expanders used:                  3/  64 (  4%)
Total Turbo logic cells used:                   47/  64 ( 73%)
Total shareable expanders not available (n/a):   6/  64 (  9%)

Total input pins required:                      32
Total output pins required:                     25
Total bidirectional pins required:               8
Total logic cells required:                     47
Total flipflops required:                       12
Total shareable expanders in database:           3

Synthesized logic cells:                         0/  64 (  0%)



Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** INPUTS **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
   9   (12)  (A)      INPUT         0      0   0    0    0  CPA4
  37     20    B      BIDIR         0      0   0    3    2  CPD0
  39     19    B      BIDIR         0      0   0    2    1  CPD1
  56     43    C      BIDIR         0      0   0    3    0  CPD2
  55     42    C      BIDIR         0      0   0    3    0  CPD3
  54     41    C      BIDIR         0      0   0    3    0  CPD4
  41     17    B      BIDIR         0      0   0    4    1  CPD5
  40     18    B      BIDIR         0      0   0    3    0  CPD6
  68     53    D      BIDIR         0      0   0    0    0  CPD7
  18    (4)  (A)      INPUT         0      0   0    0    0  CPS8
  22    (1)  (A)      INPUT         0      0   0    0    0  CPS9
  63   (49)  (D)      INPUT         0      0   0    0    0  EA16
  46   (35)  (C)      INPUT         0      0   0    0    0  EA17
  25   (30)  (B)      INPUT         0      0   0    0    0  EA18
  27   (29)  (B)      INPUT         0      0   0    0    0  EA19
  65   (51)  (D)      INPUT         0      0   0    0    0  EA20
   4   (16)  (A)      INPUT         0      0   0    0    0  EMUSPACE
  23   (32)  (B)      INPUT         0      0   0    0    0  NBPBUS0
  11   (10)  (A)      INPUT         0      0   0    0    0  NBPBUS1
  84      -   -       INPUT         0      0   0    0    0  NCOVSELG (U155)
  21    (2)  (A)      INPUT         0      0   0    0    0  NCPCS8
  16    (6)  (A)      INPUT         0      0   0    0    0  NEMVALID
   8   (13)  (A)      INPUT         0      0   0    0    0  NENEM
   6   (14)  (A)      INPUT         0      0   0    0    0  NERD
  51   (39)  (C)      INPUT         0      0   0    0    0  NEWE
  30   (26)  (B)      INPUT         0      0   0    0    0  NGUARD
  12    (9)  (A)      INPUT         0      0   0    0    0  NMAX8M
  31   (25)  (B)      INPUT         0      0   0    0    0  NMBEN0
  49   (37)  (C)      INPUT         0      0   0    0    0  NMBEN1
  75   (59)  (D)      INPUT         0      0   0    0    0  NMCS2L
  83      -   -       INPUT         0      0   0    0    0  NMEMRQ
   2      -   -       INPUT         0      0   0    0    0  NRDOEG (U154)
  10   (11)  (A)      INPUT         0      0   0    0    0  NRDONLY
  20    (3)  (A)      INPUT         0      0   0    0    0  NRESET
  15    (7)  (A)      INPUT         0      0   0    0    0  NSTROBE
   5   (15)  (A)      INPUT         0      0   0    0    0  N1MVLD
   1      -   -       INPUT         0      0   0    0    0  N2MVLD0
  14    (8)  (A)      INPUT         0      0   0    0    0  N2MVLD1
  29   (27)  (B)      INPUT         0      0   0    0    0  N512KVLD
  17    (5)  (A)      INPUT         0      0   0    0    0  SEL8


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** OUTPUTS **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
  57     44    C     OUTPUT   t     0      0   0    2    0  CEMA17
  37     20    B        TRI   t     0      0   0    3    2  CPD0
  39     19    B        TRI   t     0      0   0    2    1  CPD1
  56     43    C        TRI   t     0      0   0    3    0  CPD2
  55     42    C        TRI   t     0      0   0    3    0  CPD3
  54     41    C        TRI   t     0      0   0    3    0  CPD4
  41     17    B        TRI   t     0      0   0    4    1  CPD5
  40     18    B        TRI   t     0      0   0    3    0  CPD6
  68     53    D        TRI   t     0      0   0    0    0  CPD7
  74     58    D     OUTPUT   t     0      0   0    2    1  DIR
  36     21    B         FF   t     1      1   0    4    1  INHIMAP (|7474:U147|:10)
  34     23    B         FF   t     1      1   0    4    1  MAPCOVSEL (|7474:U148|:9)
  79     62    D        TRI   t     0      0   0    0    0  MD0
  77     61    D        TRI   t     0      0   0    0    0  MD8
  76     60    D     OUTPUT   t     0      0   0    2    1  NEMRD0
  73     57    D     OUTPUT   t     0      0   0    2    1  NEMRD1
  71     56    D     OUTPUT   t     0      0   0    7    2  NENEMBH
  70     55    D     OUTPUT   t     0      0   0    6    2  NENEMBL
  28     28    B         FF   t     1      1   0    4    1  NENMAP (|7474:U149|:9)
  52     40    C     OUTPUT   t     1      0   1    9    0  NEN1M0
  45     34    C     OUTPUT   t     1      0   1    9    0  NEN1M1
  58     45    C     OUTPUT   t     0      0   0    9    0  NEN2M0
  62     48    C     OUTPUT   t     0      0   0    9    0  NEN2M1
  61     47    C     OUTPUT   t     0      0   0    9    0  NEN2M2
  60     46    C     OUTPUT   t     0      0   0    9    0  NEN2M3
  69     54    D     OUTPUT   t     0      0   0    8    2  NEN8B
  50     38    C     OUTPUT   t     1      0   1    9    0  NEN512K0
  48     36    C     OUTPUT   t     1      0   1    9    0  NEN512K1
  35     22    B     OUTPUT   t     0      0   0    3    1  NRDOEOUT
  33     24    B     OUTPUT   t     0      0   0    0    3  NVIOLBRK
  64     50    D     OUTPUT   t     1      0   1   10    4  NWE0
  67     52    D     OUTPUT   t     1      0   1   10    4  NWE1
  24     31    B         FF   t     1      1   0    4    1  RESERVE (|7474:U147|:9)


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** BURIED LOGIC **

                                     Shareable
                                     Expanders     Fan-In
 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  Name
 (30)    26    B       DFFE   t     1      1   0    4    2  DIAG_1 (|7474:U163|:10)
 (29)    27    B       DFFE   t     1      1   0    4    1  DISRDONLY_1 (|7474:U148|:10)
 (25)    30    B       DFFE   t     1      1   0    4    2  ENIDCODE_7 (|7474:U159|:9)
 (81)    64    D       DFFE   t     1      1   0    5    1  GUFLG_3 (|7474:U57|:10)
 (31)    25    B       DFFE   t     1      0   0    4    1  NDMA_1 (|7474:U159|:10)
 (23)    32    B       DFFE   t     1      1   0    4    1  NENVIOL_1 (|7474:U149|:10)
 (27)    29    B       DFFE   t     1      1   0    4    2  NPRVIOL_1 (|7474:U163|:9)
 (80)    63    D       DFFE   t     1      1   0    6    1  WPFLG_3 (|7474:U57|:9)
 (51)    39    C       PEXP   t     0      0   0    0    0  _LC039
 (44)    33    C       PEXP   t     0      0   0    0    0  _LC033
 (49)    37    C       PEXP   t     0      0   0    0    0  _LC037
 (46)    35    C       PEXP   t     0      0   0    0    0  _LC035
 (63)    49    D       PEXP   t     0      0   0    0    0  _LC049
 (65)    51    D       PEXP   t     0      0   0    0    0  _LC051


s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

        +------------------------------- LC20 CPD0
        | +----------------------------- LC19 CPD1
        | | +--------------------------- LC17 CPD5
        | | | +------------------------- LC18 CPD6
        | | | | +----------------------- LC26 DIAG_1
        | | | | | +--------------------- LC27 DISRDONLY_1
        | | | | | | +------------------- LC30 ENIDCODE_7
        | | | | | | | +----------------- LC21 INHIMAP
        | | | | | | | | +--------------- LC23 MAPCOVSEL
        | | | | | | | | | +------------- LC25 NDMA_1
        | | | | | | | | | | +----------- LC28 NENMAP
        | | | | | | | | | | | +--------- LC32 NENVIOL_1
        | | | | | | | | | | | | +------- LC29 NPRVIOL_1
        | | | | | | | | | | | | | +----- LC22 NRDOEOUT
        | | | | | | | | | | | | | | +--- LC24 NVIOLBRK
        | | | | | | | | | | | | | | | +- LC31 RESERVE
        | | | | | | | | | | | | | | | | 
LC      | | | | | | | | | | | | | | | | | A B C D | Name
LC20 -> - - - - - - - - - * - - - - - * | - * - - | CPD0
LC19 -> - - - - - - - * - - - - - - - - | - * - - | CPD1
LC17 -> - - - - - - - - - - - * - - - - | - * - - | CPD5
LC18 -> - - - - * - * - - - - - * - - - | - * - - | CPD6
LC30 -> * - * - - - - - - - - - - * - - | - * - - | ENIDCODE_7
LC32 -> - - - - - - - - - - - - - - * - | - * - - | NENVIOL_1

Pin
9    -> - - - - * * * * * * * * * - - * | - * - - | CPA4
18   -> - - - - * * * * * * * * * - - * | - * - * | CPS8
22   -> * * * * - - - - - - - - - * - - | - * * * | CPS9
84   -> - - - - - - - - - - - - - - - - | - - - - | NCOVSELG
21   -> * * * * * * * * * * * * * * - * | - * * - | NCPCS8
12   -> - - * - - - - - - - - - - - - - | - * * - | NMAX8M
75   -> * - * - - - - - - - - - - * - - | - * - - | NMCS2L
83   -> - - - - - - - - - - - - - - - - | - - - * | NMEMRQ
2    -> - - - - - - - - - - - - - - - - | - - - - | NRDOEG
20   -> - - - - * * * * * * * * * - - * | - * - * | NRESET
1    -> - - - - - - - - - - - - - - - - | - - * - | N2MVLD0
29   -> - - - * - - - - - - - - - - - - | - * - - | N512KVLD
LC43 -> - - - - - - - - * - - - - - - - | - * - - | CPD2
LC42 -> - - - - - * - - - - - - - - - - | - * - - | CPD3
LC41 -> - - - - - - - - - - * - - - - - | - * - - | CPD4
LC53 -> - - - - * - * - - - - - * - - - | - * - - | CPD7
LC64 -> - * - - - - - - - - - - - - * - | - * - - | GUFLG_3
LC63 -> * - - - - - - - - - - - - - * - | - * - - | WPFLG_3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

        +------------------------------- LC44 CEMA17
        | +----------------------------- LC43 CPD2
        | | +--------------------------- LC42 CPD3
        | | | +------------------------- LC41 CPD4
        | | | | +----------------------- LC40 NEN1M0
        | | | | | +--------------------- LC34 NEN1M1
        | | | | | | +------------------- LC45 NEN2M0
        | | | | | | | +----------------- LC48 NEN2M1
        | | | | | | | | +--------------- LC47 NEN2M2
        | | | | | | | | | +------------- LC46 NEN2M3
        | | | | | | | | | | +----------- LC38 NEN512K0
        | | | | | | | | | | | +--------- LC36 NEN512K1
        | | | | | | | | | | | | +------- LC39 
        | | | | | | | | | | | | | +----- LC33 
        | | | | | | | | | | | | | | +--- LC37 
        | | | | | | | | | | | | | | | +- LC35 
        | | | | | | | | | | | | | | | | 
LC      | | | | | | | | | | | | | | | | | A B C D | Name

Pin
22   -> - * * * - - - - - - - - - - - - | - * * * | CPS9
63   -> - - - - * * * * * * * * - - - - | - - * - | EA16
46   -> * - - - * * * * * * * * - - - - | - - * - | EA17
25   -> - - - - * * * * * * * * - - - - | - - * - | EA18
27   -> - - - - * * * * * * * * - - - - | - - * - | EA19
65   -> - - - - * * * * * * * * - - - - | - - * - | EA20
84   -> - - - - - - - - - - - - - - - - | - - - - | NCOVSELG
21   -> - * * * - - - - - - - - - - - - | - * * - | NCPCS8
12   -> * - - - * * * * * * * * - - - - | - * * - | NMAX8M
83   -> - - - - - - - - - - - - - - - - | - - - * | NMEMRQ
2    -> - - - - - - - - - - - - - - - - | - - - - | NRDOEG
5    -> - * - - * * * * * * * * - - - - | - - * - | N1MVLD
1    -> - - * - * * * * * * * * - - - - | - - * - | N2MVLD0
14   -> - - - * * * * * * * * * - - - - | - - * - | N2MVLD1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

        +----------------------------- LC53 CPD7
        | +--------------------------- LC58 DIR
        | | +------------------------- LC64 GUFLG_3
        | | | +----------------------- LC62 MD0
        | | | | +--------------------- LC61 MD8
        | | | | | +------------------- LC60 NEMRD0
        | | | | | | +----------------- LC57 NEMRD1
        | | | | | | | +--------------- LC56 NENEMBH
        | | | | | | | | +------------- LC55 NENEMBL
        | | | | | | | | | +----------- LC54 NEN8B
        | | | | | | | | | | +--------- LC50 NWE0
        | | | | | | | | | | | +------- LC52 NWE1
        | | | | | | | | | | | | +----- LC63 WPFLG_3
        | | | | | | | | | | | | | +--- LC49 
        | | | | | | | | | | | | | | +- LC51 
        | | | | | | | | | | | | | | | 
LC      | | | | | | | | | | | | | | | | A B C D | Name

Pin
18   -> - - - - - - - - - - * * - - - | - * - * | CPS8
22   -> - * - - - * * - - - - - - - - | - * * * | CPS9
4    -> - - * - - - - * * * * * * - - | - - - * | EMUSPACE
23   -> - - - - - - - - * * * - - - - | - - - * | NBPBUS0
11   -> - - - - - - - * - * - * - - - | - - - * | NBPBUS1
84   -> - - - - - - - - - - - - - - - | - - - - | NCOVSELG
16   -> - - * - - - - - - - * * * - - | - - - * | NEMVALID
8    -> - - - - - - - * * * * * - - - | - - - * | NENEM
6    -> - * - - - * * - - - * * - - - | - - - * | NERD
51   -> - - - - - - - - - - * * * - - | - - - * | NEWE
30   -> - - * - - - - - - - - - - - - | - - - * | NGUARD
31   -> - - - - - - - - * - * - - - - | - - - * | NMBEN0
49   -> - - - - - - - * - * - * - - - | - - - * | NMBEN1
83   -> - - * - - - - * * * * * * - - | - - - * | NMEMRQ
2    -> - - - - - - - - - - - - - - - | - - - - | NRDOEG
10   -> - - - - - - - - - - * * * - - | - - - * | NRDONLY
20   -> - - * - - - - - - - - - * - - | - * - * | NRESET
15   -> - - - - - - - * * * - - - - - | - - - * | NSTROBE
1    -> - - - - - - - - - - - - - - - | - - * - | N2MVLD0
17   -> - - - - - - - * - * - - - - - | - - - * | SEL8
LC26 -> - * - - - * * * * * * * - - - | - - - * | DIAG_1
LC27 -> - - - - - - - - - - * * - - - | - - - * | DISRDONLY_1
LC23 -> - - - - - - - * * * * * - - - | - - - * | MAPCOVSEL
LC25 -> - - - - - - - - - - * * - - - | - - - * | NDMA_1
LC29 -> - - * - - - - - - - - - * - - | - - - * | NPRVIOL_1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                  c:\orcad4.04\orcad\ovrm\ovrm.rpt
OVRM

** EQUATIONS **

CPA4     : INPUT;
CPS8     : INPUT;
CPS9     : INPUT;
EA16     : INPUT;
EA17     : INPUT;
EA18     : INPUT;
EA19     : INPUT;
EA20     : INPUT;
EMUSPACE : INPUT;
NBPBUS0  : INPUT;
NBPBUS1  : INPUT;
NCOVSELG : INPUT;
NCPCS8   : INPUT;
NEMVALID : INPUT;
NENEM    : INPUT;
NERD     : INPUT;
NEWE     : INPUT;
NGUARD   : INPUT;
NMAX8M   : INPUT;
NMBEN0   : INPUT;
NMBEN1   : INPUT;
NMCS2L   : INPUT;
NMEMRQ   : INPUT;
NRDOEG   : INPUT;
NRDONLY  : INPUT;
NRESET   : INPUT;
NSTROBE  : INPUT;
N1MVLD   : INPUT;
N2MVLD0  : INPUT;
N2MVLD1  : INPUT;
N512KVLD : INPUT;
SEL8     : INPUT;

 CEMA17  = LCELL( _EQ001 $  VCC);
  _EQ001 = !EA17 & !NMAX8M;

CPD0     = TRI(_LC020, GLOBAL(!NRDOEG));
_LC020   = LCELL( _EQ002 $  GND);
  _EQ002 = !CPS9 &  ENIDCODE_7 & !NMCS2L
         # !CPS9 & !NCPCS8 & !WPFLG_3;

CPD1     = TRI(_LC019, GLOBAL(!NRDOEG));
_LC019   = LCELL( _EQ003 $  GND);
  _EQ003 = !CPS9 & !GUFLG_3 & !NCPCS8;

CPD2     = TRI(_LC043, GLOBAL(!NRDOEG));
_LC043   = LCELL( _EQ004 $  GND);
  _EQ004 = !CPS9 & !NCPCS8 &  N1MVLD;

CPD3     = TRI(_LC042, GLOBAL(!NRDOEG));
_LC042   = LCELL( _EQ005 $  GND);
  _EQ005 = !CPS9 & !NCPCS8 &  N2MVLD0;

CPD4     = TRI(_LC041, GLOBAL(!NRDOEG));
_LC041   = LCELL( _EQ006 $  GND);
  _EQ006 = !CPS9 & !NCPCS8 &  N2MVLD1;

CPD5     = TRI(_LC017, GLOBAL(!NRDOEG));
_LC017   = LCELL( _EQ007 $  GND);
  _EQ007 = !CPS9 &  ENIDCODE_7 & !NMCS2L
         # !CPS9 & !NCPCS8 &  NMAX8M;

CPD6     = TRI(_LC018, GLOBAL(!NRDOEG));
_LC018   = LCELL( _EQ008 $  GND);
  _EQ008 = !CPS9 & !NCPCS8 &  N512KVLD;

CPD7     = TRI(_LC053, GLOBAL(!NRDOEG));
_LC053   = LCELL( GND $  GND);

% DIAG_1   = _LC026 %
DIAG_1   = DFFE( _EQ009 $  GND,  _EQ010,  NRESET,  VCC,  VCC);
  _EQ009 = !CPD6 &  CPD7;
  _EQ010 =  _X001;
  _X001  = EXP(!CPA4 & !CPS8 & !NCPCS8);

 DIR     = LCELL( _EQ011 $  GND);
  _EQ011 = !CPS9 &  DIAG_1
         # !DIAG_1 & !NERD;

% DISRDONLY_1 = _LC027 %
DISRDONLY_1 = DFFE( CPD3 $  GND,  _EQ012,  VCC,  NRESET,  VCC);
  _EQ012 =  _X001;

% ENIDCODE_7 = _LC030 %
ENIDCODE_7 = DFFE( _EQ013 $  GND,  _EQ014,  NRESET,  VCC,  VCC);
  _EQ013 =  CPD6 &  CPD7;
  _EQ014 =  _X001;

% GUFLG_3  = _LC064 %
GUFLG_3  = DFFE( GND $  GND,  VCC, !_EQ015, !_EQ016,  VCC);
  _EQ015 =  _X002;
  _X002  = EXP( NPRVIOL_1 &  NRESET);
  _EQ016 =  EMUSPACE & !NEMVALID & !NGUARD & !NMEMRQ;

% INHIMAP  = _LC021 %
% INHIMAP  = |7474:U147|2Q %
 INHIMAP = DFFE( CPD1 $  GND,  _EQ017,  VCC,  NRESET,  VCC);
  _EQ017 =  _X001;

% MAPCOVSEL = _LC023 %
% MAPCOVSEL = |7474:U148|1Q %
 MAPCOVSEL = DFFE( CPD2 $  GND,  _EQ018,  VCC,  NRESET,  VCC);
  _EQ018 =  _X001;

MD0      = TRI(_LC062, GLOBAL(!NCOVSELG));
_LC062   = LCELL( GND $  VCC);

MD8      = TRI(_LC061, GLOBAL(!NCOVSELG));
_LC061   = LCELL( GND $  VCC);

% NDMA_1   = _LC025 %
NDMA_1   = DFFE( CPD0 $  GND,  _EQ019,  VCC,  NRESET,  VCC);
  _EQ019 =  _X003;
  _X003  = EXP( CPA4 & !CPS8 & !NCPCS8);

 NEMRD0  = LCELL( _EQ020 $  GND);
  _EQ020 =  CPS9 &  DIAG_1
         # !DIAG_1 &  NERD;

 NEMRD1  = LCELL( _EQ021 $  GND);
  _EQ021 =  CPS9 &  DIAG_1
         # !DIAG_1 &  NERD;

 NENEMBH = LCELL( _EQ022 $  VCC);
  _EQ022 = !DIAG_1 &  EMUSPACE &  MAPCOVSEL &  NBPBUS1 & !NENEM & !NMBEN1 & 
             !NMEMRQ & !NSTROBE & !SEL8;

 NENEMBL = LCELL( _EQ023 $  VCC);
  _EQ023 = !DIAG_1 &  EMUSPACE &  MAPCOVSEL &  NBPBUS0 & !NENEM & !NMBEN0 & 
             !NMEMRQ & !NSTROBE
         #  DIAG_1 & !NBPBUS0;

% NENMAP   = _LC028 %
% NENMAP   = |7474:U149|1Q %
 NENMAP  = DFFE( CPD4 $  GND,  _EQ024,  VCC,  NRESET,  VCC);
  _EQ024 =  _X001;

% NENVIOL_1 = _LC032 %
NENVIOL_1 = DFFE( CPD5 $  GND,  _EQ025,  VCC,  NRESET,  VCC);
  _EQ025 =  _X001;

% _LC040 borrows parallel expanders from _LC039 %
 NEN1M0  = LCELL( _EQ026 $  VCC);
  _EQ026 = !EA16 &  EA17 &  NMAX8M & !N1MVLD &  N2MVLD1
         # !EA16 &  EA17 &  NMAX8M & !N1MVLD &  N2MVLD0
         # !EA18 &  EA19 & !NMAX8M & !N1MVLD &  N2MVLD1
         # !EA18 &  EA19 & !NMAX8M & !N1MVLD &  N2MVLD0
         # !EA16 &  EA17 & !EA18 &  NMAX8M & !N1MVLD
         # !EA18 &  EA19 & !EA20 & !NMAX8M & !N1MVLD;

% _LC034 borrows parallel expanders from _LC033 %
 NEN1M1  = LCELL( _EQ027 $  VCC);
  _EQ027 =  EA16 &  EA17 &  NMAX8M & !N1MVLD &  N2MVLD1
         #  EA16 &  EA17 &  NMAX8M & !N1MVLD &  N2MVLD0
         #  EA18 &  EA19 & !NMAX8M & !N1MVLD &  N2MVLD1
         #  EA18 &  EA19 & !NMAX8M & !N1MVLD &  N2MVLD0
         #  EA16 &  EA17 & !EA18 &  NMAX8M & !N1MVLD
         #  EA18 &  EA19 & !EA20 & !NMAX8M & !N1MVLD;

 NEN2M0  = LCELL( _EQ028 $  VCC);
  _EQ028 = !EA16 & !EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         # !EA18 & !EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

 NEN2M1  = LCELL( _EQ029 $  VCC);
  _EQ029 =  EA16 & !EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA18 & !EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

 NEN2M2  = LCELL( _EQ030 $  VCC);
  _EQ030 = !EA16 &  EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         # !EA18 &  EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

 NEN2M3  = LCELL( _EQ031 $  VCC);
  _EQ031 =  EA16 &  EA17 &  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA18 &  EA19 &  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1;

 NEN8B   = LCELL( _EQ032 $  VCC);
  _EQ032 = !DIAG_1 &  EMUSPACE &  MAPCOVSEL &  NBPBUS0 & !NENEM & !NMBEN1 & 
             !NMEMRQ & !NSTROBE &  SEL8
         #  DIAG_1 & !NBPBUS1;

% _LC038 borrows parallel expanders from _LC037 %
 NEN512K0 = LCELL( _EQ033 $  GND);
  _EQ033 =  EA20 & !NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA18 & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA17 &  NMAX8M & !N1MVLD
         #  EA19 & !NMAX8M & !N1MVLD
         #  EA16 &  NMAX8M
         #  EA18 & !NMAX8M;

% _LC036 borrows parallel expanders from _LC035 %
 NEN512K1 = LCELL( _EQ034 $  GND);
  _EQ034 =  EA18 &  NMAX8M & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA18 &  EA20 & !N1MVLD & !N2MVLD0 & !N2MVLD1
         #  EA17 &  NMAX8M & !N1MVLD
         #  EA19 & !NMAX8M & !N1MVLD
         # !EA16 &  NMAX8M
         # !EA18 & !NMAX8M;

% NPRVIOL_1 = _LC029 %
NPRVIOL_1 = DFFE( _EQ035 $  VCC,  _EQ036,  VCC,  NRESET,  VCC);
  _EQ035 = !CPD6 & !CPD7;
  _EQ036 =  _X001;

 NRDOEOUT = LCELL( _EQ037 $  VCC);
  _EQ037 = !CPS9 &  ENIDCODE_7 & !NMCS2L
         # !CPS9 & !NCPCS8;

 NVIOLBRK = LCELL( _EQ038 $  NENVIOL_1);
  _EQ038 = !GUFLG_3 & !NENVIOL_1 & !WPFLG_3;

% _LC050 borrows parallel expanders from _LC049 %
 NWE0    = LCELL( _EQ039 $  VCC);
  _EQ039 = !DIAG_1 &  DISRDONLY_1 &  EMUSPACE & !NEMVALID & !NENEM & !NEWE & 
             !NMBEN0 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !NEMVALID & !NENEM & !NEWE & !NMBEN0 & 
             !NMEMRQ &  NRDONLY
         # !DIAG_1 &  DISRDONLY_1 &  EMUSPACE & !NDMA_1 & !NENEM & !NEWE & 
             !NMBEN0 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !NDMA_1 & !NENEM & !NEWE & !NMBEN0 & !NMEMRQ & 
              NRDONLY
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NEMVALID & !NENEM & !NERD & 
             !NMBEN0 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NEMVALID & !NENEM & !NEWE & 
             !NMBEN0 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NDMA_1 & !NENEM & !NERD & 
             !NMBEN0 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NDMA_1 & !NENEM & !NEWE & 
             !NMBEN0 & !NMEMRQ
         # !CPS8 &  DIAG_1 & !NBPBUS0;

% _LC052 borrows parallel expanders from _LC051 %
 NWE1    = LCELL( _EQ040 $  VCC);
  _EQ040 = !DIAG_1 &  DISRDONLY_1 &  EMUSPACE & !NEMVALID & !NENEM & !NEWE & 
             !NMBEN1 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !NEMVALID & !NENEM & !NEWE & !NMBEN1 & 
             !NMEMRQ &  NRDONLY
         # !DIAG_1 &  DISRDONLY_1 &  EMUSPACE & !NDMA_1 & !NENEM & !NEWE & 
             !NMBEN1 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !NDMA_1 & !NENEM & !NEWE & !NMBEN1 & !NMEMRQ & 
              NRDONLY
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NEMVALID & !NENEM & !NERD & 
             !NMBEN1 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NEMVALID & !NENEM & !NEWE & 
             !NMBEN1 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NDMA_1 & !NENEM & !NERD & 
             !NMBEN1 & !NMEMRQ
         # !DIAG_1 &  EMUSPACE & !MAPCOVSEL & !NDMA_1 & !NENEM & !NEWE & 
             !NMBEN1 & !NMEMRQ
         # !CPS8 &  DIAG_1 & !NBPBUS1;

% RESERVE  = _LC031 %
% RESERVE  = |7474:U147|1Q %
 RESERVE = DFFE( CPD0 $  GND,  _EQ041,  VCC,  NRESET,  VCC);
  _EQ041 =  _X001;

% WPFLG_3  = _LC063 %
WPFLG_3  = DFFE( GND $  GND,  VCC, !_EQ042, !_EQ043,  VCC);
  _EQ042 =  _X002;
  _EQ043 =  EMUSPACE & !NEMVALID & !NEWE & !NMEMRQ & !NRDONLY;

% _LC033 lends parallel expanders to _LC034 %

% _LC035 lends parallel expanders to _LC036 %

% _LC037 lends parallel expanders to _LC038 %

% _LC039 lends parallel expanders to _LC040 %

% _LC049 lends parallel expanders to _LC050 %

% _LC051 lends parallel expanders to _LC052 %


%
    Shareable expanders that are duplicated in multiple LABs:
    (none)
%


Project Information                           c:\orcad4.04\orcad\ovrm\ovrm.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                          = on
   Rules                               = EPLD Rules


Logic Synthesis:

   Default Synthesis Style             = Normal

      Logic option settings in 'Normal' style for 'MAX7000' family

      minimization                     = full
      parallel_expanders               = on
      soft_buffer_insertion            = on
      turbo_bit                        = on
      xor_synthesis                    = on

   Other logic synthesis settings:

      Automatic Global Clock           = on
      Automatic Global Clear           = on
      Automatic Global Preset          = on
      Automatic Global Output Enable   = on
      Automatic Peripheral Registers   = on

Functional SNF Extractor               = off

Linked SNF Extractor                   = off
Timing SNF Extractor                   = on
Optimize Timing SNF                    = on
Ignore Previous Fit                    = on
Automatic LCELL Insertion              = off
Generate JEDEC Files                   = on
Total Recompile                        = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                    = off
Verilog Netlist Writer                 = on
VHDL Netlist Writer                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor          00:00:29
   Database Builder                    00:00:11
   Logic Synthesizer                   00:00:11
   Partitioner                         00:00:03
   Fitter                              00:00:14
   Timing SNF Extractor                00:00:04
   Verilog Netlist Writer              00:00:12
   Assembler                           00:00:03
   Design Doctor                       00:00:17
   Timing SNF Optimization             00:00:19
   --------------------------          --------
   Total Time                          00:02:03

