PALASM 4 v1.5 MACH FITR - MARKET RELEASE (7-24-92)
 (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990,91,92

 
Reading User Design (TRE File)...
User Logic Pre-Placements... (PLC File)
|> WARNING F190 - Signal not found in Design! (Placement ignored) EA0

            ES4        EPSGN12       CLREMPTY   _9_ICEACTIVE
     _9_SDESGN8    _9_ESGN8ACT       _9_X17_Q    _9_ICEVALID
 
Reading Device Database ...

*************************************************
     Mach PLD Fitter - v 1.67          eph215
*************************************************

PAIR Analysis...
|> WARNING F179 - Pair Declaration Ignored: 215 PAIR S/R found - BUF0/_2_BUFQ1
|> WARNING F175 - Pair Equation Caution Bad Placements - BUF0/_2_BUFQ1

Pre-Placement & Equation Usage Checks... 
 
|> WARNING F210 - Design contains both floating & fixed placements.  


|> WARNING F138 - Clock signal(s) connected by PT logic: 
     _5_EPHOLDQ         ESGN10       _5_X29_D    _11_ENRDNDT





*** Timing Analysis for Signals

 Parameter   Min   Max           Signal List (Those having Max delay.)
      Tpd     1     2          _5_IO34_I 
      Tsu     1     3         _5_EPHOLDQ 
      Tco     0     2         _11_IO37_I       _5_IO34_I     _11_SDESGN8 
                              _11_RSICVL 
      Tcr     1     3       _11_ICEVALID      _5_EPHOLDQ           ESGN8 
                             _11_ENRDNDT    _11_PRTNDTVL 
.

 Key:
 Tpd - Combinatorial propagation delay, input to output
 Tsu - Combinatorial setup delay before clock
 Tco - clock to output (register output to combinatorial output)
 Tcr - Clock to register setup delay
.......(Register output thru combinatorial logic to reg input)
 All delay values are expressed in terms of array passes




*** Device Resource Checks

                Available        Used        Remaining
        Clocks:     2              1              1
          Pins:    38             30              8     ->    78%
     I/O Macro:    32             11             21
   Total Macro:    64             30             34
 Product Terms:   128             34              8     ->    92%
 
MACH-PLD Resource Checks OK!  



Partitioning Design into Blocks...

*** Last Equations Placed in Blocks

Weakly -      _11_IO37_I       _11_M47_O     _11_ENRDNDT    _11_PRTNDTVL 
Assign -    _11_ESGN8ACT        _5_X29_D       _5_IO34_I 


|> INFORMATION F050 - Device Utilization.............. *: 76 %



*** Block Partitioning Results

               Array   Product     # I/O    Buried    Signal    Macros
              Inputs    Terms      Macro     Logic    Fanout    Remain
   Block-> A    16        32*        3         5         6         8
   Block-> B    12        28         0         7         7         9
   Block-> C    12        28         2         5         7         9
   Block-> D    14        32*        6         2         8         8



*** Block Signal List

Blk-> A    _11_ENRDNDT  1      _11_M47_O  1       _5_ACTRD  5       _2_BUFQ3  1
                EPSGN8  3           ETB2  3           QSMD  3       _2_BUFQ1  0

Blk-> B       _5_X29_D  2  _11_ICEACTIVE  4    _11_SDESGN8  5      _11_X17_Q  5
            _5_EPHOLDQ  2     _5_ICEHOLD  2       _2_BUFQ2  1

Blk-> C   _11_ESGN8ACT  1     _11_IO37_I  1     _11_RSICVL  2   _11_ICEVALID  2
              _2_BUFQ4  1          EMPTY  1          ESGN7  5

Blk-> D      _5_IO34_I  1   _11_PRTNDTVL  6           NEWR  3           NERD  2
               NSTROBE  1         ESGN10  5          ESGN9  2          ESGN8  6



*** Block Input List

Blk-> A           BUF0  2         EPSGN3  1           EPT5  1        EPSGN16  1
                  EPT4  1        EPSGN15  1           EPS0  1           EPS1  1
                  EPS2  1           EPS3  1          ECTL3  1       _2_BUFQ2  1
              _2_BUFQ4  2     _5_ICEHOLD  1     _11_RSICVL  1   _11_ICEVALID  1
       

Singular:         EPSGN3{           ETB2}           EPT5{       _5_ACTRD}
                 EPSGN16{           QSMD}           EPT4{           QSMD}
                 EPSGN15{           QSMD}           EPS0{       _5_ACTRD}
                    EPS1{       _5_ACTRD}           EPS2{       _5_ACTRD}
                    EPS3{       _5_ACTRD}          ECTL3{         EPSGN8}
                _2_BUFQ2{           ETB2}     _5_ICEHOLD{         EPSGN8}
              _11_RSICVL{    _11_ENRDNDT}   _11_ICEVALID{      _11_M47_O}
         

Blk-> B           EPS0  3           EPS1  3           EPS2  3           EPS3  3
                  EPS7  1           EPS6  1          ESGN8  1       _2_BUFQ3  1
              _5_ACTRD  2      _5_IO34_I  1     _5_EPHOLDQ  1   _11_ESGN8ACT  1
       

Singular:           EPS7{       _5_X29_D}           EPS6{       _5_X29_D}
                   ESGN8{      _11_X17_Q}       _2_BUFQ3{       _2_BUFQ2}
               _5_IO34_I{     _5_EPHOLDQ}     _5_EPHOLDQ{     _5_ICEHOLD}
            _11_ESGN8ACT{    _11_SDESGN8}


Blk-> C       _2_BUFQ1  1           EPT5  2            ES0  1            ES1  1
                   ES2  1            ES3  1         EPSGN4  1          ESGN9  1
              _5_X29_D  1      _11_X17_Q  1      _11_M47_O  1     _11_IO37_I  1
       

Singular:       _2_BUFQ1{       _2_BUFQ4}            ES0{          ESGN7}
                     ES1{          ESGN7}            ES2{          ESGN7}
                     ES3{          ESGN7}         EPSGN4{          ESGN7}
                   ESGN9{     _11_IO37_I}       _5_X29_D{          EMPTY}
               _11_X17_Q{   _11_ESGN8ACT}      _11_M47_O{     _11_RSICVL}
              _11_IO37_I{   _11_ICEVALID}


Blk-> D         EPSGN8  1           EPS0  3           EPS1  3           EPS2  3
                  EPS3  3            ES0  1            ES1  2        NSTROBE  4
         _11_ICEACTIVE  1    _11_SDESGN8  1   _11_ESGN8ACT  1   _11_PRTNDTVL  1
           _11_ENRDNDT  1     _11_RSICVL  1

Singular:         EPSGN8{      _5_IO34_I}            ES0{           NEWR}
           _11_ICEACTIVE{        NSTROBE}    _11_SDESGN8{          ESGN8}
            _11_ESGN8ACT{          ESGN8}   _11_PRTNDTVL{          ESGN9}
             _11_ENRDNDT{   _11_PRTNDTVL}     _11_RSICVL{   _11_PRTNDTVL}
         

|> INFORMATION F070 - Multiple Assignment Mode - Repeat Count: 4
Assigning Resources...


Flags Used:             Unplace=False        Max Packing=False
Flags Used:        Expand Small=False         Expand All=False



*** Macro Block D

           NEWR (D  0)
           NERD (D  2)
          ESGN9 (D 12) -> (C  4)
        NSTROBE (D  6) -> (B  5) (D  5)
          ESGN8 (D 14) -> (A  6) (B  6) (D  6)
         ESGN10 (D 10)

 Buried Logic>       _5_IO34_I    _11_PRTNDTVL
      Targets>   4(41)   8(39)

      _5_IO34_I (D  4) -> (B  3)
   _11_PRTNDTVL (D  8) -> (D  0)



*** Macro Block Inputs

           EPT4 (I  0) -> (A  2)
        EPSGN15 (I  1) -> (A  0)
        ICECLK1 (I  2) -> (A  1)



*** Macro Block B

     _5_EPHOLDQ (B  6) -> (B 10)
     _5_ICEHOLD (B  2) -> (A  3)
       _2_BUFQ2 (B  0) -> (A  4)

 Buried Logic>        _5_X29_D     _11_SDESGN8       _11_X17_Q   _11_ICEACTIVE
              
      Targets>   4(19)   8(17)   9(na)  11(na)  13(na)


|> ERROR F610 - Product Term distribution - No feasible solution! _11_X17_Q 4


|> ERROR F610 - Product Term distribution - No feasible solution! _11_ICEACTIVE 4

       _5_X29_D (B  4) -> (C  8)
    _11_SDESGN8 (B  8) -> (D  3)
      _11_X17_Q (B  9) -> (C  6)
  _11_ICEACTIVE (B 11) -> (D  8)



*** Macro Block C

          EMPTY (C 14)
       _2_BUFQ4 (C  0) -> (A  5)
          ESGN7 (C 10)

 Buried Logic>    _11_ESGN8ACT    _11_ICEVALID      _11_IO37_I      _11_RSICVL
              
      Targets>   2(25)   3(na)   5(na)   7(na)  12(30)


|> ERROR F610 - Product Term distribution - No feasible solution! _11_ICEVALID 4


|> ERROR F610 - Product Term distribution - No feasible solution! _11_IO37_I 4


|> ERROR F610 - Product Term distribution - No feasible solution! _11_RSICVL 4

   _11_ESGN8ACT (C  2) -> (B  9) (D  9)
   _11_ICEVALID (C  3) -> (A 10)
     _11_IO37_I (C  5) -> (C  1)
     _11_RSICVL (C  7) -> (A 21) (D 21)



*** Macro Block A

           ETB2 (A  6)
         EPSGN8 (A 10) -> (D 16)
           QSMD (A  2)
       _2_BUFQ1 (A  0) -> (C  0)
       _2_BUFQ3 (A  4) -> (B 11)
       _5_ACTRD (A 12) -> (B  0)

 Buried Logic>       _11_M47_O
      Targets>  14( 9)

      _11_M47_O (A 14) -> (C 21)

|> ERROR F610 - Product Term distribution - No feasible solution!  

Try Using Expand Product Term Option  
 
 Unplaced:
    _11_ENRDNDT

           EPS1 (B 12) -> (A  9) (B 12) (D 12)
           EPT5 (A 12) -> (A 17) (C 17)
           EPS0 (B 14) -> (A 13) (B 13) (D 10)
        EPSGN16 (A 14) -> (A  7)
           EPS2 (B 10) -> (A  8) (B  8) (D 11)
           EPS3 (B  8)?
           EPS6 (B  0) -> (B  1)
           EPS7 (B  2) -> (B  2)
            ES0 (C  0) -> (C 12) (D  4)
            ES1 (C  2) -> (C  5) (D  7)
         EPSGN3 (A  8) -> (A 15) (B  4)
          ECTL3 (D  8) -> (A 11)
            ES2 (C  4) -> (C 11)
            ES3 (C  6) -> (C  9)
           BUF0 (A  0)?
         EPSGN4 (C  8) -> (C 10)
           EPS3 (B  8) ->   Blocked -> Reshuffling SwMtrx
           EPT5 -> (A 20)    Moved. -> Reshuffling SwMtrx
   _11_ICEVALID -> (A 17)    Moved. -> Reshuffling SwMtrx
           EPT4 -> (A 10)    Moved. -> Reshuffling SwMtrx
       _2_BUFQ2 -> (A  2)    Moved. -> Reshuffling SwMtrx
         EPSGN3 -> (A  4)    Moved. -> Reshuffling SwMtrx
          ESGN8 -> (A 15)    Moved. -> Reshuffling SwMtrx
     _5_ICEHOLD -> (A  6)    Moved. -> Reshuffling SwMtrx
     _11_RSICVL -> (A  3)    Moved. -> Reshuffling SwMtrx
        EPSGN16 -> (A 21)    Moved.
           EPS3 -> (A  7) (B  7)   Blocked -> Reshuffling SwMtrx
        NSTROBE -> (D 15)    Moved. -> Reshuffling SwMtrx
            ES1 -> (D  5)    Moved.
           EPS3 -> (D  7)
           BUF0 (A  0) ->   Blocked -> Reshuffling SwMtrx
        EPSGN16 -> (A 18)    Moved. -> Reshuffling SwMtrx
     _11_RSICVL -> (A 21)    Moved. -> Reshuffling SwMtrx
     _5_ICEHOLD -> (A  3)    Moved. -> Reshuffling SwMtrx
          ESGN8 -> (A  6)    Moved. -> Reshuffling SwMtrx
         EPSGN3 -> (A 15)    Moved. -> Reshuffling SwMtrx
       _2_BUFQ2 -> (A  4)    Moved. -> Reshuffling SwMtrx
          ECTL3 -> (A  2)    Moved. -> Reshuffling SwMtrx
           EPS2 -> (A 11)    Moved. -> Reshuffling SwMtrx
        EPSGN15 -> (A  8)    Moved.
           BUF0 -> (A  0)





Wiring Completion:   88% -> ( 13 nc)

*** Physical Signal Placements

           BUF0  (A  0)        _2_BUFQ1  (A  0)            QSMD  (A  2) 
           ETB2  (A  6)          EPSGN3  (A  8)          EPSGN8  (A 10) 
           EPT5  (A 12)         EPSGN16  (A 14)            EPT4  (I  0) 
        EPSGN15  (I  1)         ICECLK1  (I  2)            EPS0  (B 14) 
           EPS1  (B 12)            EPS2  (B 10)            EPS3  (B  8) 
           EPS7  (B  2)            EPS6  (B  0)             ES0  (C  0) 
            ES1  (C  2)             ES2  (C  4)             ES3  (C  6) 
         EPSGN4  (C  8)           ESGN7  (C 10)           EMPTY  (C 14) 
          ESGN8  (D 14)           ESGN9  (D 12)          ESGN10  (D 10) 
          ECTL3  (D  8)         NSTROBE  (D  6)            NERD  (D  2) 
           NEWR  (D  0)        _2_BUFQ3  (A  4)        _2_BUFQ2  (B  0) 
       _2_BUFQ4  (C  0)      _5_ICEHOLD  (B  2)        _5_ACTRD  (A 12) 
      _5_IO34_I  (D  4)      _5_EPHOLDQ  (B  6)        _5_X29_D  (B  4) 
  _11_ICEACTIVE  (B 11)     _11_SDESGN8  (B  8)    _11_ESGN8ACT  (C  2) 
   _11_PRTNDTVL  (D  8)       _11_X17_Q  (B  9)     _11_ENRDNDT    .?.  
     _11_RSICVL  (C  7)       _11_M47_O  (A 14)    _11_ICEVALID  (C  3) 
     _11_IO37_I  (C  5) Assigning Resources...
|> INFORMATION F085 - Intermediate Error Count: 6, Warning Count: 5


Flags Used:             Unplace=False        Max Packing=False
Flags Used:        Expand Small=True          Expand All=False



*** Macro Block D

           NEWR (D  0)
           NERD (D  2)
          ESGN9 (D 12) -> (C  4)
        NSTROBE (D  6) -> (B  5) (D  5)
         ESGN10 (D 10)
          ESGN8 (D 14) -> (A  6) (B  6) (D  6)

 Buried Logic>       _5_IO34_I    _11_PRTNDTVL
      Targets>   4(41)   8(39)

      _5_IO34_I (D  4) -> (B  3)
   _11_PRTNDTVL (D  8) -> (D  0)



*** Macro Block Inputs

           EPT4 (I  0) -> (A  2)
        EPSGN15 (I  1) -> (A  0)
        ICECLK1 (I  2) -> (A  1)



*** Macro Block B

       _2_BUFQ2 (B  0) -> (A  4)
     _5_ICEHOLD (B  2) -> (A  3)
     _5_EPHOLDQ (B  6) -> (B 10)

 Buried Logic>        _5_X29_D   _11_ICEACTIVE     _11_SDESGN8       _11_X17_Q
              
      Targets>   4(19)   8(17)  10(16)  12(15)  14(14)

       _5_X29_D (B  4) -> (C  8)
  _11_ICEACTIVE (B  8) -> (D  3)
    _11_SDESGN8 (B 10) -> (D  4)
      _11_X17_Q (B 12) -> (C  9)



*** Macro Block C

          ESGN7 (C 10)
          EMPTY (C 14)
       _2_BUFQ4 (C  0) -> (A  5)

 Buried Logic>    _11_ESGN8ACT      _11_IO37_I      _11_RSICVL    _11_ICEVALID
              
      Targets>   2(25)   4(26)   6(27)   8(28)  12(30)

   _11_ESGN8ACT (C  2) -> (B  9) (D  9)
     _11_IO37_I (C  4) -> (C  0)
     _11_RSICVL (C  6) -> (A 13) (D  2)
   _11_ICEVALID (C  8) -> (A  8)



*** Macro Block A

           ETB2 (A  6)
         EPSGN8 (A 10) -> (D 16)
           QSMD (A  2)
       _2_BUFQ1 (A  0) -> (C  1)
       _2_BUFQ3 (A  4) -> (B 11)
       _5_ACTRD (A 12) -> (B  0)

 Buried Logic>     _11_ENRDNDT       _11_M47_O
      Targets>   8( 6)  14( 9)

    _11_ENRDNDT (A  8) -> (D 13)
      _11_M47_O (A 14) -> (C 21)

           EPS6 (B  0) -> (B  1)
            ES0 (C  0) -> (C  6) (D 12)
           BUF0 (A  0) -> (A  9)
           EPS7 (B  2) -> (B  2)
            ES1 (C  2) -> (C  5) (D  7)
            ES2 (C  4) -> (C 11)
            ES3 (C  6) -> (C 15)
           EPS3 (B  8) -> (A  7) (B  7) (D 21)
         EPSGN3 (A  8) -> (A 15) (B  4)
         EPSGN4 (C  8) -> (C 10)
          ECTL3 (D  8) -> (A 11)
           EPS2 (B 10)?
           EPS1 (B 12) -> (A 12) (B 12) (D 15)
           EPT5 (A 12) -> (A 17) (C 17)
           EPS0 (B 14) -> (A 10) (B 13) (D 10)
        EPSGN16 (A 14) -> (A 18)
           EPS2 (B 10) ->   Blocked -> Reshuffling SwMtrx
        EPSGN15 -> (A 16)    Moved. -> Reshuffling SwMtrx
           BUF0 -> (A  0)    Moved. -> Reshuffling SwMtrx
           EPS1 -> (A  9)    Moved. -> Reshuffling SwMtrx
          ESGN8 -> (A 12)    Moved. -> Reshuffling SwMtrx
   _11_ICEVALID -> (A  6)    Moved.
           EPS2 -> (A  8) (B  8) (D  8)





Wiring Completion:  100% -> (  0 nc)

|> INFORMATION F058 - Total Block Fanout (All Signals) *: 59 


*** Signals - Tabular Information

          Signal   #   P/N #   (Loc)      Type     Logic  # PT    Blocks
           BUF0    1     2      A  0       input       .     .    .A...
       _2_BUFQ1    2     2      A  0      buried    d-ff     1    ...C.
           QSMD    3     3      A  2     i/o pin    d-ff     1    .....
           ETB2    4     5      A  6     i/o pin    comb     1    .....
         EPSGN3    5     6      A  8       input       .     .    .AB..
         EPSGN8    6     7      A 10     i/o pin    comb     2    ....D
           EPT5    7     8      A 12       input       .     .    .A.C.
        EPSGN16    8     9      A 14       input       .     .    .A...
           EPT4    9    10      I  0       input       .     .    .A...
        EPSGN15   10    11      I  1       input       .     .    .A...
        ICECLK1   11    13      I  2   clock pin       .     .    .A...
           EPS0   12    14      B 14       input       .     .    .AB.D
           EPS1   13    15      B 12       input       .     .    .AB.D
           EPS2   14    16      B 10       input       .     .    .AB.D
           EPS3   15    17      B  8       input       .     .    .AB.D
           EPS7   16    20      B  2       input       .     .    ..B..
           EPS6   17    21      B  0       input       .     .    ..B..
            ES0   18    24      C  0       input       .     .    ...CD
            ES1   19    25      C  2       input       .     .    ...CD
            ES2   20    26      C  4       input       .     .    ...C.
            ES3   21    27      C  6       input       .     .    ...C.
         EPSGN4   22    28      C  8       input       .     .    ...C.
          ESGN7   23    29      C 10     i/o pin    comb     2    .....
          EMPTY   24    31      C 14     i/o pin    d-ff     1    .....
          ESGN8   25    36      D 14     i/o pin    d-ff     1    .AB.D
          ESGN9   26    37      D 12     i/o pin    comb     1    ...C.
         ESGN10   27    38      D 10     i/o pin    d-ff     1    .....
          ECTL3   28    39      D  8       input       .     .    .A...
        NSTROBE   29    40      D  6     i/o pin    d-ff     1    ..B.D
           NERD   30    42      D  2     i/o pin    comb     1    .....
           NEWR   31    43      D  0     i/o pin    comb     1    .....
       _2_BUFQ3   32     6      A  4      buried    d-ff     1    ..B..
       _2_BUFQ2   33    18      B  0      buried    d-ff     1    .A...
       _2_BUFQ4   34    34      C  0      buried    d-ff     1    .A...
     _5_ICEHOLD   35    20      B  2      buried    d-ff     1    .A...
       _5_ACTRD   36    14      A 12      buried    comb     1    ..B..
      _5_IO34_I   37    54      D  4      buried    comb     1    ..B..
     _5_EPHOLDQ   38    24      B  6      buried    d-ff     1    ..B..
       _5_X29_D   39    22      B  4      buried    d-ff     1    ...C.
  _11_ICEACTIVE   40    26      B  8      buried    d-ff     2    ....D
    _11_SDESGN8   41    28      B 10      buried    comb     2    ....D
   _11_ESGN8ACT   42    36      C  2      buried    comb     1    ..B.D
   _11_PRTNDTVL   43    58      D  8      buried    d-ff     1    ....D
      _11_X17_Q   44    30      B 12      buried    d-ff     1    ...C.
    _11_ENRDNDT   45    10      A  8      buried    d-ff     1    ....D
     _11_RSICVL   46    40      C  6      buried    comb     1    .A..D
      _11_M47_O   47    16      A 14      buried    comb     1    ...C.
   _11_ICEVALID   48    42      C  8      buried    d-ff     1    .A...
     _11_IO37_I   49    38      C  4      buried    comb     1    ...C.
.

 Key:
 P/N # - Pin/Node Number
 .?. - Signal Unplaced
 (Loc) - Macrocell Location (Block & Cell)
 # PT - Number of used product terms in logic
 Blocks- Device blocks driven by signal
 comb - Combinatorial logic function
 d-ff - D-Type Flip-flop
 t-ff - T-Type Flip-flop
 Note: Registered input storage equations (MACH-2xx family)
 ..... are realized with 0 array product terms.


*** Signals - Equations Where Used

   Signal Source                   Fanout List
           BUF0:       _2_BUFQ1          EPSGN8 
               {AA}
       _2_BUFQ1:       _2_BUFQ4 
               {C}
         EPSGN3:           ETB2      _5_EPHOLDQ 
               {AB}
         EPSGN8:      _5_IO34_I 
               {D}
           EPT5:   _11_ICEVALID      _11_RSICVL        _5_ACTRD 
               {CCA}
        EPSGN16:           QSMD 
               {A}
           EPT4:           QSMD 
               {A}
        EPSGN15:           QSMD 
               {A}
        ICECLK1:       _2_BUFQ1 
               {A}
           EPS0:      _11_X17_Q    _11_PRTNDTVL     _11_SDESGN8   _11_ICEACTIVE 
               :       _5_ACTRD          ESGN10           ESGN8 
               {BDBB ADD}

           EPS1:      _11_X17_Q    _11_PRTNDTVL     _11_SDESGN8   _11_ICEACTIVE 
               :       _5_ACTRD          ESGN10           ESGN8 
               {BDBB ADD}

           EPS2:      _11_X17_Q    _11_PRTNDTVL     _11_SDESGN8   _11_ICEACTIVE 
               :       _5_ACTRD          ESGN10           ESGN8 
               {BDBB ADD}

           EPS3:      _11_X17_Q    _11_PRTNDTVL     _11_SDESGN8   _11_ICEACTIVE 
               :       _5_ACTRD          ESGN10           ESGN8 
               {BDBB ADD}

           EPS7:       _5_X29_D 
               {B}
           EPS6:       _5_X29_D 
               {B}
            ES0:           NEWR           ESGN7 
               {DC}
            ES1:           NEWR            NERD           ESGN7 
               {DDC}
            ES2:          ESGN7 
               {C}
            ES3:          ESGN7 
               {C}
         EPSGN4:          ESGN7 
               {C}
          ESGN8:      _11_X17_Q          ESGN10     _11_ENRDNDT 
               {BDA}
          ESGN9:     _11_IO37_I 
               {C}
          ECTL3:         EPSGN8 
               {A}
        NSTROBE:           NEWR            NERD          ESGN10           ESGN9 
               :       _5_X29_D 
               {DDDD B}

       _2_BUFQ3:       _2_BUFQ2 
               {B}
       _2_BUFQ2:           ETB2 
               {A}
       _2_BUFQ4:       _2_BUFQ3            ETB2 
               {AA}
     _5_ICEHOLD:         EPSGN8 
               {A}
       _5_ACTRD:     _5_EPHOLDQ      _5_ICEHOLD 
               {BB}
      _5_IO34_I:     _5_EPHOLDQ 
               {B}
     _5_EPHOLDQ:     _5_ICEHOLD 
               {B}
       _5_X29_D:          EMPTY 
               {C}
  _11_ICEACTIVE:        NSTROBE 
               {D}
    _11_SDESGN8:          ESGN8 
               {D}
   _11_ESGN8ACT:    _11_SDESGN8           ESGN8 
               {BD}
   _11_PRTNDTVL:          ESGN9 
               {D}
      _11_X17_Q:   _11_ESGN8ACT 
               {C}
    _11_ENRDNDT:   _11_PRTNDTVL 
               {D}
     _11_RSICVL:    _11_ENRDNDT    _11_PRTNDTVL 
               {AD}
      _11_M47_O:     _11_RSICVL 
               {C}
   _11_ICEVALID:      _11_M47_O 
               {A}
     _11_IO37_I:   _11_ICEVALID 
               {C}



*** Outputs with no feedback

             QSMD            ETB2           ESGN7           EMPTY          ESGN10 
             NERD            NEWR 


*** Feedback Map - eph215

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
         | 0|     BUF0 : 0|     |21|             _5_ACTRD  0|     |21|        
         | 1|  ICECLK1 : 1|     |20|                EPS6 : 1|     |20|        
         | 2|     EPT4 : 2|     |19|                EPS7 : 2|     |19|        
         | 3|  _5_ICEHO  3|     |18| EPSGN16     _5_IO34_  3|     |18|        
         | 4|  _2_BUFQ2  4|     |17| EPT5         EPSGN3 : 4|     |17|        
         | 5|  _2_BUFQ4  5|     |16| EPSGN15     NSTROBE : 5|     |16|        
         '--'  _11_ICEV  6|     |15: EPSGN3        ESGN8 : 6|     |15|        
                  EPS3 : 7|     |14|                EPS3 : 7|     |14|        
                  EPS2 : 8|     |13: _11_RSI        EPS2 : 8|     |13: EPS0   
                  EPS1 : 9|     |12: ESGN8       _11_ESGN  9|     |12: EPS1   
K:  * Used        EPS0 :10|     |11: ECTL3       _5_EPHOL 10|     |11: _2_BUFQ
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A      _11_IO37  0|     |21| _11_M47     _11_PRTN  0|     |21| EPS3   
    0 RegIn    _2_BUFQ1  1|     |20|                     | 1|     |20|        
    - No.PT            | 2|     |19|             _11_RSIC  2|     |19|        
                       | 3|     |18|             _11_ICEA  3|     |18|        
                 ESGN9 : 4|     |17| EPT5        _11_SDES  4|     |17|        
                   ES1 : 5|     |16|             NSTROBE : 5|     |16| EPSGN8 
                   ES0 : 6|     |15: ES3           ESGN8 : 6|     |15: EPS1   
                       | 7|     |14|                 ES1 : 7|     |14|        
               _5_X29_D  8|     |13|                EPS2 : 8|     |13: _11_ENR
               _11_X17_  9|     |12|             _11_ESGN  9|     |12: ES0    
                EPSGN4 :10|     |11: ES2            EPS0 :10|     |11|        
                       '--+-u--u+--'                     '--+-u--u+--'        



*** Logic Map - eph215

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
         | 0|  _2_BUFQ1  0| 1  #|21|             _2_BUFQ2  0| 1  #|21|        
         | 1|          | 1| -  #|20|                     | 1| -  #|20|        
         | 2|     QSMD | 2| 1  #|19|             _5_ICEHO  2| 1  #|19|        
         | 3|          | 3| -  #|18|                     | 3| -  #|18|        
         | 4|  _2_BUFQ3  4| 1  #|17|             _5_X29_D  4| 1  #|17|        
         | 5|          | 5| -  #|16|                     | 5| -  #|16|        
         '--'     ETB2 | 6| 1  -|15|             _5_EPHOL  6| 1  -|15|        
                       | 7| -  1|14| _11_M47             | 7| -  .|14|        
               _11_ENRD  8| 1  -|13|             _11_ICEA  8| 2  -|13|        
                       | 9| -  1|12| _5_ACTR             | 9| -  1|12| _11_X17
K:  * Used      EPSGN8 |10| 2  -|11|             _11_SDES 10| 2  -|11|        
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A      _2_BUFQ4  0| 1  #|21|                NEWR | 0| 1  #|21|        
    0 RegIn            | 1| -  #|20|                     | 1| -  #|20|        
    - No.PT    _11_ESGN  2| 1  #|19|                NERD | 2| 1  #|19|        
                       | 3| -  #|18|                     | 3| -  #|18|        
               _11_IO37  4| 1  #|17|             _5_IO34_  4| 1  #|17|        
                       | 5| -  #|16|                     | 5| -  #|16|        
               _11_RSIC  6| 1  -|15|             NSTROBE | 6| 1  -|15|        
                       | 7| -  1|14| EMPTY               | 7| -  1|14| ESGN8  
               _11_ICEV  8| 1  -|13|             _11_PRTN  8| 1  -|13|        
                       | 9| -  .|12|                     | 9| -  1|12| ESGN9  
                 ESGN7 |10| 2  -|11|              ESGN10 |10| 1  -|11|        
                       '--+-u--u+--'                     '--+-u--u+--'        


*** Pin Map - eph215
                                                                   
                                                                   
                                                                   
                                                                   
                                   BUF0                            
                                QSMD  |        NEWR                
                                .  |  |        |  NERD             
                          ETB2  |  |  |        |  |  .             
                     EPSGN3  |  |  |  |        |  |  |  NSTROBE    
                          |  |  |  |  |        |  |  |  |          
                    .-----'--'--'--'--'--o-----'--'--'--'---.      
                    |                       4  4  4  4  4   |      
                    |     6  5  4  3  2  1  4  3  2  1  0   |      
              EPSGN8| 7                                   39|ECTL3 
                EPT5| 8                  G  V             38|ESGN10
             EPSGN16| 9                  n  c             37|ESGN9 
                EPT4|10                  d  c             36|ESGN8 
             EPSGN15|11                                   35|      
                Gnd |12            MACH-215               34| Gnd  
             ICECLK1|13                                   33|      
                EPS0|14             V  G                  32|      
                EPS1|15             c  n                  31|EMPTY 
                EPS2|16             c  d                  30|      
                EPS3|17                                   29|ESGN7 
                    |   1  1  2  2  2  2  2  2  2  2  2     |      
                    |   8  9  0  1  2  3  4  5  6  7  8     |      
                    '---.--.--.--.--------.--.--.--.--.-----'      
                        |  |  |  |        |  |  |  |  |            
                        '  |  |  |        |  |  |  |  EPSGN4       
                           '  |  |        |  |  |  ES3             
                           EPS7  |        |  |  ES2                
                              EPS6        |  ES1                   
                                          ES0                      
The Jedec Data is  stored in ===> EPH215.jed
The Placements are stored in ===> EPH215.plc
The Design Doc is  stored in ===> EPH215.rpt
 
%% FITR %% Error Count: 0, Warning Count: 5
%% FITR %% File Processed Successfully. - File: EPH215.PDS
 
