Project Information                               c:\hd302\hd302c2\hd302c2.rpt

MAX+plus II Compiler Report File
Version 6.1 02/28/96
Compiled: 05/10/96 16:26:36

Copyright (c) 1996 by Altera Corporation.  All rights reserved.  This text
contains proprietary, confidential information of Altera Corporation, and
may be used, copied, and/or disclosed only pursuant to the terms of a
valid software license agreement with Altera Corporation.  This copyright
notice must be retained as part of this text at all times.



***** Project compilation was successful


The Header controller of MICEpack 68302. rev 1.0


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

hd302c2   EPM7032LC44-10   12       17       0      17      0           53 %

User Pins:                 12       17       0  



Project Information                               c:\hd302\hd302c2\hd302c2.rpt

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

hd302c2@36                        bmsk8
hd302c2@41                        eDisCpu
hd302c2@4                         epD0
hd302c2@5                         epD1
hd302c2@6                         epD2
hd302c2@7                         epD3
hd302c2@8                         epD4
hd302c2@9                         epD5
hd302c2@11                        epD6
hd302c2@12                        epD7
hd302c2@13                        epD8
hd302c2@14                        epD9
hd302c2@16                        epD10
hd302c2@17                        epD11
hd302c2@18                        epD12
hd302c2@19                        epD13
hd302c2@20                        epD14
hd302c2@21                        epD15
hd302c2@40                        epUds
hd302c2@1                         iac
hd302c2@31                        nCsActive
hd302c2@28                        ncsExt0
hd302c2@29                        ncsExt1
hd302c2@24                        ncs0
hd302c2@25                        ncs1
hd302c2@26                        ncs2
hd302c2@27                        ncs3
hd302c2@44                        neHiByte
hd302c2@2                         neLowByte


Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

***** Logic for device 'hd302c2' compiled without errors.




Device: EPM7032LC44-10
Turbo: ON
Security: OFF


Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

** ERROR SUMMARY **

Info: Chip 'hd302c2' in device 'EPM7032LC44-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                           n                    
                           e     n              
                           L     e        e     
                           o     H        D     
                           w     i        i  e  
               e  e  e     B     B        s  p  
               p  p  p  V  y  i  y  G  G  C  U  
               D  D  D  C  t  a  t  N  N  p  d  
               2  1  0  C  e  c  e  D  D  u  s  
             -----------------------------------_ 
           /   6  5  4  3  2  1 44 43 42 41 40   | 
     epD3 |  7                                39 | RESERVED 
     epD4 |  8                                38 | RESERVED 
     epD5 |  9                                37 | RESERVED 
      GND | 10                                36 | bmsk8 
     epD6 | 11                                35 | VCC 
     epD7 | 12         EPM7032LC44-10         34 | RESERVED 
     epD8 | 13                                33 | RESERVED 
     epD9 | 14                                32 | RESERVED 
      VCC | 15                                31 | nCsActive 
    epD10 | 16                                30 | GND 
    epD11 | 17                                29 | ncsExt1 
          |_  18 19 20 21 22 23 24 25 26 27 28  _| 
            ------------------------------------ 
               e  e  e  e  G  V  n  n  n  n  n  
               p  p  p  p  N  C  c  c  c  c  c  
               D  D  D  D  D  C  s  s  s  s  s  
               1  1  1  1        0  1  2  3  E  
               2  3  4  5                    x  
                                             t  
                                             0  
                                                
                                                


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    16/16(100%)  16/16(100%)   0/16(  0%)   2/36(  5%) 
B:    LC17 - LC32     1/16(  6%)  10/16( 62%)   0/16(  0%)   8/36( 22%) 


Total dedicated input pins used:                 3/4    ( 75%)
Total I/O pins used:                            26/32   ( 81%)
Total logic cells used:                         17/32   ( 53%)
Total shareable expanders used:                  0/32   (  0%)
Total Turbo logic cells used:                   17/32   ( 53%)
Total shareable expanders not available (n/a):   0/32   (  0%)

Total input pins required:                      12
Total output pins required:                     17
Total bidirectional pins required:               0
Total logic cells required:                     17
Total flipflops required:                        0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32 (  0%)



Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  36   (22)  (B)      INPUT              0      0   0    0    0    5    0  bmsk8
  41   (17)  (B)      INPUT              0      0   0    0    0    1    0  eDisCpu
  40   (18)  (B)      INPUT              0      0   0    0    0    5    0  epUds
   1      -   -       INPUT              0      0   0    0    0    1    0  iac
  28   (28)  (B)      INPUT              0      0   0    0    0    1    0  ncsExt0
  29   (27)  (B)      INPUT              0      0   0    0    0    1    0  ncsExt1
  24   (32)  (B)      INPUT              0      0   0    0    0    1    0  ncs0
  25   (31)  (B)      INPUT              0      0   0    0    0    1    0  ncs1
  26   (30)  (B)      INPUT              0      0   0    0    0    1    0  ncs2
  27   (29)  (B)      INPUT              0      0   0    0    0    1    0  ncs3
  44      -   -       INPUT              0      0   0    0    0    0    0  neHiByte
   2      -   -       INPUT              0      0   0    0    0    0    0  neLowByte


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4      1    A        TRI     t        0      0   0    0    0    0    0  epD0
   5      2    A        TRI     t        0      0   0    2    0    0    0  epD1
   6      3    A        TRI     t        0      0   0    2    0    0    0  epD2
   7      4    A        TRI     t        0      0   0    2    0    0    0  epD3
   8      5    A        TRI     t        0      0   0    2    0    0    0  epD4
   9      6    A        TRI     t        0      0   0    0    0    0    0  epD5
  11      7    A        TRI     t        0      0   0    0    0    0    0  epD6
  12      8    A        TRI     t        0      0   0    2    0    0    0  epD7
  13      9    A        TRI     t        0      0   0    0    0    0    0  epD8
  14     10    A        TRI     t        0      0   0    0    0    0    0  epD9
  16     11    A        TRI     t        0      0   0    0    0    0    0  epD10
  17     12    A        TRI     t        0      0   0    0    0    0    0  epD11
  18     13    A        TRI     t        0      0   0    0    0    0    0  epD12
  19     14    A        TRI     t        0      0   0    0    0    0    0  epD13
  20     15    A        TRI     t        0      0   0    0    0    0    0  epD14
  21     16    A        TRI     t        0      0   0    0    0    0    0  epD15
  31     26    B     OUTPUT     t        0      0   0    8    0    0    0  nCsActive


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                         Logic cells placed in LAB 'A'
        +------------------------------- LC1 epD0
        | +----------------------------- LC2 epD1
        | | +--------------------------- LC3 epD2
        | | | +------------------------- LC4 epD3
        | | | | +----------------------- LC5 epD4
        | | | | | +--------------------- LC6 epD5
        | | | | | | +------------------- LC7 epD6
        | | | | | | | +----------------- LC8 epD7
        | | | | | | | | +--------------- LC9 epD8
        | | | | | | | | | +------------- LC10 epD9
        | | | | | | | | | | +----------- LC11 epD10
        | | | | | | | | | | | +--------- LC12 epD11
        | | | | | | | | | | | | +------- LC13 epD12
        | | | | | | | | | | | | | +----- LC14 epD13
        | | | | | | | | | | | | | | +--- LC15 epD14
        | | | | | | | | | | | | | | | +- LC16 epD15
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':

Pin
36   -> - * * * * - - * - - - - - - - - | * - | <-- bmsk8
40   -> - * * * * - - * - - - - - - - - | * - | <-- epUds
1    -> - - - - - - - - - - - - - - - - | - * | <-- iac
44   -> - - - - - - - - - - - - - - - - | - - | <-- neHiByte
2    -> - - - - - - - - - - - - - - - - | - - | <-- neLowByte


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

           Logic cells placed in LAB 'B'
        +- LC26 nCsActive
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'B'
LC      | | A B |     Logic cells that feed LAB 'B':

Pin
41   -> * | - * | <-- eDisCpu
1    -> * | - * | <-- iac
28   -> * | - * | <-- ncsExt0
29   -> * | - * | <-- ncsExt1
24   -> * | - * | <-- ncs0
25   -> * | - * | <-- ncs1
26   -> * | - * | <-- ncs2
27   -> * | - * | <-- ncs3
44   -> - | - - | <-- neHiByte
2    -> - | - - | <-- neLowByte


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      c:\hd302\hd302c2\hd302c2.rpt
hd302c2

** EQUATIONS **

bmsk8    : INPUT;
eDisCpu  : INPUT;
epUds    : INPUT;
iac      : INPUT;
ncsExt0  : INPUT;
ncsExt1  : INPUT;
ncs0     : INPUT;
ncs1     : INPUT;
ncs2     : INPUT;
ncs3     : INPUT;
neHiByte : INPUT;
neLowByte : INPUT;

-- Node name is 'epD0' 
-- Equation name is 'epD0', location is LC001, type is output.
epD0     = TRI(_LC001, GLOBAL(!neLowByte));
_LC001   = LCELL( GND $  GND);

-- Node name is 'epD1' 
-- Equation name is 'epD1', location is LC002, type is output.
epD1     = TRI(_LC002, GLOBAL(!neLowByte));
_LC002   = LCELL( _EQ001 $ !bmsk8);
  _EQ001 =  bmsk8 &  epUds;

-- Node name is 'epD2' 
-- Equation name is 'epD2', location is LC003, type is output.
epD2     = TRI(_LC003, GLOBAL(!neLowByte));
_LC003   = LCELL( _EQ002 $ !bmsk8);
  _EQ002 =  bmsk8 &  epUds;

-- Node name is 'epD3' 
-- Equation name is 'epD3', location is LC004, type is output.
epD3     = TRI(_LC004, GLOBAL(!neLowByte));
_LC004   = LCELL( _EQ003 $ !bmsk8);
  _EQ003 =  bmsk8 &  epUds;

-- Node name is 'epD4' 
-- Equation name is 'epD4', location is LC005, type is output.
epD4     = TRI(_LC005, GLOBAL(!neLowByte));
_LC005   = LCELL( _EQ004 $ !bmsk8);
  _EQ004 =  bmsk8 &  epUds;

-- Node name is 'epD5' 
-- Equation name is 'epD5', location is LC006, type is output.
epD5     = TRI(_LC006, GLOBAL(!neLowByte));
_LC006   = LCELL( GND $  VCC);

-- Node name is 'epD6' 
-- Equation name is 'epD6', location is LC007, type is output.
epD6     = TRI(_LC007, GLOBAL(!neLowByte));
_LC007   = LCELL( GND $  VCC);

-- Node name is 'epD7' 
-- Equation name is 'epD7', location is LC008, type is output.
epD7     = TRI(_LC008, GLOBAL(!neLowByte));
_LC008   = LCELL( _EQ005 $ !bmsk8);
  _EQ005 =  bmsk8 &  epUds;

-- Node name is 'epD8' 
-- Equation name is 'epD8', location is LC009, type is output.
epD8     = TRI(_LC009, GLOBAL(!neHiByte));
_LC009   = LCELL( GND $  GND);

-- Node name is 'epD9' 
-- Equation name is 'epD9', location is LC010, type is output.
epD9     = TRI(_LC010, GLOBAL(!neHiByte));
_LC010   = LCELL( GND $  GND);

-- Node name is 'epD10' 
-- Equation name is 'epD10', location is LC011, type is output.
epD10    = TRI(_LC011, GLOBAL(!neHiByte));
_LC011   = LCELL( GND $  GND);

-- Node name is 'epD11' 
-- Equation name is 'epD11', location is LC012, type is output.
epD11    = TRI(_LC012, GLOBAL(!neHiByte));
_LC012   = LCELL( GND $  GND);

-- Node name is 'epD12' 
-- Equation name is 'epD12', location is LC013, type is output.
epD12    = TRI(_LC013, GLOBAL(!neHiByte));
_LC013   = LCELL( GND $  GND);

-- Node name is 'epD13' 
-- Equation name is 'epD13', location is LC014, type is output.
epD13    = TRI(_LC014, GLOBAL(!neHiByte));
_LC014   = LCELL( GND $  VCC);

-- Node name is 'epD14' 
-- Equation name is 'epD14', location is LC015, type is output.
epD14    = TRI(_LC015, GLOBAL(!neHiByte));
_LC015   = LCELL( GND $  VCC);

-- Node name is 'epD15' 
-- Equation name is 'epD15', location is LC016, type is output.
epD15    = TRI(_LC016, GLOBAL(!neHiByte));
_LC016   = LCELL( GND $  GND);

-- Node name is 'nCsActive' 
-- Equation name is 'nCsActive', location is LC026, type is output.
 nCsActive = LCELL( _EQ006 $  GND);
  _EQ006 =  eDisCpu & !iac &  ncsExt0 &  ncsExt1 &  ncs1 &  ncs2 &  ncs3
         # !iac &  ncsExt0 &  ncsExt1 &  ncs0 &  ncs1 &  ncs2 &  ncs3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                               c:\hd302\hd302c2\hd302c2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic I/O Cell Registers        = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,626K
