Project Information                                         c:\hd328\hd328.rpt

MAX+plus II Compiler Report File
Version 6.2 06/12/96
Compiled: 10/15/96 18:01:13

Copyright (c) 1996 by Altera Corporation.  All rights reserved.  This text
contains proprietary, confidential information of Altera Corporation, and
may be used, copied, and/or disclosed only pursuant to the terms of a
valid software license agreement with Altera Corporation.  This copyright
notice must be retained as part of this text at all times.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

HD328     EPM7064LC84-10   30       30       0      48      9           75 %

User Pins:                 30       30       0  



Project Information                                         c:\hd328\hd328.rpt

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

HD328@30                          BA0
HD328@4                           BONDBG
HD328@18                          BRKACK
HD328@9                           CPENAS
HD328@49                          DIRPBDH
HD328@48                          DIRPBDL
HD328@79                          DISNRDYF
HD328@24                          DLYAS
HD328@23                          DLYLDS
HD328@35                          DLYUDS
HD328@11                          EMUSPACE
HD328@20                          EPAS
HD328@34                          EPA0
HD328@62                          EPBG
HD328@63                          EPDTACK
HD328@80                          EPFC0
HD328@14                          EPFC1
HD328@15                          EPFC2
HD328@29                          EPGO
HD328@84                          EPLDS
HD328@17                          EPRW
HD328@37                          EPSTOP
HD328@2                           EPUDS
HD328@22                          EXRDY
HD328@67                          FLAGNOTRDY
HD328@55                          ICEBRK
HD328@83                          ICECLK1
HD328@10                          ICEDTACK
HD328@31                          ICERDY
HD328@5                           ISOEP
HD328@6                           MEA0
HD328@60                          NADVALID
HD328@16                          NCSSYS
HD328@44                          NDATAVALID
HD328@36                          NEMDFC
HD328@46                          NEMSFC
HD328@69                          NEMVALID
HD328@51                          NENASDS
HD328@41                          NENEPFC
HD328@45                          NENPBA
HD328@57                          NENPBD
HD328@56                          NENRWSTB
HD328@54                          NENVDH
HD328@52                          NENVDL
HD328@39                          NERD
HD328@40                          NEWR
HD328@25                          NINSHI
HD328@58                          NINSJMP
HD328@12                          NINSLOW
HD328@65                          NLDSDLY
HD328@61                          NMEMREQ
HD328@21                          NMHERE
HD328@27                          NRDONLY
HD328@50                          NSELEPFC
HD328@64                          NSTROBE
HD328@33                          NSTSVALID
HD328@68                          NUDSDLY
HD328@1                           ONCHIP
HD328@8                           QUAL
HD328@28                          TGHOLD


Project Information                                         c:\hd328\hd328.rpt

** FILE HIERARCHY **



|7474:U18|
|7474:U22|
|7474:U25|
|7474:U32|
|7474:U43|
|7474:U54|
|7474:U55|
|7474:U56|
|7474:U67|
|7474:U70|
|7474:U73|
|7474:U77|


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

***** Logic for device 'HD328' compiled without errors.




Device: EPM7064LC84-10
Turbo: ON
Security: OFF


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** ERROR SUMMARY **

Info: Chip 'HD328' in device 'EPM7064LC84-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                                               
                                                                               
                E  I                                      R     D     R  R  R  
                M  C                                I     E     I     E  E  E  
                U  E  C              B        O     C     S     S     S  S  S  
                S  D  P           I  O     E  N  E  E     E  E  N     E  E  E  
                P  T  E  Q     M  S  N     P  C  P  C     R  P  R     R  R  R  
                A  A  N  U  G  E  O  D  V  U  H  L  L  G  V  F  D  V  V  V  V  
                C  C  A  A  N  A  E  B  C  D  I  D  K  N  E  C  Y  C  E  E  E  
                E  K  S  L  D  0  P  G  C  S  P  S  1  D  D  0  F  C  D  D  D  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
   NINSLOW | 12                                                              74 | RESERVED 
       VCC | 13                                                              73 | RESERVED 
     EPFC1 | 14                                                              72 | GND 
     EPFC2 | 15                                                              71 | RESERVED 
    NCSSYS | 16                                                              70 | RESERVED 
      EPRW | 17                                                              69 | NEMVALID 
    BRKACK | 18                                                              68 | NUDSDLY 
       GND | 19                                                              67 | FLAGNOTRDY 
      EPAS | 20                                                              66 | VCC 
    NMHERE | 21                                                              65 | NLDSDLY 
     EXRDY | 22                        EPM7064LC84-10                        64 | NSTROBE 
    DLYLDS | 23                                                              63 | EPDTACK 
     DLYAS | 24                                                              62 | EPBG 
    NINSHI | 25                                                              61 | NMEMREQ 
       VCC | 26                                                              60 | NADVALID 
   NRDONLY | 27                                                              59 | GND 
    TGHOLD | 28                                                              58 | NINSJMP 
      EPGO | 29                                                              57 | NENPBD 
       BA0 | 30                                                              56 | NENRWSTB 
    ICERDY | 31                                                              55 | ICEBRK 
       GND | 32                                                              54 | NENVDH 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                N  E  D  N  E  V  N  N  N  G  V  N  N  N  G  D  D  N  N  N  V  
                S  P  L  E  P  C  E  E  E  N  C  D  E  E  N  I  I  S  E  E  C  
                T  A  Y  M  S  C  R  W  N  D  C  A  N  M  D  R  R  E  N  N  C  
                S  0  U  D  T     D  R  E        T  P  S     P  P  L  A  V     
                V     D  F  O           P        A  B  F     B  B  E  S  D     
                A     S  C  P           F        V  A  C     D  D  P  D  L     
                L                       C        A           L  H  F  S        
                I                                L                 C           
                D                                I                             
                                                 D                             


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     7/16( 43%)  16/16(100%)   0/16(  0%)   8/36( 22%) 
B:    LC17 - LC32    13/16( 81%)  16/16(100%)   1/16(  6%)  19/36( 52%) 
C:    LC33 - LC48    14/16( 87%)  16/16(100%)   1/16(  6%)  20/36( 55%) 
D:    LC49 - LC64    14/16( 87%)   8/16( 50%)   8/16( 50%)  21/36( 58%) 


Total dedicated input pins used:                 4/4    (100%)
Total I/O pins used:                            56/64   ( 87%)
Total logic cells used:                         48/64   ( 75%)
Total shareable expanders used:                  9/64   ( 14%)
Total Turbo logic cells used:                   48/64   ( 75%)
Total shareable expanders not available (n/a):   1/64   (  1%)

Total input pins required:                      30
Total output pins required:                     30
Total bidirectional pins required:               0
Total logic cells required:                     48
Total flipflops required:                       24
Total shareable expanders in database:           8

Synthesized logic cells:                         0/  64 (  0%)



Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  30   (26)  (B)      INPUT              0      0   0    0    0    1    0  BA0
  18    (4)  (A)      INPUT              0      0   0    0    0    1    0  BRKACK
   9   (12)  (A)      INPUT              0      0   0    0    0    1    0  CPENAS
  79   (62)  (D)      INPUT              0      0   0    0    0    1    0  DISNRDYF
  11   (10)  (A)      INPUT              0      0   0    0    0    7    0  EMUSPACE
  20    (3)  (A)      INPUT              0      0   0    0    0    5    3  EPAS
  62   (48)  (C)      INPUT              0      0   0    0    0    2    0  EPBG
  80   (63)  (D)      INPUT              0      0   0    0    0    3    0  EPFC0
  14    (8)  (A)      INPUT              0      0   0    0    0    3    0  EPFC1
  15    (7)  (A)      INPUT              0      0   0    0    0    3    0  EPFC2
  29   (27)  (B)      INPUT              0      0   0    0    0    1    0  EPGO
  84      -   -       INPUT              0      0   0    0    0    8    9  EPLDS
  17    (5)  (A)      INPUT              0      0   0    0    0   10    0  EPRW
  37   (20)  (B)      INPUT              0      0   0    0    0    2    0  EPSTOP
   2      -   -       INPUT              0      0   0    0    0    8    9  EPUDS
  22    (1)  (A)      INPUT              0      0   0    0    0    1    6  EXRDY
  55   (42)  (C)      INPUT              0      0   0    0    0    1    0  ICEBRK
  83      -   -       INPUT              0      0   0    0    0    2    3  ICECLK1 (U24)
  10   (11)  (A)      INPUT              0      0   0    0    0    1    1  ICEDTACK
  31   (25)  (B)      INPUT              0      0   0    0    0    0    6  ICERDY
   5   (15)  (A)      INPUT              0      0   0    0    0    2    0  ISOEP
  16    (6)  (A)      INPUT              0      0   0    0    0    0    5  NCSSYS
  36   (21)  (B)      INPUT              0      0   0    0    0    1    0  NEMDFC
  46   (35)  (C)      INPUT              0      0   0    0    0    1    0  NEMSFC
  25   (30)  (B)      INPUT              0      0   0    0    0    2    0  NINSHI
  12    (9)  (A)      INPUT              0      0   0    0    0    2    0  NINSLOW
  21    (2)  (A)      INPUT              0      0   0    0    0    5    6  NMHERE
  27   (29)  (B)      INPUT              0      0   0    0    0    3    0  NRDONLY
   1      -   -       INPUT              0      0   0    0    0    6    6  ONCHIP
   8   (13)  (A)      INPUT              0      0   0    0    0    1    0  QUAL


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4     16    A         FF  +  t        0      0   0    2    1    0    0  BONDBG (|7474:U22|:9)
  49     37    C     OUTPUT     t        0      0   0    5    0    0    0  DIRPBDH
  48     36    C     OUTPUT     t        0      0   0    5    0    0    0  DIRPBDL
  24     31    B     OUTPUT     t        0      0   0    2    2    0    0  DLYAS
  23     32    B     OUTPUT     t        0      0   0    2    2    0    0  DLYLDS
  35     22    B     OUTPUT     t        0      0   0    2    2    0    0  DLYUDS
  34     23    B     OUTPUT     t        0      0   0    3    2    0    0  EPA0
  63     49    D     OUTPUT     t        0      0   0    1    1    0    0  EPDTACK
  67     52    D         FF  +  t        0      0   0    2    6    1    0  FLAGNOTRDY (|7474:U43|:9)
   6     14    A     OUTPUT     t        0      0   0    2    2    0    0  MEA0
  60     46    C     OUTPUT     t        0      0   0    1    1    0    0  NADVALID
  44     33    C         FF  +  t        0      0   0    0    2    1    0  NDATAVALID (|7474:U32|:9)
  69     54    D     OUTPUT     t        0      0   0    2    2    0    0  NEMVALID
  51     39    C     OUTPUT     t        0      0   0    9    1    0    0  NENASDS
  41     17    B     OUTPUT     t        0      0   0    2    0    0    0  NENEPFC
  45     34    C     OUTPUT     t        0      0   0    1    0    0    0  NENPBA
  57     44    C     OUTPUT     t        0      0   0    4    1    0    0  NENPBD
  56     43    C     OUTPUT     t        0      0   0    2    1    0    0  NENRWSTB
  54     41    C     OUTPUT     t        0      0   0    6    0    0    0  NENVDH
  52     40    C     OUTPUT     t        0      0   0    6    0    0    0  NENVDL
  39     19    B     OUTPUT     t        0      0   0    3    1    0    0  NERD
  40     18    B     OUTPUT     t        0      0   0    3    1    0    0  NEWR
  58     45    C     OUTPUT     t        0      0   0    1    1    0    0  NINSJMP
  65     51    D         FF     t        0      0   0    2    1    0    0  NLDSDLY (|7474:U18|:10)
  61     47    C     OUTPUT     t        0      0   0    5    1    0    0  NMEMREQ
  50     38    C     OUTPUT     t        0      0   0    4    0    0    0  NSELEPFC
  64     50    D     OUTPUT     t        0      0   0    2    1    0    0  NSTROBE
  33     24    B     OUTPUT     t        0      0   0    1    1    0    0  NSTSVALID
  68     53    D         FF     t        0      0   0    2    1    0    0  NUDSDLY (|7474:U18|:9)
  28     28    B         FF  +  t !      0      0   0    2    1   14    2  TGHOLD (|7474:U22|:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (37)    20    B       DFFE  +  t        1      1   0    1    1    0    1  SLOAS_4 (|7474:U22|:10)
 (74)    58    D       DFFE     t        0      0   0    2    2    1    1  N00032 (|7474:U25|:9)
 (73)    57    D       DFFE  +  t        0      0   0    2    0    1    0  N00028 (|7474:U25|:10)
 (55)    42    C       DFFE  +  t        1      1   0    1    2    1    0  N00034 (|7474:U32|:10)
 (77)    61    D       DFFE  +  t        2      0   1    6    6    1    2  N00007 (|7474:U43|:10)
 (71)    56    D       TFFE  +  t        6      6   0    7    0    1    5  TC0_2 (|7474:U54|:9)
 (80)    63    D       TFFE  +  t        6      6   0    7    1    1    4  TC1_2 (|7474:U54|:10)
 (76)    60    D       TFFE  +  t        6      6   0    7    2    1    3  TC2_2 (|7474:U55|:9)
 (75)    59    D       TFFE  +  t        6      6   0    7    3    1    2  TC3_2 (|7474:U55|:10)
 (70)    55    D       TFFE  +  t        6      6   0    7    4    1    1  TC4_2 (|7474:U56|:9)
 (22)     1    A       DFFE  +  t        0      0   0    1    0    1    1  N00049 (|7474:U67|:9)
 (25)    30    B       DFFE  +  t        0      0   0    0    1    1    0  N00051 (|7474:U67|:10)
 (10)    11    A       DFFE  +  t        0      0   0    1    0    1    1  N00053 (|7474:U70|:9)
 (29)    27    B       DFFE  +  t        0      0   0    0    1    1    0  N00055 (|7474:U70|:10)
 (11)    10    A       DFFE  +  t        0      0   0    1    0    1    1  N00056 (|7474:U73|:9)
 (31)    25    B       DFFE  +  t        0      0   0    0    1    1    0  N00058 (|7474:U73|:10)
  (9)    12    A       DFFE     t        0      0   0    2    0    2    0  N00060 (|7474:U77|:9)
  (5)    15    A       DFFE     t        0      0   0    2    0    2    0  N00061 (|7474:U77|:10)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                       Logic cells placed in LAB 'A'
        +------------- LC16 BONDBG
        | +----------- LC14 MEA0
        | | +--------- LC1 N00049
        | | | +------- LC11 N00053
        | | | | +----- LC10 N00056
        | | | | | +--- LC12 N00060
        | | | | | | +- LC15 N00061
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | A B C D |     Logic cells that feed LAB 'A':
LC12 -> - * - - - - - | * * - - | <-- N00060
LC15 -> - * - - - - - | * * - - | <-- N00061

Pin
20   -> * - * - - - - | * * * - | <-- EPAS
62   -> * - - - - - - | * * - - | <-- EPBG
84   -> - * - - * * - | * * - * | <-- EPLDS
2    -> - * - * - - * | * * - * | <-- EPUDS
83   -> - - - - - * * | * - - * | <-- ICECLK1
1    -> - - - - - - - | - - * * | <-- ONCHIP
LC28 -> * - - - - - - | * * * * | <-- TGHOLD


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                   Logic cells placed in LAB 'B'
        +------------------------- LC31 DLYAS
        | +----------------------- LC32 DLYLDS
        | | +--------------------- LC22 DLYUDS
        | | | +------------------- LC23 EPA0
        | | | | +----------------- LC17 NENEPFC
        | | | | | +--------------- LC19 NERD
        | | | | | | +------------- LC18 NEWR
        | | | | | | | +----------- LC24 NSTSVALID
        | | | | | | | | +--------- LC28 TGHOLD
        | | | | | | | | | +------- LC20 SLOAS_4
        | | | | | | | | | | +----- LC30 N00051
        | | | | | | | | | | | +--- LC27 N00055
        | | | | | | | | | | | | +- LC25 N00058
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC28 -> - - - - - * * - * * - - - | * * * * | <-- TGHOLD
LC30 -> * - - - - - - - - - - - - | - * - - | <-- N00051
LC27 -> - - * - - - - - - - - - - | - * - - | <-- N00055
LC25 -> - * - - - - - - - - - - - | - * - - | <-- N00058

Pin
30   -> - - - * - - - - - - - - - | - * - - | <-- BA0
20   -> * - - - - - - - * * - - - | * * * - | <-- EPAS
62   -> - - - - - - - - * - - - - | * * - - | <-- EPBG
84   -> - * - * - * * - - - - - - | * * - * | <-- EPLDS
17   -> * * * - - * * - - - - - - | - * * - | <-- EPRW
2    -> - - * * - * * - - - - - - | * * - * | <-- EPUDS
83   -> - - - - - - - - - - - - - | * - - * | <-- ICECLK1
36   -> - - - - * - - - - - - - - | - * - - | <-- NEMDFC
46   -> - - - - * - - - - - - - - | - * - - | <-- NEMSFC
1    -> - - - - - - - - - - - - - | - - * * | <-- ONCHIP
8    -> - - - - - - - * - - - - - | - * - - | <-- QUAL
LC42 -> - - - - - - - * - - - - - | - * - - | <-- N00034
LC1  -> * - - - - - - - - - * - - | - * - - | <-- N00049
LC11 -> - - * - - - - - - - - * - | - * - - | <-- N00053
LC10 -> - * - - - - - - - - - - * | - * - - | <-- N00056
LC12 -> - - - * - - - - - - - - - | * * - - | <-- N00060
LC15 -> - - - * - - - - - - - - - | * * - - | <-- N00061


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                     Logic cells placed in LAB 'C'
        +--------------------------- LC37 DIRPBDH
        | +------------------------- LC36 DIRPBDL
        | | +----------------------- LC46 NADVALID
        | | | +--------------------- LC33 NDATAVALID
        | | | | +------------------- LC39 NENASDS
        | | | | | +----------------- LC34 NENPBA
        | | | | | | +--------------- LC44 NENPBD
        | | | | | | | +------------- LC43 NENRWSTB
        | | | | | | | | +----------- LC41 NENVDH
        | | | | | | | | | +--------- LC40 NENVDL
        | | | | | | | | | | +------- LC45 NINSJMP
        | | | | | | | | | | | +----- LC47 NMEMREQ
        | | | | | | | | | | | | +--- LC38 NSELEPFC
        | | | | | | | | | | | | | +- LC42 N00034
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC33 -> - - - * - - - - - - - - - - | - - * - | <-- NDATAVALID

Pin
18   -> - - - - * - - - - - - - - - | - - * - | <-- BRKACK
9    -> - - - - * - - - - - - - - - | - - * - | <-- CPENAS
11   -> * * - - * - - * * * - * - - | - - * - | <-- EMUSPACE
20   -> - - * - - - * - - - - - - * | * * * - | <-- EPAS
80   -> - - - - * - - - - - - * * - | - - * - | <-- EPFC0
14   -> - - - - * - - - - - - * * - | - - * - | <-- EPFC1
15   -> - - - - * - - - - - - * * - | - - * - | <-- EPFC2
84   -> - - - - - - - - - - - - - - | * * - * | <-- EPLDS
17   -> * * - - - - * - * * - - - - | - * * - | <-- EPRW
37   -> - - - - - - * - - - * - - - | - - * - | <-- EPSTOP
2    -> - - - - - - - - - - - - - - | * * - * | <-- EPUDS
22   -> - - - - * - - - - - - - - - | - - * * | <-- EXRDY
55   -> - - - - - - - - - - - - * - | - - * - | <-- ICEBRK
83   -> - - - - - - - - - - - - - - | * - - * | <-- ICECLK1
5    -> - - - - - * * - - - - - - - | - - * - | <-- ISOEP
25   -> - * - - - - - - * - - - - - | - - * - | <-- NINSHI
12   -> * - - - - - - - - * - - - - | - - * - | <-- NINSLOW
21   -> * * - - * - - - * * - - - - | - - * * | <-- NMHERE
27   -> - - - - - - - * * * - - - - | - - * - | <-- NRDONLY
1    -> * * - - * - - - * * - * - - | - - * * | <-- ONCHIP
LC28 -> - - * - * - * * - - * * - * | * * * * | <-- TGHOLD
LC58 -> - - - * - - - - - - - - - * | - - * - | <-- N00032


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                     Logic cells placed in LAB 'D'
        +--------------------------- LC49 EPDTACK
        | +------------------------- LC52 FLAGNOTRDY
        | | +----------------------- LC54 NEMVALID
        | | | +--------------------- LC51 NLDSDLY
        | | | | +------------------- LC50 NSTROBE
        | | | | | +----------------- LC53 NUDSDLY
        | | | | | | +--------------- LC58 N00032
        | | | | | | | +------------- LC57 N00028
        | | | | | | | | +----------- LC61 N00007
        | | | | | | | | | +--------- LC56 TC0_2
        | | | | | | | | | | +------- LC63 TC1_2
        | | | | | | | | | | | +----- LC60 TC2_2
        | | | | | | | | | | | | +--- LC59 TC3_2
        | | | | | | | | | | | | | +- LC55 TC4_2
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC52 -> - * - - - - - - - - - - - - | - - - * | <-- FLAGNOTRDY
LC57 -> - - * - - - - - - - - - - - | - - - * | <-- N00028
LC61 -> * - - - - - * - * - - - - - | - - - * | <-- N00007
LC56 -> - * - - - - - - * * * * * * | - - - * | <-- TC0_2
LC63 -> - * - - - - - - * - * * * * | - - - * | <-- TC1_2
LC60 -> - * - - - - - - * - - * * * | - - - * | <-- TC2_2
LC59 -> - * - - - - - - * - - - * * | - - - * | <-- TC3_2
LC55 -> - * - - - - - - * - - - - * | - - - * | <-- TC4_2

Pin
79   -> - * - - - - - - - - - - - - | - - - * | <-- DISNRDYF
29   -> - * - - - - - - - - - - - - | - - - * | <-- EPGO
84   -> - - * * * - - * * * * * * * | * * - * | <-- EPLDS
2    -> - - * - * * - * * * * * * * | * * - * | <-- EPUDS
22   -> - - - - - - - - * * * * * * | - - * * | <-- EXRDY
83   -> - - - * - * * - - - - - - - | * - - * | <-- ICECLK1
10   -> * - - - - - * - - - - - - - | - - - * | <-- ICEDTACK
31   -> - - - - - - - - * * * * * * | - - - * | <-- ICERDY
16   -> - - - - - - - - - * * * * * | - - - * | <-- NCSSYS
21   -> - - - - - - - - * * * * * * | - - * * | <-- NMHERE
1    -> - - - - - - - - * * * * * * | - - * * | <-- ONCHIP
LC28 -> - - * * * * - - - - - - - - | * * * * | <-- TGHOLD
LC20 -> - - - - - - * - - - - - - - | - - - * | <-- SLOAS_4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\hd328\hd328.rpt
HD328

** EQUATIONS **

BA0      : INPUT;
BRKACK   : INPUT;
CPENAS   : INPUT;
DISNRDYF : INPUT;
EMUSPACE : INPUT;
EPAS     : INPUT;
EPBG     : INPUT;
EPFC0    : INPUT;
EPFC1    : INPUT;
EPFC2    : INPUT;
EPGO     : INPUT;
EPLDS    : INPUT;
EPRW     : INPUT;
EPSTOP   : INPUT;
EPUDS    : INPUT;
EXRDY    : INPUT;
ICEBRK   : INPUT;
ICECLK1  : INPUT;
ICEDTACK : INPUT;
ICERDY   : INPUT;
ISOEP    : INPUT;
NCSSYS   : INPUT;
NEMDFC   : INPUT;
NEMSFC   : INPUT;
NINSHI   : INPUT;
NINSLOW  : INPUT;
NMHERE   : INPUT;
NRDONLY  : INPUT;
ONCHIP   : INPUT;
QUAL     : INPUT;

-- Node name is 'BONDBG' = '|7474~U22.1q~1' 
-- Equation name is 'BONDBG', type is output 
 BONDBG  = DFFE( _EQ001 $  GND, GLOBAL( ICECLK1),  VCC, !EPBG,  VCC);
  _EQ001 = !EPAS & !TGHOLD;

-- Node name is 'DIRPBDH' 
-- Equation name is 'DIRPBDH', location is LC037, type is output.
 DIRPBDH = LCELL( _EQ002 $ !EPRW);
  _EQ002 =  EMUSPACE &  EPRW &  NINSLOW &  ONCHIP
         #  EMUSPACE &  EPRW &  NINSLOW &  NMHERE;

-- Node name is 'DIRPBDL' 
-- Equation name is 'DIRPBDL', location is LC036, type is output.
 DIRPBDL = LCELL( _EQ003 $ !EPRW);
  _EQ003 =  EMUSPACE &  EPRW &  NINSHI &  ONCHIP
         #  EMUSPACE &  EPRW &  NINSHI &  NMHERE;

-- Node name is 'DLYAS' 
-- Equation name is 'DLYAS', location is LC031, type is output.
 DLYAS   = LCELL( _EQ004 $  VCC);
  _EQ004 = !EPAS &  EPRW & !N00049
         # !EPAS & !N00049 & !N00051;

-- Node name is 'DLYLDS' 
-- Equation name is 'DLYLDS', location is LC032, type is output.
 DLYLDS  = LCELL( _EQ005 $  VCC);
  _EQ005 = !EPLDS &  EPRW & !N00056
         # !EPLDS & !N00056 & !N00058;

-- Node name is 'DLYUDS' 
-- Equation name is 'DLYUDS', location is LC022, type is output.
 DLYUDS  = LCELL( _EQ006 $  VCC);
  _EQ006 =  EPRW & !EPUDS & !N00053
         # !EPUDS & !N00053 & !N00055;

-- Node name is 'EPA0' 
-- Equation name is 'EPA0', location is LC023, type is output.
 EPA0    = LCELL( _EQ007 $  BA0);
  _EQ007 = !BA0 &  EPUDS & !N00060 &  N00061
         # !BA0 & !EPLDS &  EPUDS &  N00061;

-- Node name is 'EPDTACK' 
-- Equation name is 'EPDTACK', location is LC049, type is output.
 EPDTACK = LCELL( _EQ008 $  GND);
  _EQ008 =  ICEDTACK & !N00007;

-- Node name is 'FLAGNOTRDY' = '|7474:U43.1q' 
-- Equation name is 'FLAGNOTRDY', type is output 
 FLAGNOTRDY = TFFE( _EQ009, GLOBAL( ICECLK1), !EPGO,  VCC,  VCC);
  _EQ009 = !DISNRDYF & !FLAGNOTRDY &  TC0_2 &  TC1_2 &  TC2_2 &  TC3_2 & 
              TC4_2;

-- Node name is 'MEA0' 
-- Equation name is 'MEA0', location is LC014, type is output.
 MEA0    = LCELL( _EQ010 $  GND);
  _EQ010 =  EPUDS & !N00060 &  N00061
         # !EPLDS &  EPUDS &  N00061;

-- Node name is 'NADVALID' 
-- Equation name is 'NADVALID', location is LC046, type is output.
 NADVALID = LCELL( _EQ011 $  VCC);
  _EQ011 = !EPAS & !TGHOLD;

-- Node name is 'NDATAVALID' = '|7474:U32.1q' 
-- Equation name is 'NDATAVALID', type is output 
 NDATAVALID = DFFE( _EQ012 $  VCC, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);
  _EQ012 =  NDATAVALID & !N00032;

-- Node name is 'NEMVALID' 
-- Equation name is 'NEMVALID', location is LC054, type is output.
 NEMVALID = LCELL( _EQ013 $  VCC);
  _EQ013 = !EPUDS & !N00028 & !TGHOLD
         # !EPLDS & !N00028 & !TGHOLD;

-- Node name is 'NENASDS' 
-- Equation name is 'NENASDS', location is LC039, type is output.
 NENASDS = LCELL( _EQ014 $  TGHOLD);
  _EQ014 =  BRKACK &  EPFC0 &  EPFC1 &  EPFC2 & !TGHOLD
         # !CPENAS & !EXRDY & !NMHERE & !ONCHIP & !TGHOLD
         # !CPENAS & !EMUSPACE & !TGHOLD;

-- Node name is 'NENEPFC' 
-- Equation name is 'NENEPFC', location is LC017, type is output.
 NENEPFC = LCELL( _EQ015 $  VCC);
  _EQ015 =  NEMDFC &  NEMSFC;

-- Node name is 'NENPBA' 
-- Equation name is 'NENPBA', location is LC034, type is output.
 NENPBA  = LCELL( ISOEP $  GND);

-- Node name is 'NENPBD' 
-- Equation name is 'NENPBD', location is LC044, type is output.
 NENPBD  = LCELL( _EQ016 $  VCC);
  _EQ016 = !EPRW & !EPSTOP & !ISOEP & !TGHOLD
         # !EPAS & !EPSTOP & !ISOEP & !TGHOLD;

-- Node name is 'NENRWSTB' 
-- Equation name is 'NENRWSTB', location is LC043, type is output.
 NENRWSTB = LCELL( _EQ017 $  VCC);
  _EQ017 =  EMUSPACE &  NRDONLY & !TGHOLD;

-- Node name is 'NENVDH' 
-- Equation name is 'NENVDH', location is LC041, type is output.
 NENVDH  = LCELL( _EQ018 $ !EMUSPACE);
  _EQ018 =  EMUSPACE & !EPRW & !NRDONLY
         #  EMUSPACE & !NMHERE & !ONCHIP
         #  EMUSPACE & !NINSHI;

-- Node name is 'NENVDL' 
-- Equation name is 'NENVDL', location is LC040, type is output.
 NENVDL  = LCELL( _EQ019 $ !EMUSPACE);
  _EQ019 =  EMUSPACE & !EPRW & !NRDONLY
         #  EMUSPACE & !NMHERE & !ONCHIP
         #  EMUSPACE & !NINSLOW;

-- Node name is 'NERD' 
-- Equation name is 'NERD', location is LC019, type is output.
 NERD    = LCELL( _EQ020 $  VCC);
  _EQ020 =  EPRW & !EPUDS & !TGHOLD
         # !EPLDS &  EPRW & !TGHOLD;

-- Node name is 'NEWR' 
-- Equation name is 'NEWR', location is LC018, type is output.
 NEWR    = LCELL( _EQ021 $  VCC);
  _EQ021 = !EPRW & !EPUDS & !TGHOLD
         # !EPLDS & !EPRW & !TGHOLD;

-- Node name is 'NINSJMP' 
-- Equation name is 'NINSJMP', location is LC045, type is output.
 NINSJMP = LCELL( _EQ022 $  VCC);
  _EQ022 =  EPSTOP & !TGHOLD;

-- Node name is 'NLDSDLY' = '|7474:U18.2q' 
-- Equation name is 'NLDSDLY', type is output 
 NLDSDLY = DFFE( GND $  VCC, !ICECLK1, !_EQ023,  VCC,  VCC);
  _EQ023 = !EPLDS & !TGHOLD;

-- Node name is 'NMEMREQ' 
-- Equation name is 'NMEMREQ', location is LC047, type is output.
 NMEMREQ = LCELL( _EQ024 $  VCC);
  _EQ024 =  EMUSPACE & !EPFC2 & !ONCHIP & !TGHOLD
         #  EMUSPACE & !EPFC1 & !ONCHIP & !TGHOLD
         #  EMUSPACE & !EPFC0 & !ONCHIP & !TGHOLD;

-- Node name is 'NSELEPFC' 
-- Equation name is 'NSELEPFC', location is LC038, type is output.
 NSELEPFC = LCELL( _EQ025 $  GND);
  _EQ025 =  EPFC0 &  EPFC1 &  EPFC2 &  ICEBRK;

-- Node name is 'NSTROBE' 
-- Equation name is 'NSTROBE', location is LC050, type is output.
 NSTROBE = LCELL( _EQ026 $  TGHOLD);
  _EQ026 =  EPLDS &  EPUDS & !TGHOLD;

-- Node name is 'NSTSVALID' 
-- Equation name is 'NSTSVALID', location is LC024, type is output.
 NSTSVALID = LCELL( _EQ027 $  GND);
  _EQ027 =  N00034 &  QUAL;

-- Node name is 'NUDSDLY' = '|7474:U18.1q' 
-- Equation name is 'NUDSDLY', type is output 
 NUDSDLY = DFFE( GND $  VCC, !ICECLK1, !_EQ028,  VCC,  VCC);
  _EQ028 = !EPUDS & !TGHOLD;

-- Node name is '|7474:U43|:10' = 'N00007' 
-- Equation name is 'N00007', location is LC061, type is buried.
N00007   = DFFE( _EQ029 $  GND, GLOBAL( ICECLK1), !_EQ030,  VCC,  VCC);
  _EQ029 =  TC0_2 &  TC1_2 &  TC2_2 &  TC3_2 &  TC4_2
         # !EXRDY & !NMHERE & !ONCHIP &  _X001
         #  ICERDY &  _X001
         #  N00007;
  _X001  = EXP(!TC2_2 & !TC3_2 & !TC4_2);
  _EQ030 =  EPLDS &  EPUDS;

-- Node name is '|7474:U25|:10' = 'N00028' 
-- Equation name is 'N00028', location is LC057, type is buried.
N00028   = DFFE( _EQ031 $  GND, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);
  _EQ031 =  EPLDS &  EPUDS;

-- Node name is '|7474:U25|:9' = 'N00032' 
-- Equation name is 'N00032', location is LC058, type is buried.
N00032   = DFFE( _EQ032 $  GND, !ICECLK1,  VCC,  SLOAS_4,  VCC);
  _EQ032 =  ICEDTACK & !N00007;

-- Node name is '|7474:U32|:10' = 'N00034' 
-- Equation name is 'N00034', location is LC042, type is buried.
N00034   = DFFE(!N00032 $  GND, GLOBAL( ICECLK1), !_EQ033,  VCC,  VCC);
  _EQ033 =  _X002;
  _X002  = EXP(!EPAS & !TGHOLD);

-- Node name is '|7474:U67|:9' = 'N00049' 
-- Equation name is 'N00049', location is LC001, type is buried.
N00049   = DFFE( EPAS $  GND, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);

-- Node name is '|7474:U67|:10' = 'N00051' 
-- Equation name is 'N00051', location is LC030, type is buried.
N00051   = DFFE( N00049 $  GND, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);

-- Node name is '|7474:U70|:9' = 'N00053' 
-- Equation name is 'N00053', location is LC011, type is buried.
N00053   = DFFE( EPUDS $  GND, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);

-- Node name is '|7474:U70|:10' = 'N00055' 
-- Equation name is 'N00055', location is LC027, type is buried.
N00055   = DFFE( N00053 $  GND, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);

-- Node name is '|7474:U73|:9' = 'N00056' 
-- Equation name is 'N00056', location is LC010, type is buried.
N00056   = DFFE( EPLDS $  GND, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);

-- Node name is '|7474:U73|:10' = 'N00058' 
-- Equation name is 'N00058', location is LC025, type is buried.
N00058   = DFFE( N00056 $  GND, GLOBAL( ICECLK1),  VCC,  VCC,  VCC);

-- Node name is '|7474:U77|:9' = 'N00060' 
-- Equation name is 'N00060', location is LC012, type is buried.
N00060   = DFFE( EPLDS $  GND, !ICECLK1,  VCC,  VCC,  VCC);

-- Node name is '|7474:U77|:10' = 'N00061' 
-- Equation name is 'N00061', location is LC015, type is buried.
N00061   = DFFE( EPUDS $  GND, !ICECLK1,  VCC,  VCC,  VCC);

-- Node name is '|7474:U22|:10' = 'SLOAS_4' 
-- Equation name is 'SLOAS_4', location is LC020, type is buried.
SLOAS_4  = DFFE( _EQ034 $  GND, GLOBAL( ICECLK1), !_EQ035,  VCC,  VCC);
  _EQ034 = !EPAS & !TGHOLD;
  _EQ035 =  _X002;
  _X002  = EXP(!EPAS & !TGHOLD);

-- Node name is '|7474:U54|:9' = 'TC0_2' 
-- Equation name is 'TC0_2', location is LC056, type is buried.
TC0_2    = TFFE( VCC, GLOBAL( ICECLK1), !_EQ036,  VCC,  VCC);
  _EQ036 =  _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008;
  _X003  = EXP(!EPUDS & !EXRDY & !NMHERE & !ONCHIP);
  _X004  = EXP(!EPLDS & !EXRDY & !NMHERE & !ONCHIP);
  _X005  = EXP(!EPLDS &  NCSSYS);
  _X006  = EXP(!EPLDS &  ICERDY);
  _X007  = EXP(!EPUDS &  NCSSYS);
  _X008  = EXP(!EPUDS &  ICERDY);

-- Node name is '|7474:U54|:10' = 'TC1_2' 
-- Equation name is 'TC1_2', location is LC063, type is buried.
TC1_2    = TFFE( TC0_2, GLOBAL( ICECLK1), !_EQ037,  VCC,  VCC);
  _EQ037 =  _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008;
  _X003  = EXP(!EPUDS & !EXRDY & !NMHERE & !ONCHIP);
  _X004  = EXP(!EPLDS & !EXRDY & !NMHERE & !ONCHIP);
  _X005  = EXP(!EPLDS &  NCSSYS);
  _X006  = EXP(!EPLDS &  ICERDY);
  _X007  = EXP(!EPUDS &  NCSSYS);
  _X008  = EXP(!EPUDS &  ICERDY);

-- Node name is '|7474:U55|:9' = 'TC2_2' 
-- Equation name is 'TC2_2', location is LC060, type is buried.
TC2_2    = TFFE( _EQ038, GLOBAL( ICECLK1), !_EQ039,  VCC,  VCC);
  _EQ038 =  TC0_2 &  TC1_2;
  _EQ039 =  _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008;
  _X003  = EXP(!EPUDS & !EXRDY & !NMHERE & !ONCHIP);
  _X004  = EXP(!EPLDS & !EXRDY & !NMHERE & !ONCHIP);
  _X005  = EXP(!EPLDS &  NCSSYS);
  _X006  = EXP(!EPLDS &  ICERDY);
  _X007  = EXP(!EPUDS &  NCSSYS);
  _X008  = EXP(!EPUDS &  ICERDY);

-- Node name is '|7474:U55|:10' = 'TC3_2' 
-- Equation name is 'TC3_2', location is LC059, type is buried.
TC3_2    = TFFE( _EQ040, GLOBAL( ICECLK1), !_EQ041,  VCC,  VCC);
  _EQ040 =  TC0_2 &  TC1_2 &  TC2_2;
  _EQ041 =  _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008;
  _X003  = EXP(!EPUDS & !EXRDY & !NMHERE & !ONCHIP);
  _X004  = EXP(!EPLDS & !EXRDY & !NMHERE & !ONCHIP);
  _X005  = EXP(!EPLDS &  NCSSYS);
  _X006  = EXP(!EPLDS &  ICERDY);
  _X007  = EXP(!EPUDS &  NCSSYS);
  _X008  = EXP(!EPUDS &  ICERDY);

-- Node name is '|7474:U56|:9' = 'TC4_2' 
-- Equation name is 'TC4_2', location is LC055, type is buried.
TC4_2    = TFFE( _EQ042, GLOBAL( ICECLK1), !_EQ043,  VCC,  VCC);
  _EQ042 =  TC0_2 &  TC1_2 &  TC2_2 &  TC3_2;
  _EQ043 =  _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008;
  _X003  = EXP(!EPUDS & !EXRDY & !NMHERE & !ONCHIP);
  _X004  = EXP(!EPLDS & !EXRDY & !NMHERE & !ONCHIP);
  _X005  = EXP(!EPLDS &  NCSSYS);
  _X006  = EXP(!EPLDS &  ICERDY);
  _X007  = EXP(!EPUDS &  NCSSYS);
  _X008  = EXP(!EPUDS &  ICERDY);

-- Node name is 'TGHOLD' = '|7474:U22.1q' 
-- Equation name is 'TGHOLD', type is output 
TGHOLD   = _LC028~NOT;
_LC028~NOT = DFFE( _EQ044 $  VCC, GLOBAL( ICECLK1), !EPBG,  VCC,  VCC);
  _EQ044 = !EPAS & !TGHOLD;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X002 occurs in LABs -BC-




Project Information                                         c:\hd328\hd328.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = Normal

      Logic option settings in 'Normal' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = off
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = off
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = off
      REFACTORIZATION                     = off
      REGISTER_OPTIMIZATION               = off
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = off
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = off
      Automatic Global Clear              = off
      Automatic Global Preset             = off
      Automatic Global Output Enable      = off
      Automatic I/O Cell Registers        = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,383K
