(is)pLSI Development System Plus Release 2.1.13, Jun  5 1995 10:02:40


Design Parameters
-----------------

IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16 ((is)pLSI1000,(is)pLSI2000), 24((is)pLSI3000)
MAX_GLB_OUT:                    4
STRATEGY:                       AREA


Design Specification
--------------------

Design:                         sio302
Part:                           ispLSI1016-60LJ44


Y1_AS_RESET:                    OFF


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          36


Input Pins

    Pin Name                Pin Attribute

        BUSW                    LOCK 30
        EMON                    LOCK 19
        EPAS                    LOCK 32
        ICEBRK                  LOCK 6
        NLOAD                   LOCK 4
        NRSTEP                  LOCK 7
        NTFRZ                   LOCK 44
        PSQ0                    LOCK 14
        PSQ1                    LOCK 15
        PSQ2                    LOCK 16
        PSQ3                    LOCK 17
        PSQ4                    LOCK 18
        PSQ5                    LOCK 36
        PSQ6                    LOCK 37
        PSQ7                    LOCK 24
        SCLK                    LOCK 11
        SIN                     LOCK 2
        TDISCPU                 LOCK 20


Output Pins

    Pin Name                Pin Attribute

        BMSK8                   LOCK 31
        CPENAS                  LOCK 40
        CPENDS                  LOCK 38
        DISRST                  LOCK 5
        EDISCPU                 LOCK 21
        NENBERR                 LOCK 3
        NENIPL                  LOCK 8
        NEPFRZ                  LOCK 43
        PDQ0                    LOCK 22
        PDQ1                    LOCK 25
        PDQ13                   LOCK 41
        PDQ14                   LOCK 42
        PDQ2                    LOCK 26
        PDQ3                    LOCK 27
        PDQ4                    LOCK 28
        PDQ5                    LOCK 29
        PDQ8                    LOCK 39
        SOUT                    LOCK 9


Pre-Route Design Statistics
---------------------------

Number of GLBs:                 16
Number of I/Os:                 35
Number of Nets:                 72

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    13
Number of Locked DIs:           4
Number of Locked Outputs:       18
Number of Locked Three-States:  0
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      1


GLB Utilization (Out of 16):	100%
I/O Utilization (Out of 36):	97%
Net Utilization (Out of 100):	72%


Nets with Fanout of  1:         47
Nets with Fanout of  2:         13
Nets with Fanout of  3:         8
Nets with Fanout of  4:         2
Nets with Fanout of 10:         1
Nets with Fanout of 11:         1

Average Fanout per Net:         1.75


GLBs with  2 Input(s):          1
GLBs with  5 Input(s):          5
GLBs with  6 Input(s):          1
GLBs with  7 Input(s):          1
GLBs with  8 Input(s):          4
GLBs with  9 Input(s):          4

Average Inputs per GLB:         6.75


GLBs with  1 Output(s):         1
GLBs with  2 Output(s):         1
GLBs with  3 Output(s):         2
GLBs with  4 Output(s):         12

Average Outputs per GLB:        3.56


Post-Route Design Implementation
--------------------------------

Number of GLBs:			16
Number of IOCs:			31
Number of DIs:			4
Number of GLB Levels:		1


GLB glb0, A1

    9 Input(s)
        (glb0.O2, BMSK8_PIN, I6), (BUSW.O, _PIN_BUSW, I13), (NLOAD.O, 
        _PIN_NLOAD, I9), (PSQ0.O, _PIN_PSQ0, I16), (PSQ2.O, 
        _PIN_PSQ2, I1), (PSQ3.O, _PIN_PSQ3, I2), (PSQ7.O, 
        _PIN_PSQ7, I17), (glb14.O2, Q1_Q, I14), (glb15.O0, Q6_Q, I12)
    4 Output(s)
        (Q7_Q, O0), (Q2_Q, O1), (Q0_Q, O3), (BMSK8_PIN, O2)
    8 Product Term(s)

    Output Q7_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ7, Q6_Q
        1 Fanout(s)
            glb14.I11
        2 Product Term(s)
        1 GLB Level(s)

        Q7_Q.D = (_PIN_PSQ7 & !_PIN_NLOAD
            # _PIN_NLOAD & Q6_Q)
        Q7_Q.C = _PIN_SCLK

    Output Q2_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ2, Q1_Q
        1 Fanout(s)
            glb14.I10
        2 Product Term(s)
        1 GLB Level(s)

        Q2_Q.D = (_PIN_PSQ2 & !_PIN_NLOAD
            # _PIN_NLOAD & Q1_Q)
        Q2_Q.C = _PIN_SCLK

    Output Q0_Q

        2 Input(s)
            _PIN_NLOAD, _PIN_PSQ0
        1 Fanout(s)
            glb14.I8
        2 Product Term(s)
        1 GLB Level(s)

        Q0_Q.D = (!_PIN_NLOAD & !_PIN_PSQ0)
            $ VCC
        Q0_Q.C = _PIN_SCLK

    Output BMSK8_PIN

        4 Input(s)
            BMSK8_PIN, _PIN_BUSW, _PIN_PSQ2, _PIN_PSQ3
        2 Fanout(s)
            glb0.I6, BMSK8.IR
        3 Product Term(s)
        1 GLB Level(s)

        BMSK8_PIN = (BMSK8_PIN & _PIN_PSQ2
            # BMSK8_PIN & _PIN_PSQ3
            # !_PIN_BUSW & !_PIN_PSQ2 & !_PIN_PSQ3)


GLB glb1, A4

    5 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I12), (glb3.O3, SQD0, I3), (glb10.O0, 
        SQD2, I0), (glb11.O0, SQD3, I8), (glb11.O2, SQD5, I10)
    4 Output(s)
        (PDQ5_PIN, O0), (PDQ3_PIN, O2), (PDQ2_PIN, O1), (PDQ0_PIN, O3)
    5 Product Term(s)

    Output PDQ5_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD5
        1 Fanout(s)
            PDQ5.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ5_PIN.D = SQD5
        PDQ5_PIN.C = _BUF_511
        PDQ5_PIN.R = !_PIN_NRSTEP

    Output PDQ3_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD3
        1 Fanout(s)
            PDQ3.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ3_PIN.D = SQD3
        PDQ3_PIN.C = _BUF_511
        PDQ3_PIN.R = !_PIN_NRSTEP

    Output PDQ2_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD2
        1 Fanout(s)
            PDQ2.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ2_PIN.D = SQD2
        PDQ2_PIN.C = _BUF_511
        PDQ2_PIN.R = !_PIN_NRSTEP

    Output PDQ0_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD0
        1 Fanout(s)
            PDQ0.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ0_PIN.D = SQD0
        PDQ0_PIN.C = _BUF_511
        PDQ0_PIN.R = !_PIN_NRSTEP


GLB glb10, A0

    8 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (NRSTEP.O, _PIN_NRSTEP, I12), 
        (glb9.O3, SQD1, I7), (glb9.O1, SQD11, I5), (glb10.O3, 
        SQD12, I3), (glb10.O1, SQD13, I1), (glb10.O2, SQD14, I2), 
        (glb10.O0, SQD2, I0)
    4 Output(s)
        (SQD2, O0), (SQD14, O2), (SQD13, O1), (SQD12, O3)
    9 Product Term(s)

    Output SQD2

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD1, SQD2
        3 Fanout(s)
            glb10.I0, glb1.I0, glb11.I15
        2 Product Term(s)
        1 GLB Level(s)

        SQD2.D = (_PIN_NLOAD & SQD1
            # SQD2 & !_PIN_NLOAD)
        SQD2.C = _PIN_SCLK
        SQD2.R = !_PIN_NRSTEP

    Output SQD14

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD13, SQD14
        3 Fanout(s)
            glb10.I2, glb11.I13, glb4.I13
        2 Product Term(s)
        1 GLB Level(s)

        SQD14.D = (_PIN_NLOAD & SQD13
            # SQD14 & !_PIN_NLOAD)
        SQD14.C = _PIN_SCLK
        SQD14.R = !_PIN_NRSTEP

    Output SQD13

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD12, SQD13
        2 Fanout(s)
            glb10.I1, glb7.I14
        2 Product Term(s)
        1 GLB Level(s)

        SQD13.D = (_PIN_NLOAD & SQD12
            # SQD13 & !_PIN_NLOAD)
        SQD13.C = _PIN_SCLK
        SQD13.R = !_PIN_NRSTEP

    Output SQD12

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD11, SQD12
        2 Fanout(s)
            glb10.I3, glb4.I12
        2 Product Term(s)
        1 GLB Level(s)

        SQD12.D = (_PIN_NLOAD & SQD11
            # SQD12 & !_PIN_NLOAD)
        SQD12.C = _PIN_SCLK
        SQD12.R = !_PIN_NRSTEP


GLB glb11, B2

    8 Input(s)
        (NLOAD.O, _PIN_NLOAD, I6), (NRSTEP.O, _PIN_NRSTEP, I3), 
        (glb10.O2, SQD14, I13), (glb11.O3, SQD15, I4), (glb10.O0, 
        SQD2, I15), (glb11.O0, SQD3, I7), (glb11.O1, SQD4, I16), 
        (glb11.O2, SQD5, I5)
    4 Output(s)
        (SQD5, O2), (SQD4, O1), (SQD3, O0), (SQD15, O3)
    9 Product Term(s)

    Output SQD5

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD4, SQD5
        3 Fanout(s)
            glb1.I10, glb12.I10, glb11.I5
        2 Product Term(s)
        1 GLB Level(s)

        SQD5.D = (_PIN_NLOAD & SQD4
            # SQD5 & !_PIN_NLOAD)
        SQD5.C = _PIN_SCLK
        SQD5.R = !_PIN_NRSTEP

    Output SQD4

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD3, SQD4
        2 Fanout(s)
            glb2.I9, glb11.I16
        2 Product Term(s)
        1 GLB Level(s)

        SQD4.D = (_PIN_NLOAD & SQD3
            # SQD4 & !_PIN_NLOAD)
        SQD4.C = _PIN_SCLK
        SQD4.R = !_PIN_NRSTEP

    Output SQD3

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD2, SQD3
        2 Fanout(s)
            glb1.I8, glb11.I7
        2 Product Term(s)
        1 GLB Level(s)

        SQD3.D = (_PIN_NLOAD & SQD2
            # SQD3 & !_PIN_NLOAD)
        SQD3.C = _PIN_SCLK
        SQD3.R = !_PIN_NRSTEP

    Output SQD15

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD14, SQD15
        2 Fanout(s)
            glb11.I4, glb7.I4
        2 Product Term(s)
        1 GLB Level(s)

        SQD15.D = (_PIN_NLOAD & SQD14
            # SQD15 & !_PIN_NLOAD)
        SQD15.C = _PIN_SCLK
        SQD15.R = !_PIN_NRSTEP


GLB glb12, A6

    6 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (NRSTEP.O, _PIN_NRSTEP, I12), 
        (glb11.O2, SQD5, I10), (glb12.O2, SQD6, I17), (glb12.O1, 
        SQD7, I16), (glb12.O0, SQD8, I8)
    3 Output(s)
        (SQD8, O0), (SQD7, O1), (SQD6, O2)
    7 Product Term(s)

    Output SQD8

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD7, SQD8
        3 Fanout(s)
            glb9.I8, glb12.I8, glb7.I7
        2 Product Term(s)
        1 GLB Level(s)

        SQD8.D = (_PIN_NLOAD & SQD7
            # SQD8 & !_PIN_NLOAD)
        SQD8.C = _PIN_SCLK
        SQD8.R = !_PIN_NRSTEP

    Output SQD7

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD6, SQD7
        2 Fanout(s)
            glb8.I9, glb12.I16
        2 Product Term(s)
        1 GLB Level(s)

        SQD7.D = (_PIN_NLOAD & SQD6
            # SQD7 & !_PIN_NLOAD)
        SQD7.C = _PIN_SCLK
        SQD7.R = !_PIN_NRSTEP

    Output SQD6

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD5, SQD6
        2 Fanout(s)
            glb2.I10, glb12.I17
        2 Product Term(s)
        1 GLB Level(s)

        SQD6.D = (_PIN_NLOAD & SQD5
            # SQD6 & !_PIN_NLOAD)
        SQD6.C = _PIN_SCLK
        SQD6.R = !_PIN_NRSTEP


GLB glb13, B4

    5 Input(s)
        (NLOAD.O, _PIN_NLOAD, I6), (glb5.O3, Q10_Q, I8), (glb13.O0, 
        Q11_Q, I15), (glb13.O1, Q12_Q, I14), (glb14.O0, Q8_Q, I3)
    4 Output(s)
        (Q9_Q, O2), (Q13_Q, O3), (Q12_Q, O1), (Q11_Q, O0)
    4 Product Term(s)

    Output Q9_Q

        2 Input(s)
            _PIN_NLOAD, Q8_Q
        1 Fanout(s)
            glb5.I13
        1 Product Term(s)
        1 GLB Level(s)

        Q9_Q.D = _PIN_NLOAD & Q8_Q
        Q9_Q.C = _PIN_SCLK

    Output Q13_Q

        2 Input(s)
            _PIN_NLOAD, Q12_Q
        1 Fanout(s)
            glb14.I12
        1 Product Term(s)
        1 GLB Level(s)

        Q13_Q.D = _PIN_NLOAD & Q12_Q
        Q13_Q.C = _PIN_SCLK

    Output Q12_Q

        2 Input(s)
            _PIN_NLOAD, Q11_Q
        1 Fanout(s)
            glb13.I14
        1 Product Term(s)
        1 GLB Level(s)

        Q12_Q.D = _PIN_NLOAD & Q11_Q
        Q12_Q.C = _PIN_SCLK

    Output Q11_Q

        2 Input(s)
            _PIN_NLOAD, Q10_Q
        1 Fanout(s)
            glb13.I15
        1 Product Term(s)
        1 GLB Level(s)

        Q11_Q.D = _PIN_NLOAD & Q10_Q
        Q11_Q.C = _PIN_SCLK


GLB glb14, B7

    7 Input(s)
        (NLOAD.O, _PIN_NLOAD, I6), (PSQ1.O, _PIN_PSQ1, I15), (PSQ3.O, 
        _PIN_PSQ3, I13), (glb0.O3, Q0_Q, I8), (glb13.O3, Q13_Q, I12), 
        (glb0.O1, Q2_Q, I10), (glb0.O0, Q7_Q, I11)
    4 Output(s)
        (Q8_Q, O0), (Q3_Q, O1), (Q1_Q, O2), (Q14_Q, O3)
    6 Product Term(s)

    Output Q8_Q

        2 Input(s)
            _PIN_NLOAD, Q7_Q
        1 Fanout(s)
            glb13.I3
        2 Product Term(s)
        1 GLB Level(s)

        Q8_Q.D = (_PIN_NLOAD & !Q7_Q)
            $ VCC
        Q8_Q.C = _PIN_SCLK

    Output Q3_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ3, Q2_Q
        1 Fanout(s)
            glb15.I13
        2 Product Term(s)
        1 GLB Level(s)

        Q3_Q.D = (_PIN_PSQ3 & !_PIN_NLOAD
            # _PIN_NLOAD & Q2_Q)
        Q3_Q.C = _PIN_SCLK

    Output Q1_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ1, Q0_Q
        1 Fanout(s)
            glb0.I14
        2 Product Term(s)
        1 GLB Level(s)

        Q1_Q.D = (_PIN_PSQ1 & !_PIN_NLOAD
            # _PIN_NLOAD & Q0_Q)
        Q1_Q.C = _PIN_SCLK

    Output Q14_Q

        2 Input(s)
            _PIN_NLOAD, Q13_Q
        1 Fanout(s)
            glb5.I0
        1 Product Term(s)
        1 GLB Level(s)

        Q14_Q.D = _PIN_NLOAD & Q13_Q
        Q14_Q.C = _PIN_SCLK


GLB glb15, A7

    5 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (PSQ4.O, _PIN_PSQ4, I3), (PSQ6.O, 
        _PIN_PSQ6, I0), (glb14.O1, Q3_Q, I13), (glb5.O1, Q5_Q, I5)
    2 Output(s)
        (Q6_Q, O0), (Q4_Q, O2)
    4 Product Term(s)

    Output Q6_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ6, Q5_Q
        1 Fanout(s)
            glb0.I12
        2 Product Term(s)
        1 GLB Level(s)

        Q6_Q.D = (_PIN_PSQ6 & !_PIN_NLOAD
            # _PIN_NLOAD & Q5_Q)
        Q6_Q.C = _PIN_SCLK

    Output Q4_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ4, Q3_Q
        1 Fanout(s)
            glb5.I1
        2 Product Term(s)
        1 GLB Level(s)

        Q4_Q.D = (_PIN_PSQ4 & !_PIN_NLOAD
            # _PIN_NLOAD & Q3_Q)
        Q4_Q.C = _PIN_SCLK


GLB glb2, A3

    9 Input(s)
        (glb2.O2, EDISCPU_PIN, I14), (EMON.O, _PIN_EMON, I4), 
        (NRSTEP.O, _PIN_NRSTEP, I12), (PSQ2.O, _PIN_PSQ2, I1), (PSQ3.O, 
        _PIN_PSQ3, I2), (glb9.O3, SQD1, I7), (glb11.O1, SQD4, I9), 
        (glb12.O2, SQD6, I10), (TDISCPU.O, _PIN_TDISCPU, I5)
    4 Output(s)
        (PDQ6, O1), (PDQ4_PIN, O3), (PDQ1_PIN, O0), (EDISCPU_PIN, O2)
    7 Product Term(s)

    Output PDQ6

        2 Input(s)
            _PIN_NRSTEP, SQD6
        1 Fanout(s)
            glb6.I2
        1 Product Term(s)
        1 GLB Level(s)

        PDQ6.D = SQD6
        PDQ6.C = _BUF_511
        PDQ6.R = !_PIN_NRSTEP

    Output PDQ4_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD4
        1 Fanout(s)
            PDQ4.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ4_PIN.D = SQD4
        PDQ4_PIN.C = _BUF_511
        PDQ4_PIN.R = !_PIN_NRSTEP

    Output PDQ1_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD1
        1 Fanout(s)
            PDQ1.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ1_PIN.D = SQD1
        PDQ1_PIN.C = _BUF_511
        PDQ1_PIN.R = !_PIN_NRSTEP

    Output EDISCPU_PIN

        5 Input(s)
            EDISCPU_PIN, _PIN_EMON, _PIN_PSQ2, _PIN_PSQ3, _PIN_TDISCPU
        2 Fanout(s)
            glb2.I14, EDISCPU.IR
        3 Product Term(s)
        1 GLB Level(s)

        EDISCPU_PIN = (EDISCPU_PIN & _PIN_PSQ2
            # EDISCPU_PIN & _PIN_PSQ3
            # _PIN_EMON & _PIN_TDISCPU & !_PIN_PSQ2 & !_PIN_PSQ3)


Clock GLB glb3, B0

    9 Input(s)
        (EMON.O, _PIN_EMON, I11), (EPAS.O, _PIN_EPAS, I0), (ICEBRK.O, 
        _PIN_ICEBRK, I4), (NLOAD.O, _PIN_NLOAD, I6), (NRSTEP.O, 
        _PIN_NRSTEP, I3), (glb4.O2, PDQ10, I1), (glb4.O1, 
        PDQ14_PIN, I2), (SIN.O, _PIN_SIN, I17), (glb3.O3, SQD0, I12)
    4 Output(s)
        (_OR_401, O2), (_BUF_511, O1), (_BUF_510, O0), (SQD0, O3)
    7 Product Term(s)

    Output _OR_401

        4 Input(s)
            _PIN_EMON, _PIN_ICEBRK, PDQ10, PDQ14_PIN
        1 Fanout(s)
            DISRST.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_401 = (!PDQ14_PIN
            # _PIN_EMON & PDQ10 & !_PIN_ICEBRK)

    Output _BUF_511

        1 Input(s)
            _PIN_NLOAD
        5 Fanout(s)
            glb8.CLK2, glb2.CLK2, glb1.CLK2, glb4.CLK2, glb7.CLK2
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_511 = _PIN_NLOAD

    Output _BUF_510

        1 Input(s)
            _PIN_EPAS
        1 Fanout(s)
            glb6.CLK1
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_510 = _PIN_EPAS

    Output SQD0

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, _PIN_SIN, SQD0
        3 Fanout(s)
            glb1.I3, glb9.I3, glb3.I12
        2 Product Term(s)
        1 GLB Level(s)

        SQD0.D = (_PIN_NLOAD & _PIN_SIN
            # SQD0 & !_PIN_NLOAD)
        SQD0.C = _PIN_SCLK
        SQD0.R = !_PIN_NRSTEP


GLB glb4, B3

    5 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I3), (glb9.O2, SQD10, I9), (glb9.O1, 
        SQD11, I10), (glb10.O3, SQD12, I12), (glb10.O2, SQD14, I13)
    4 Output(s)
        (PDQ14_PIN, O1), (PDQ12, O0), (PDQ11, O3), (PDQ10, O2)
    5 Product Term(s)

    Output PDQ14_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD14
        2 Fanout(s)
            glb3.I2, PDQ14.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ14_PIN.D = SQD14
        PDQ14_PIN.C = _BUF_511
        PDQ14_PIN.R = !_PIN_NRSTEP

    Output PDQ12

        2 Input(s)
            _PIN_NRSTEP, SQD12
        1 Fanout(s)
            glb5.I3
        1 Product Term(s)
        1 GLB Level(s)

        PDQ12.D = SQD12
        PDQ12.C = _BUF_511
        PDQ12.R = !_PIN_NRSTEP

    Output PDQ11

        2 Input(s)
            _PIN_NRSTEP, SQD11
        1 Fanout(s)
            glb6.I0
        1 Product Term(s)
        1 GLB Level(s)

        PDQ11.D = SQD11
        PDQ11.C = _BUF_511
        PDQ11.R = !_PIN_NRSTEP

    Output PDQ10

        2 Input(s)
            _PIN_NRSTEP, SQD10
        1 Fanout(s)
            glb3.I1
        1 Product Term(s)
        1 GLB Level(s)

        PDQ10.D = SQD10
        PDQ10.C = _BUF_511
        PDQ10.R = !_PIN_NRSTEP


GLB glb5, B1

    8 Input(s)
        (EMON.O, _PIN_EMON, I11), (ICEBRK.O, _PIN_ICEBRK, I4), 
        (NLOAD.O, _PIN_NLOAD, I6), (glb4.O0, PDQ12, I3), (PSQ5.O, 
        _PIN_PSQ5, I16), (glb14.O3, Q14_Q, I0), (glb15.O2, Q4_Q, I1), 
        (glb13.O2, Q9_Q, I13)
    4 Output(s)
        (_AND_460, O0), (SOUT_PIN, O2), (Q5_Q, O1), (Q10_Q, O3)
    5 Product Term(s)

    Output _AND_460

        3 Input(s)
            _PIN_EMON, _PIN_ICEBRK, PDQ12
        1 Fanout(s)
            NENBERR.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_460 = _PIN_EMON & PDQ12 & !_PIN_ICEBRK

    Output SOUT_PIN

        2 Input(s)
            _PIN_NLOAD, Q14_Q
        1 Fanout(s)
            SOUT.IR
        1 Product Term(s)
        1 GLB Level(s)

        SOUT_PIN.D = _PIN_NLOAD & Q14_Q
        SOUT_PIN.C = _PIN_SCLK

    Output Q5_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ5, Q4_Q
        1 Fanout(s)
            glb15.I5
        2 Product Term(s)
        1 GLB Level(s)

        Q5_Q.D = (_PIN_PSQ5 & !_PIN_NLOAD
            # _PIN_NLOAD & Q4_Q)
        Q5_Q.C = _PIN_SCLK

    Output Q10_Q

        2 Input(s)
            _PIN_NLOAD, Q9_Q
        1 Fanout(s)
            glb13.I8
        2 Product Term(s)
        1 GLB Level(s)

        Q10_Q.D = (_PIN_NLOAD & !Q9_Q)
            $ VCC
        Q10_Q.C = _PIN_SCLK


GLB glb6, B5

    9 Input(s)
        (EMON.O, _PIN_EMON, I11), (NRSTEP.O, _PIN_NRSTEP, I3), 
        (NTFRZ.O, _PIN_NTFRZ, I8), (glb4.O3, PDQ11, I0), (glb7.O3, 
        PDQ15, I4), (glb2.O1, PDQ6, I2), (glb8.O0, PDQ7, I7), (PSQ2.O, 
        _PIN_PSQ2, I14), (PSQ3.O, _PIN_PSQ3, I13)
    3 Output(s)
        (_OR_463, O2), (CPENDS_PIN, O1), (CPENAS_PIN, O3)
    7 Product Term(s)

    Output _OR_463

        6 Input(s)
            _PIN_EMON, _PIN_NTFRZ, PDQ11, PDQ15, _PIN_PSQ2, _PIN_PSQ3
        1 Fanout(s)
            NEPFRZ.IR
        4 Product Term(s)
        1 GLB Level(s)

        _OR_463 = (_PIN_EMON & _PIN_NTFRZ
            # PDQ11 & !_PIN_EMON
            # !_PIN_PSQ2 & !_PIN_PSQ3
            # _PIN_EMON & !PDQ15)

    Output CPENDS_PIN

        2 Input(s)
            _PIN_NRSTEP, PDQ7
        1 Fanout(s)
            CPENDS.IR
        1 Product Term(s)
        1 GLB Level(s)

        CPENDS_PIN.D = PDQ7
        CPENDS_PIN.C = _BUF_510
        CPENDS_PIN.R = !_PIN_NRSTEP

    Output CPENAS_PIN

        2 Input(s)
            _PIN_NRSTEP, PDQ6
        1 Fanout(s)
            CPENAS.IR
        1 Product Term(s)
        1 GLB Level(s)

        CPENAS_PIN.D = PDQ6
        CPENAS_PIN.C = _BUF_510
        CPENAS_PIN.R = !_PIN_NRSTEP


GLB glb7, B6

    5 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I3), (glb10.O1, SQD13, I14), (glb11.O3, 
        SQD15, I4), (glb12.O0, SQD8, I7), (glb9.O0, SQD9, I11)
    4 Output(s)
        (PDQ9, O1), (PDQ8_PIN, O2), (PDQ15, O3), (PDQ13_PIN, O0)
    5 Product Term(s)

    Output PDQ9

        2 Input(s)
            _PIN_NRSTEP, SQD9
        1 Fanout(s)
            NENIPL.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ9.D = SQD9
        PDQ9.C = _BUF_511
        PDQ9.R = !_PIN_NRSTEP

    Output PDQ8_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD8
        1 Fanout(s)
            PDQ8.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ8_PIN.D = SQD8
        PDQ8_PIN.C = _BUF_511
        PDQ8_PIN.R = !_PIN_NRSTEP

    Output PDQ15

        2 Input(s)
            _PIN_NRSTEP, SQD15
        1 Fanout(s)
            glb6.I4
        1 Product Term(s)
        1 GLB Level(s)

        PDQ15.D = SQD15
        PDQ15.C = _BUF_511
        PDQ15.R = !_PIN_NRSTEP

    Output PDQ13_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD13
        1 Fanout(s)
            PDQ13.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ13_PIN.D = SQD13
        PDQ13_PIN.C = _BUF_511
        PDQ13_PIN.R = !_PIN_NRSTEP


GLB glb8, A2

    2 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I12), (glb12.O1, SQD7, I9)
    1 Output(s)
        (PDQ7, O0)
    2 Product Term(s)

    Output PDQ7

        2 Input(s)
            _PIN_NRSTEP, SQD7
        1 Fanout(s)
            glb6.I7
        1 Product Term(s)
        1 GLB Level(s)

        PDQ7.D = SQD7
        PDQ7.C = _BUF_511
        PDQ7.R = !_PIN_NRSTEP


GLB glb9, A5

    8 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (NRSTEP.O, _PIN_NRSTEP, I12), 
        (glb3.O3, SQD0, I3), (glb9.O3, SQD1, I7), (glb9.O2, 
        SQD10, I6), (glb9.O1, SQD11, I5), (glb12.O0, SQD8, I8), 
        (glb9.O0, SQD9, I4)
    4 Output(s)
        (SQD9, O0), (SQD11, O1), (SQD10, O2), (SQD1, O3)
    9 Product Term(s)

    Output SQD9

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD8, SQD9
        2 Fanout(s)
            glb9.I4, glb7.I11
        2 Product Term(s)
        1 GLB Level(s)

        SQD9.D = (_PIN_NLOAD & SQD8
            # SQD9 & !_PIN_NLOAD)
        SQD9.C = _PIN_SCLK
        SQD9.R = !_PIN_NRSTEP

    Output SQD11

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD10, SQD11
        3 Fanout(s)
            glb10.I5, glb9.I5, glb4.I10
        2 Product Term(s)
        1 GLB Level(s)

        SQD11.D = (_PIN_NLOAD & SQD10
            # SQD11 & !_PIN_NLOAD)
        SQD11.C = _PIN_SCLK
        SQD11.R = !_PIN_NRSTEP

    Output SQD10

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD10, SQD9
        2 Fanout(s)
            glb9.I6, glb4.I9
        2 Product Term(s)
        1 GLB Level(s)

        SQD10.D = (SQD10 & !_PIN_NLOAD
            # _PIN_NLOAD & SQD9)
        SQD10.C = _PIN_SCLK
        SQD10.R = !_PIN_NRSTEP

    Output SQD1

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD0, SQD1
        3 Fanout(s)
            glb10.I7, glb2.I7, glb9.I7
        2 Product Term(s)
        1 GLB Level(s)

        SQD1.D = (_PIN_NLOAD & SQD0
            # SQD1 & !_PIN_NLOAD)
        SQD1.C = _PIN_SCLK
        SQD1.R = !_PIN_NRSTEP


Output BMSK8, IO14

    Input (glb0.O2, BMSK8_PIN)

    BMSK8 = BMSK8_PIN


Input BUSW, IO13

    Output _PIN_BUSW
        1 Fanout(s)
            glb0.I13


Output CPENAS, IO19

    Input (glb6.O3, CPENAS_PIN)

    CPENAS = CPENAS_PIN


Output CPENDS, IO17

    Input (glb6.O1, CPENDS_PIN)

    CPENDS = CPENDS_PIN


Output DISRST, IO26

    Input (glb3.O2, _OR_401)

    DISRST = !_OR_401


Output EDISCPU, IO6

    Input (glb2.O2, EDISCPU_PIN)

    EDISCPU = EDISCPU_PIN


Input EMON, IO4

    Output _PIN_EMON
        4 Fanout(s)
            glb2.I4, glb3.I11, glb5.I11, glb6.I11


Input EPAS, IO15

    Output _PIN_EPAS
        1 Fanout(s)
            glb3.I0


Input ICEBRK, IO27

    Output _PIN_ICEBRK
        2 Fanout(s)
            glb3.I4, glb5.I4


Output NENBERR, IO24

    Input (glb5.O0, _AND_460)

    NENBERR = !_AND_460


Output NENIPL, IO29

    Input (glb7.O1, PDQ9)

    NENIPL = !PDQ9


Output NEPFRZ, IO22

    Input (glb6.O2, _OR_463)

    NEPFRZ = _OR_463


Input NLOAD, IO25

    Output _PIN_NLOAD
        10 Fanout(s)
            glb10.I9, glb0.I9, glb9.I9, glb12.I9, glb15.I9, glb3.I6,
            glb5.I6, glb11.I6, glb13.I6, glb14.I6


Input NRSTEP, IO28

    Output _PIN_NRSTEP
        11 Fanout(s)
            glb10.I12, glb8.I12, glb2.I12, glb1.I12, glb9.I12, glb12.I12,
            glb3.I3, glb11.I3, glb4.I3, glb6.I3, glb7.I3


Input NTFRZ, IO23

    Output _PIN_NTFRZ
        1 Fanout(s)
            glb6.I8


Output PDQ0, IO7

    Input (glb1.O3, PDQ0_PIN)

    PDQ0 = PDQ0_PIN


Output PDQ1, IO8

    Input (glb2.O0, PDQ1_PIN)

    PDQ1 = PDQ1_PIN


Output PDQ13, IO20

    Input (glb7.O0, PDQ13_PIN)

    PDQ13 = PDQ13_PIN


Output PDQ14, IO21

    Input (glb4.O1, PDQ14_PIN)

    PDQ14 = PDQ14_PIN


Output PDQ2, IO9

    Input (glb1.O1, PDQ2_PIN)

    PDQ2 = PDQ2_PIN


Output PDQ3, IO10

    Input (glb1.O2, PDQ3_PIN)

    PDQ3 = PDQ3_PIN


Output PDQ4, IO11

    Input (glb2.O3, PDQ4_PIN)

    PDQ4 = PDQ4_PIN


Output PDQ5, IO12

    Input (glb1.O0, PDQ5_PIN)

    PDQ5 = PDQ5_PIN


Output PDQ8, IO18

    Input (glb7.O2, PDQ8_PIN)

    PDQ8 = PDQ8_PIN


Dedicated Input PSQ0, I0

    Output _PIN_PSQ0
        1 Fanout(s)
            glb0.I16


Input PSQ1, IO0

    Output _PIN_PSQ1
        1 Fanout(s)
            glb14.I15


Input PSQ2, IO1

    Output _PIN_PSQ2
        3 Fanout(s)
            glb0.I1, glb2.I1, glb6.I14


Input PSQ3, IO2

    Output _PIN_PSQ3
        4 Fanout(s)
            glb0.I2, glb2.I2, glb6.I13, glb14.I13


Input PSQ4, IO3

    Output _PIN_PSQ4
        1 Fanout(s)
            glb15.I3


Dedicated Input PSQ5, I2

    Output _PIN_PSQ5
        1 Fanout(s)
            glb5.I16


Input PSQ6, IO16

    Output _PIN_PSQ6
        1 Fanout(s)
            glb15.I0


Dedicated Input PSQ7, I1

    Output _PIN_PSQ7
        1 Fanout(s)
            glb0.I17


Clock Input SCLK, Y0

    Output _PIN_SCLK
        10 Fanout(s)
            glb10.CLK0, glb0.CLK0, glb9.CLK0, glb12.CLK0, glb15.CLK0,
            glb3.CLK0, glb5.CLK0, glb11.CLK0, glb13.CLK0, glb14.CLK0


Dedicated Input SIN, I3

    Output _PIN_SIN
        1 Fanout(s)
            glb3.I17


Output SOUT, IO30

    Input (glb5.O2, SOUT_PIN)

    SOUT = SOUT_PIN


Input TDISCPU, IO5

    Output _PIN_TDISCPU
        1 Fanout(s)
            glb2.I5


Clock Assignments

    Net Name		    Clock Assignment

        _PIN_SCLK               External CLK0
        _BUF_511                Internal CLK2
        _BUF_510                Internal CLK1


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb0, A1                 9,  4,  8          
            BMSK8_PIN                                    4,  2,  3,  1      
            Q0_Q                                         2,  1,  2,  1      
            Q2_Q                                         3,  1,  2,  1      
            Q7_Q                                         3,  1,  2,  1      

        glb1, A4                 5,  4,  5          
            PDQ0_PIN                                     2,  1,  1,  1      
            PDQ2_PIN                                     2,  1,  1,  1      
            PDQ3_PIN                                     2,  1,  1,  1      
            PDQ5_PIN                                     2,  1,  1,  1      

        glb10, A0                8,  4,  9          
            SQD12                                        4,  2,  2,  1      
            SQD13                                        4,  2,  2,  1      
            SQD14                                        4,  3,  2,  1      
            SQD2                                         4,  3,  2,  1      

        glb11, B2                8,  4,  9          
            SQD15                                        4,  2,  2,  1      
            SQD3                                         4,  2,  2,  1      
            SQD4                                         4,  2,  2,  1      
            SQD5                                         4,  3,  2,  1      

        glb12, A6                6,  3,  7          
            SQD6                                         4,  2,  2,  1      
            SQD7                                         4,  2,  2,  1      
            SQD8                                         4,  3,  2,  1      

        glb13, B4                5,  4,  4          
            Q11_Q                                        2,  1,  1,  1      
            Q12_Q                                        2,  1,  1,  1      
            Q13_Q                                        2,  1,  1,  1      
            Q9_Q                                         2,  1,  1,  1      

        glb14, B7                7,  4,  6          
            Q14_Q                                        2,  1,  1,  1      
            Q1_Q                                         3,  1,  2,  1      
            Q3_Q                                         3,  1,  2,  1      
            Q8_Q                                         2,  1,  2,  1      

        glb15, A7                5,  2,  4          
            Q4_Q                                         3,  1,  2,  1      
            Q6_Q                                         3,  1,  2,  1      

        glb2, A3                 9,  4,  7          
            EDISCPU_PIN                                  5,  2,  3,  1      
            PDQ1_PIN                                     2,  1,  1,  1      
            PDQ4_PIN                                     2,  1,  1,  1      
            PDQ6                                         2,  1,  1,  1      

        glb3, B0                 9,  4,  7          
            SQD0                                         4,  3,  2,  1      
            _BUF_510                                     1,  1,  1,  1      
            _BUF_511                                     1,  5,  1,  1      
            _OR_401                                      4,  1,  2,  1      

        glb4, B3                 5,  4,  5          
            PDQ10                                        2,  1,  1,  1      
            PDQ11                                        2,  1,  1,  1      
            PDQ12                                        2,  1,  1,  1      
            PDQ14_PIN                                    2,  2,  1,  1      

        glb5, B1                 8,  4,  5          
            Q10_Q                                        2,  1,  2,  1      
            Q5_Q                                         3,  1,  2,  1      
            SOUT_PIN                                     2,  1,  1,  1      
            _AND_460                                     3,  1,  1,  1      

        glb6, B5                 9,  3,  7          
            CPENAS_PIN                                   2,  1,  1,  1      
            CPENDS_PIN                                   2,  1,  1,  1      
            _OR_463                                      6,  1,  4,  1      

        glb7, B6                 5,  4,  5          
            PDQ13_PIN                                    2,  1,  1,  1      
            PDQ15                                        2,  1,  1,  1      
            PDQ8_PIN                                     2,  1,  1,  1      
            PDQ9                                         2,  1,  1,  1      

        glb8, A2                 2,  1,  2          
            PDQ7                                         2,  1,  1,  1      

        glb9, A5                 8,  4,  9          
            SQD1                                         4,  3,  2,  1      
            SQD10                                        4,  2,  2,  1      
            SQD11                                        4,  3,  2,  1      
            SQD9                                         4,  2,  2,  1      


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        SIN                     2                       Dedicated Input
        NENBERR                 3                       Output
        NLOAD                   4                       Input
        DISRST                  5                       Output
        ICEBRK                  6                       Input
        NRSTEP                  7                       Input
        NENIPL                  8                       Output
        SOUT                    9                       Output
        SCLK                    11                      Clock Input
        PSQ0                    14                      Dedicated Input
        PSQ1                    15                      Input
        PSQ2                    16                      Input
        PSQ3                    17                      Input
        PSQ4                    18                      Input
        EMON                    19                      Input
        TDISCPU                 20                      Input
        EDISCPU                 21                      Output
        PDQ0                    22                      Output
        PSQ7                    24                      Dedicated Input
        PDQ1                    25                      Output
        PDQ2                    26                      Output
        PDQ3                    27                      Output
        PDQ4                    28                      Output
        PDQ5                    29                      Output
        BUSW                    30                      Input
        BMSK8                   31                      Output
        EPAS                    32                      Input
        PSQ5                    36                      Dedicated Input
        PSQ6                    37                      Input
        CPENDS                  38                      Output
        PDQ8                    39                      Output
        CPENAS                  40                      Output
        PDQ13                   41                      Output
        PDQ14                   42                      Output
        NEPFRZ                  43                      Output
        NTFRZ                   44                      Input


Design process management completed successfully
