PALASM 4 v1.5 MACH FITR - MARKET RELEASE (7-24-92)
 (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990,91,92

 
Reading User Design (TRE File)...
 
Reading Device Database ...

***********************************************************************
     Mach PLD Fitter - v 1.67          The MACH210 on target header
***********************************************************************

PAIR Analysis...

Pre-Placement & Equation Usage Checks... 
 
|> WARNING F210 - Design contains both floating & fixed placements.  





*** Timing Analysis for Signals

 Parameter   Min   Max           Signal List (Those having Max delay.)
      Tpd     1     1             NENIPL        NENRESET         NENHALT 
                                 NENBERR         _2_PRST          NFBERR 
      Tsu     1     2           _8_SQD15        _8_SQD14        _8_SQD13 
                               _2_ENBERR        _8_SQD12       _2_ENHALT 
                              _2_ENRESET            PDQ0 
      Tco     0     1           NENRESET         NENHALT        _8_NSQD9 
                                  NENIPL         NENBERR       _8_NSQD13 
      Tcr     1     2           _2_ENINT           PDQ13 
.

 Key:
 Tpd - Combinatorial propagation delay, input to output
 Tsu - Combinatorial setup delay before clock
 Tco - clock to output (register output to combinatorial output)
 Tcr - Clock to register setup delay
.......(Register output thru combinatorial logic to reg input)
 All delay values are expressed in terms of array passes




*** Device Resource Checks

                Available        Used        Remaining
        Clocks:     2              2              0
          Pins:    38             34              4     ->    89%
     I/O Macro:    32             18             14
   Total Macro:    64             56              8
 Product Terms:   256             82             32     ->    86%
 
MACH-PLD Resource Checks OK!  



Partitioning Design into Blocks...

|> ERROR F740 - Resource violation in preplacement: (IO Pins) - Block A


*** Last Equations Placed in Blocks

Weakly -      _13_M14_QH   _15_M6_REGOUT   _15_M5_REGOUT   _15_M8_REGOUT 
Assign -   _15_M4_REGOUT   _15_M3_REGOUT   _15_M2_REGOUT       _8_NSQD13 |> INFORMATION F085 - Intermediate Error Count: 1, Warning Count: 1
|> INFORMATION F075 - Redo Partitioning with Max Packing Flag=True 

*** Last Equations Placed in Blocks

Weakly -      _13_M14_QH   _15_M6_REGOUT   _15_M5_REGOUT   _15_M8_REGOUT 
Assign -   _15_M4_REGOUT   _15_M3_REGOUT   _15_M2_REGOUT       _8_NSQD13 


|> INFORMATION F050 - Device Utilization.............. *: 80 %



*** Block Partitioning Results

               Array   Product     # I/O    Buried    Signal    Macros
              Inputs    Terms      Macro     Logic    Fanout    Remain
   Block-> A    19        56         6         8         8         2
   Block-> B    18        40         0        10        11         6
   Block-> C    11        64*        8*        8         9         0
   Block-> D    13        64*        4        12        15         0



*** Block Signal List

Blk-> A  _24_M6_REGOUT  2  _24_M5_REGOUT  2  _24_M8_REGOUT  2  _24_M4_REGOUT  2
         _24_M3_REGOUT  2  _24_M2_REGOUT  2  _24_M1_REGOUT  2  _15_M1_REGOUT  2
                  SOUT  2         NENIPL  3       NENRESET  4        NENHALT  4
               NENBERR  4         NFBERR  1

Blk-> B        _2_PRST  2       _8_NSQD9  1      _8_NSQD13  1  _15_M2_REGOUT  3
         _15_M3_REGOUT  3  _15_M4_REGOUT  3  _15_M8_REGOUT  3  _15_M5_REGOUT  3
         _15_M6_REGOUT  3     _13_M14_QH  3

Blk-> C        _2_SQD7  4        _3_SQD6  4        _3_SQD5  4        _3_SQD4  4
               _3_SQD3  4        _3_SQD2  4        _3_SQD0  4        _3_SQD1  4
                  PDQ7  2           PDQ6  2           PDQ5  2           PDQ4  2
                  PDQ3  2           PDQ2  2           PDQ1  2           PDQ0  2

Blk-> D       _2_ENINT  2      _2_ENBERR  2      _2_ENHALT  2     _2_ENRESET  2
              _8_SQD15  4       _8_SQD14  4       _8_SQD13  4       _8_SQD12  4
              _8_SQD11  4       _8_SQD10  4        _8_SQD8  4        _8_SQD9  4
                 PDQ13  2          PDQ15  2          PDQ14  2           PDQ8  2



*** Block Input List

Blk-> A         ICEBRK  4         TRESET  2           EMON  3           PSQ0  1
                NENNMI  1          NLOAD  9          PDQ14  2       _2_ENINT  1
            _2_ENRESET  1      _2_ENHALT  1      _2_ENBERR  1     _13_M14_QH  1
         _24_M1_REGOUT  1  _24_M2_REGOUT  1  _24_M3_REGOUT  1  _24_M4_REGOUT  1
         _24_M8_REGOUT  1  _24_M5_REGOUT  1  _24_M6_REGOUT  1

Singular:           PSQ0{  _15_M1_REGOUT}         NENNMI{         NENIPL}
                _2_ENINT{         NENIPL}     _2_ENRESET{       NENRESET}
               _2_ENHALT{        NENHALT}      _2_ENBERR{        NENBERR}
              _13_M14_QH{  _24_M1_REGOUT}  _24_M1_REGOUT{  _24_M2_REGOUT}
           _24_M2_REGOUT{  _24_M3_REGOUT}  _24_M3_REGOUT{  _24_M4_REGOUT}
           _24_M4_REGOUT{  _24_M8_REGOUT}  _24_M8_REGOUT{  _24_M5_REGOUT}
           _24_M5_REGOUT{  _24_M6_REGOUT}  _24_M6_REGOUT{           SOUT}
         

Blk-> B         NRSTEP  1           PSQ1  1           PSQ2  1           PSQ3  1
                  PSQ4  1           PSQ5  1           PSQ6  1         JTAGOK  2
                 NLOAD  7        _8_SQD9  1       _8_SQD13  1  _15_M1_REGOUT  1
         _15_M2_REGOUT  1  _15_M3_REGOUT  1  _15_M4_REGOUT  1  _15_M8_REGOUT  1
         _15_M5_REGOUT  1  _15_M6_REGOUT  1

Singular:         NRSTEP{        _2_PRST}           PSQ1{  _15_M2_REGOUT}
                    PSQ2{  _15_M3_REGOUT}           PSQ3{  _15_M4_REGOUT}
                    PSQ4{  _15_M8_REGOUT}           PSQ5{  _15_M5_REGOUT}
                    PSQ6{  _15_M6_REGOUT}        _8_SQD9{       _8_NSQD9}
                _8_SQD13{      _8_NSQD13}  _15_M1_REGOUT{  _15_M2_REGOUT}
           _15_M2_REGOUT{  _15_M3_REGOUT}  _15_M3_REGOUT{  _15_M4_REGOUT}
           _15_M4_REGOUT{  _15_M8_REGOUT}  _15_M8_REGOUT{  _15_M5_REGOUT}
           _15_M5_REGOUT{  _15_M6_REGOUT}  _15_M6_REGOUT{     _13_M14_QH}
         

Blk-> C            SIN  1          NLOAD  8        _3_SQD0  2        _2_PRST 16
               _3_SQD1  2        _3_SQD2  2        _3_SQD3  2        _3_SQD4  2
               _3_SQD5  2        _3_SQD6  2        _2_SQD7  1

Singular:            SIN{        _3_SQD0}        _2_SQD7{           PDQ7}
         

Blk-> D          NLOAD  8        _2_PRST 16        _2_SQD7  1        _8_SQD8  2
               _8_SQD9  1       _8_SQD10  2       _8_SQD11  2       _8_NSQD9  1
              _8_SQD12  2       _8_SQD13  1       _8_SQD14  2       _8_SQD15  1
             _8_NSQD13  1

Singular:        _2_SQD7{        _8_SQD8}        _8_SQD9{       _8_SQD10}
                _8_NSQD9{       _2_ENINT}       _8_SQD13{       _8_SQD14}
                _8_SQD15{          PDQ15}      _8_NSQD13{          PDQ13}
         

|> INFORMATION F070 - Multiple Assignment Mode - Repeat Count: 4
Assigning Resources...


Flags Used:             Unplace=False        Max Packing=True 
Flags Used:        Expand Small=False         Expand All=False



*** Macro Block D

          PDQ15 (D  0)
          PDQ14 (D  2) -> (A  1)
          PDQ13 (D  4)
           PDQ8 (D 14)

 Buried Logic>        _8_SQD10        _8_SQD11        _8_SQD12        _8_SQD13
                      _8_SQD14        _8_SQD15      _2_ENRESET       _2_ENHALT
                      _2_ENINT       _2_ENBERR         _8_SQD8         _8_SQD9
              
      Targets>   1(na)   3(na)   5(na)   6(40)   7(na)   8(39)   9(na)  10(38)
                11(na)  12(37)  13(na)  15(na)

       _8_SQD10 (D  1) -> (D  0)
       _8_SQD11 (D  3) -> (D  2)
       _8_SQD12 (D  5) -> (D  4)
       _8_SQD13 (D  6) -> (B  5) (D  5)
       _8_SQD14 (D  7) -> (D  6)
       _8_SQD15 (D  8) -> (D  9)
     _2_ENRESET (D  9) -> (A 13)
      _2_ENHALT (D 10) -> (A 10)
       _2_ENINT (D 11) -> (A  3)
      _2_ENBERR (D 12) -> (A 11)
        _8_SQD8 (D 13) -> (D 16)
        _8_SQD9 (D 15) -> (B  7) (D  7)



*** Macro Block B


 Buried Logic>         _2_PRST   _15_M2_REGOUT   _15_M3_REGOUT   _15_M4_REGOUT
                 _15_M5_REGOUT   _15_M6_REGOUT   _15_M8_REGOUT        _8_NSQD9
                    _13_M14_QH       _8_NSQD13
      Targets>   0(21)   1(na)   2(20)   3(na)   4(19)   5(na)   6(18)   7(na)
                 8(17)   9(na)  10(16)  11(na)  12(15)  13(na)  14(14)  15(na)
              

     * Retry Mapping
     * Retry Mapping
  _15_M2_REGOUT (B  0) -> (B  2)
     _13_M14_QH (B  1) -> (A 20)
  _15_M3_REGOUT (B  3) -> (B 11)
        _2_PRST (B  4) -> (C  8) (D  8)
  _15_M4_REGOUT (B  5) -> (B 16)
  _15_M5_REGOUT (B  6) -> (B 10)
  _15_M6_REGOUT (B  8) -> (B  3)
  _15_M8_REGOUT (B  9) -> (B  6)
       _8_NSQD9 (B 14) -> (D 19)
      _8_NSQD13 (B 15) -> (D  1)



*** Macro Block C

           PDQ0 (C  0)
           PDQ1 (C  2)
           PDQ2 (C  4)
           PDQ3 (C  6)
           PDQ4 (C  8)
           PDQ5 (C 10)
           PDQ6 (C 12)
           PDQ7 (C 14)

 Buried Logic>         _3_SQD0         _3_SQD1         _3_SQD2         _3_SQD3
                       _3_SQD4         _3_SQD5         _2_SQD7         _3_SQD6
              
      Targets>   1(na)   3(na)   5(na)   7(na)   9(na)  11(na)  13(na)  15(na)
              

        _3_SQD0 (C  1) -> (C 15)
        _3_SQD1 (C  3) -> (C 10)
        _3_SQD2 (C  5) -> (C  1)
        _3_SQD3 (C  7) -> (C  3)
        _3_SQD4 (C  9) -> (C  9)
        _3_SQD5 (C 11) -> (C  0)
        _2_SQD7 (C 13) -> (C  2) (D 21)
        _3_SQD6 (C 15) -> (C  4)



*** Macro Block A

         NFBERR (A  0)
        NENBERR (A  2)
        NENHALT (A  4)
       NENRESET (A  6)
         NENIPL (A 12)
           SOUT (A 14)

 Buried Logic>   _24_M1_REGOUT   _15_M1_REGOUT   _24_M2_REGOUT   _24_M3_REGOUT
                 _24_M4_REGOUT   _24_M5_REGOUT   _24_M6_REGOUT   _24_M8_REGOUT
              
      Targets>   1(na)   3(na)   5(na)   7(na)   8( 6)   9(na)  10( 7)  11(na)
                13(na)  15(na)

     * Retry Mapping
  _24_M1_REGOUT (A  1) -> (A  2)
  _15_M1_REGOUT (A  3) -> (B  4)
  _24_M2_REGOUT (A  5) -> (A  6)
  _24_M3_REGOUT (A  7) -> (A  8)
  _24_M4_REGOUT (A  8) -> (A 15)
  _24_M5_REGOUT (A 10) -> (A 14)
  _24_M6_REGOUT (A 11) -> (A  5)
  _24_M8_REGOUT (A 15) -> (A  9)



*** Macro Block Inputs

         TRESET (I  0) -> (A 12)
           EMON (I  1) -> (A  0)
         NENNMI (I  3)?
            SIN (I  4) -> (C  7)
          NLOAD (I  5)?
         NENNMI (I  3) ->   Blocked -> Reshuffling SwMtrx
       _2_ENINT -> (A 18)    Moved.
         NENNMI -> (A  3)
          NLOAD (I  5) ->   Blocked -> Reshuffling SwMtrx
  _24_M5_REGOUT -> (A 17)    Moved. -> Reshuffling SwMtrx
  _24_M1_REGOUT -> (A 14)    Moved. -> Reshuffling SwMtrx
  _24_M4_REGOUT -> (A  2)    Moved. -> Reshuffling SwMtrx
         NENNMI -> (A 15)    Moved. -> Reshuffling SwMtrx
       _2_ENINT -> (A  3)    Moved. -> Reshuffling SwMtrx
  _24_M6_REGOUT -> (A 18)    Moved.
          NLOAD -> (A  5) (B  8) (C  5) (D 13)

         JTAGOK (B  0) -> (B  1)
           PSQ6 (B  2) -> (B 18)
           PSQ5 (B  4) -> (B 14)
           PSQ4 (B  6) -> (B 20)
           PSQ3 (B  8) -> (B 21)
         ICEBRK (A  8) -> (A  4)
           PSQ2 (B 10)?
         NRSTEP (A 10)?
           PSQ1 (B 12) -> (B  9)
           PSQ0 (B 14)?
           PSQ2 (B 10) ->   Blocked -> Reshuffling SwMtrx
       _8_SQD13 -> (B 15)    Moved. -> Reshuffling SwMtrx
          NLOAD -> (B  5)    Moved.
           PSQ2 -> (B  8)
         NRSTEP (A 10) ->   Blocked -> Reshuffling SwMtrx
           PSQ5 -> (B 19)    Moved. -> Reshuffling SwMtrx
        _8_SQD9 -> (B 14)    Moved. -> Reshuffling SwMtrx
  _15_M3_REGOUT -> (B  7)    Moved. -> Reshuffling SwMtrx
           PSQ2 -> (B 11)    Moved. -> Reshuffling SwMtrx
          NLOAD -> (B  8)    Moved.
         NRSTEP -> (B  5)
           PSQ0 (B 14) ->   Blocked -> Reshuffling SwMtrx
      _2_ENHALT -> (A 19)    Moved.
           PSQ0 -> (A 10)





Wiring Completion:  100% -> (  0 nc)

|> INFORMATION F058 - Total Block Fanout (All Signals) *: 61 


*** Signals - Tabular Information

          Signal   #   P/N #   (Loc)      Type     Logic  # PT    Blocks
         NFBERR    1     2      A  0     i/o pin    comb     1    .....
        NENBERR    2     3      A  2     i/o pin    comb     1    .....
        NENHALT    3     4      A  4     i/o pin    comb     2    .....
       NENRESET    4     5      A  6     i/o pin    comb     2    .....
         ICEBRK    5     6      A  8       input       .     .    .A...
         NRSTEP    6     7      A 10       input       .     .    ..B..
         NENIPL    7     8      A 12     i/o pin    comb     2    .....
           SOUT    8     9      A 14     i/o pin    d-ff     1    .....
         TRESET    9    10      I  0       input       .     .    .A...
           EMON   10    11      I  1       input       .     .    .A...
           SCLK   11    13      I  2   clock pin       .     .    .....
           PSQ0   12    14      B 14       input       .     .    .A...
           PSQ1   13    15      B 12       input       .     .    ..B..
           PSQ2   14    16      B 10       input       .     .    ..B..
           PSQ3   15    17      B  8       input       .     .    ..B..
           PSQ4   16    18      B  6       input       .     .    ..B..
           PSQ5   17    19      B  4       input       .     .    ..B..
           PSQ6   18    20      B  2       input       .     .    ..B..
         JTAGOK   19    21      B  0       input       .     .    ..B..
           PDQ0   20    24      C  0     i/o pin    d-ff     1    .....
           PDQ1   21    25      C  2     i/o pin    d-ff     1    .....
           PDQ2   22    26      C  4     i/o pin    d-ff     1    .....
           PDQ3   23    27      C  6     i/o pin    d-ff     1    .....
           PDQ4   24    28      C  8     i/o pin    d-ff     1    .....
           PDQ5   25    29      C 10     i/o pin    d-ff     1    .....
           PDQ6   26    30      C 12     i/o pin    d-ff     1    .....
           PDQ7   27    31      C 14     i/o pin    d-ff     1    .....
         NENNMI   28    32      I  3       input       .     .    .A...
            SIN   29    33      I  4       input       .     .    ...C.
          NLOAD   30    35      I  5   clock pin       .     .    .ABCD
           PDQ8   31    36      D 14     i/o pin    d-ff     1    .....
       _8_X14_Q   32    54      D  4    out pair    d-ff     1    .....
          PDQ14   33    42      D  2     i/o pin    d-ff     1    .A...
          PDQ15   34    43      D  0     i/o pin    d-ff     1    .....
        __AB1_O   35     2      A  0    out pair    comb     1    .....
       _2_M43_O   36    14      A 12    out pair    comb     2    .....
          PDQ13   37    41      D  4     i/o pin    d-ff     1    .....
        _3_SQD0   38    35      C  1      buried    d-ff     2    ...C.
        _2_PRST   39    22      B  4      buried    comb     1    ...CD
        _3_SQD1   40    37      C  3      buried    d-ff     2    ...C.
        _3_SQD2   41    39      C  5      buried    d-ff     2    ...C.
        _3_SQD3   42    41      C  7      buried    d-ff     2    ...C.
        _3_SQD4   43    43      C  9      buried    d-ff     2    ...C.
        _3_SQD5   44    45      C 11      buried    d-ff     2    ...C.
        _3_SQD6   45    49      C 15      buried    d-ff     2    ...C.
        _2_SQD7   46    47      C 13      buried    d-ff     2    ...CD
        _8_SQD8   47    63      D 13      buried    d-ff     2    ....D
        _8_SQD9   48    65      D 15      buried    d-ff     2    ..B.D
       _8_SQD10   49    51      D  1      buried    d-ff     2    ....D
       _8_SQD11   50    53      D  3      buried    d-ff     2    ....D
       _8_NSQD9   51    32      B 14      buried    comb     1    ....D
       _2_ENINT   52    61      D 11      buried    d-ff     1    .A...
     _2_ENRESET   53    59      D  9      buried    d-ff     1    .A...
      _2_ENHALT   54    60      D 10      buried    d-ff     1    .A...
       _8_SQD12   55    55      D  5      buried    d-ff     2    ....D
      _2_ENBERR   56    62      D 12      buried    d-ff     1    .A...
       _8_SQD13   57    56      D  6      buried    d-ff     2    ..B.D
       _8_SQD14   58    57      D  7      buried    d-ff     2    ....D
       _8_SQD15   59    58      D  8      buried    d-ff     2    ....D
      _8_NSQD13   60    33      B 15      buried    comb     1    ....D
  _15_M1_REGOUT   61     5      A  3      buried    d-ff     1    ..B..
  _15_M2_REGOUT   62    18      B  0      buried    d-ff     2    ..B..
  _15_M3_REGOUT   63    21      B  3      buried    d-ff     2    ..B..
  _15_M4_REGOUT   64    23      B  5      buried    d-ff     2    ..B..
  _15_M8_REGOUT   65    27      B  9      buried    d-ff     2    ..B..
  _15_M5_REGOUT   66    24      B  6      buried    d-ff     2    ..B..
  _15_M6_REGOUT   67    26      B  8      buried    d-ff     2    ..B..
     _13_M14_QH   68    19      B  1      buried    d-ff     2    .A...
  _24_M1_REGOUT   69     3      A  1      buried    d-ff     1    .A...
  _24_M2_REGOUT   70     7      A  5      buried    d-ff     1    .A...
  _24_M3_REGOUT   71     9      A  7      buried    d-ff     1    .A...
  _24_M4_REGOUT   72    10      A  8      buried    d-ff     1    .A...
  _24_M8_REGOUT   73    17      A 15      buried    d-ff     1    .A...
  _24_M5_REGOUT   74    12      A 10      buried    d-ff     1    .A...
  _24_M6_REGOUT   75    13      A 11      buried    d-ff     1    .A...
.

 Key:
 P/N # - Pin/Node Number
 .?. - Signal Unplaced
 (Loc) - Macrocell Location (Block & Cell)
 # PT - Number of used product terms in logic
 Blocks- Device blocks driven by signal
 comb - Combinatorial logic function
 d-ff - D-Type Flip-flop
 t-ff - T-Type Flip-flop
 Note: Registered input storage equations (MACH-2xx family)
 ..... are realized with 0 array product terms.


*** Signals - Equations Where Used

   Signal Source                   Fanout List

         ICEBRK:         NENIPL          NENIPL        NENRESET         NENHALT 
               :        NENBERR 
               {AAAA A}

         NRSTEP:        _2_PRST 
               {B}
         TRESET:         NFBERR          NFBERR         NENBERR 
               {AAA}
           EMON:       NENRESET         NENHALT         NENBERR 
               {AAA}
           PSQ0:  _15_M1_REGOUT 
               {A}
           PSQ1:  _15_M2_REGOUT 
               {B}
           PSQ2:  _15_M3_REGOUT 
               {B}
           PSQ3:  _15_M4_REGOUT 
               {B}
           PSQ4:  _15_M8_REGOUT 
               {B}
           PSQ5:  _15_M5_REGOUT 
               {B}
           PSQ6:  _15_M6_REGOUT 
               {B}
         JTAGOK:     _13_M14_QH         _2_PRST 
               {BB}
         NENNMI:         NENIPL          NENIPL 
               {AA}
            SIN:        _3_SQD0 
               {C}
          NLOAD:  _24_M6_REGOUT   _24_M5_REGOUT   _24_M8_REGOUT   _24_M4_REGOUT 
               :  _24_M3_REGOUT   _24_M2_REGOUT   _24_M1_REGOUT      _13_M14_QH 
               :  _15_M6_REGOUT   _15_M5_REGOUT   _15_M8_REGOUT   _15_M4_REGOUT 
               :  _15_M3_REGOUT   _15_M2_REGOUT   _15_M1_REGOUT        _8_SQD15 
               :       _8_SQD14        _8_SQD13        _8_SQD12        _8_SQD11 
               :       _8_SQD10         _8_SQD9         _8_SQD8         _2_SQD7 
               :        _3_SQD6         _3_SQD5         _3_SQD4         _3_SQD3 
               :        _3_SQD2         _3_SQD1         _3_SQD0            SOUT 
               {AAAA AAAB BBBB BBAD DDDD DDDC CCCC CCCA}

          PDQ14:       NENRESET         NENHALT 
               {AA}
        _3_SQD0:        _3_SQD1         _3_SQD0            PDQ0 
               {CCC}
        _2_PRST:       _8_SQD15        _8_SQD14        _8_SQD13       _2_ENBERR 
               :       _8_SQD12       _2_ENHALT      _2_ENRESET        _2_ENINT 
               :       _8_SQD11        _8_SQD10         _8_SQD9         _8_SQD8 
               :        _2_SQD7         _3_SQD6         _3_SQD5         _3_SQD4 
               :        _3_SQD3         _3_SQD2         _3_SQD1         _3_SQD0 
               :          PDQ13           PDQ13           PDQ15           PDQ14 
               :           PDQ8            PDQ7            PDQ6            PDQ5 
               :           PDQ4            PDQ3            PDQ2            PDQ1 
               :           PDQ0 
               {DDDD DDDD DDDD CCCC CCCC DDDD DCCC CCCC C}

        _3_SQD1:        _3_SQD2         _3_SQD1            PDQ1 
               {CCC}
        _3_SQD2:        _3_SQD3         _3_SQD2            PDQ2 
               {CCC}
        _3_SQD3:        _3_SQD4         _3_SQD3            PDQ3 
               {CCC}
        _3_SQD4:        _3_SQD5         _3_SQD4            PDQ4 
               {CCC}
        _3_SQD5:        _3_SQD6         _3_SQD5            PDQ5 
               {CCC}
        _3_SQD6:        _2_SQD7         _3_SQD6            PDQ6 
               {CCC}
        _2_SQD7:        _8_SQD8         _2_SQD7            PDQ7 
               {DCC}
        _8_SQD8:        _8_SQD9         _8_SQD8            PDQ8 
               {DDD}
        _8_SQD9:       _8_NSQD9        _8_SQD10         _8_SQD9 
               {BDD}
       _8_SQD10:     _2_ENRESET        _8_SQD11        _8_SQD10 
               {DDD}
       _8_SQD11:       _8_SQD12       _2_ENHALT        _8_SQD11 
               {DDD}
       _8_NSQD9:       _2_ENINT 
               {D}
       _2_ENINT:         NENIPL          NENIPL 
               {AA}
     _2_ENRESET:       NENRESET 
               {A}
      _2_ENHALT:        NENHALT 
               {A}
       _8_SQD12:       _8_SQD13       _2_ENBERR        _8_SQD12 
               {DDD}
      _2_ENBERR:        NENBERR 
               {A}
       _8_SQD13:      _8_NSQD13        _8_SQD14        _8_SQD13 
               {BDD}
       _8_SQD14:       _8_SQD15        _8_SQD14           PDQ14 
               {DDD}
       _8_SQD15:       _8_SQD15           PDQ15 
               {DD}
      _8_NSQD13:          PDQ13           PDQ13 
               {DD}
  _15_M1_REGOUT:  _15_M2_REGOUT 
               {B}
  _15_M2_REGOUT:  _15_M3_REGOUT 
               {B}
  _15_M3_REGOUT:  _15_M4_REGOUT 
               {B}
  _15_M4_REGOUT:  _15_M8_REGOUT 
               {B}
  _15_M8_REGOUT:  _15_M5_REGOUT 
               {B}
  _15_M5_REGOUT:  _15_M6_REGOUT 
               {B}
  _15_M6_REGOUT:     _13_M14_QH 
               {B}
     _13_M14_QH:  _24_M1_REGOUT 
               {A}
  _24_M1_REGOUT:  _24_M2_REGOUT 
               {A}
  _24_M2_REGOUT:  _24_M3_REGOUT 
               {A}
  _24_M3_REGOUT:  _24_M4_REGOUT 
               {A}
  _24_M4_REGOUT:  _24_M8_REGOUT 
               {A}
  _24_M8_REGOUT:  _24_M5_REGOUT 
               {A}
  _24_M5_REGOUT:  _24_M6_REGOUT 
               {A}
  _24_M6_REGOUT:           SOUT 
               {A}



*** Outputs with no feedback

           NFBERR         NENBERR         NENHALT        NENRESET          NENIPL 
             SOUT            PDQ0            PDQ1            PDQ2            PDQ3 
             PDQ4            PDQ5            PDQ6            PDQ7            PDQ8 
            PDQ15           PDQ13 


*** Feedback Map - The MACH210 on target header

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
         | 0|     EMON : 0|     |21|                     | 0|     |21| PSQ3   
         | 1|    PDQ14 : 1|     |20| _13_M14      JTAGOK : 1|     |20| PSQ4   
         | 2|  _24_M4_R  2|     |19| _2_ENHA     _15_M2_R  2|     |19| PSQ5   
         | 3|  _2_ENINT  3|     |18| _24_M6_     _15_M6_R  3|     |18| PSQ6   
         | 4|   ICEBRK : 4|     |17| _24_M5_     _15_M1_R  4|     |17|        
         | 5|    NLOAD : 5|     |16|              NRSTEP : 5|     |16| _15_M4_
         '--'  _24_M2_R  6|     |15: NENNMI      _15_M8_R  6|     |15: _8_SQD1
                       | 7|     |14: _24_M1_     _15_M3_R  7|     |14: _8_SQD9
               _24_M3_R  8|     |13: _2_ENRE       NLOAD : 8|     |13|        
               _24_M8_R  9|     |12: TRESET         PSQ1 : 9|     |12|        
K:  * Used        PSQ0 :10|     |11: _2_ENBE     _15_M5_R 10|     |11: PSQ2   
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A      _3_SQD5 : 0|     |21|             _8_SQD10  0|     |21| _2_SQD7
    0 RegIn    _3_SQD2 : 1|     |20|             _8_NSQD1  1|     |20|        
               _2_SQD7 : 2|     |19|             _8_SQD11  2|     |19| _8_NSQD
               _3_SQD3 : 3|     |18|                     | 3|     |18|        
               _3_SQD6 : 4|     |17|             _8_SQD12  4|     |17|        
                 NLOAD : 5|     |16|             _8_SQD13  5|     |16| _8_SQD8
                       | 6|     |15: _3_SQD0     _8_SQD14  6|     |15|        
                   SIN : 7|     |14|             _8_SQD9 : 7|     |14|        
               _2_PRST : 8|     |13|             _2_PRST : 8|     |13: NLOAD  
               _3_SQD4 : 9|     |12|             _8_SQD15  9|     |12|        
               _3_SQD1 :10|     |11|                     |10|     |11|        
                       '--+-u--u+--'                     '--+-u--u+--'        



*** Logic Map - The MACH210 on target header

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O   
   TRESET| 0|   NFBERR | 0| 1  #|21|             _15_M2_R  0| 2  #|21|        
     EMON| 1|  _24_M1_R  1| 1  #|20|             _13_M14_  1| 2  #|20|        
     SCLK| 2|  NENBERR | 2| 1  #|19|                     | 2| .  #|19|        
   NENNMI| 3|  _15_M1_R  3| 1  #|18|             _15_M3_R  3| 2  #|18|        
      SIN| 4|  NENHALT | 4| 2  #|17|             _2_PRST | 4| 1  #|17|        
    NLOAD| 5|  _24_M2_R  5| 1  #|16|             _15_M4_R  5| 2  #|16|        
         '--'  NENRESET  6| 2  1|15| _24_M8_     _15_M5_R  6| 2  1|15| _8_NSQD
               _24_M3_R  7| 1  1|14| SOUT                | 7| .  1|14| _8_NSQD
               _24_M4_R  8| 1  .|13|             _15_M6_R  8| 2  .|13|        
                       | 9| .  2|12| NENIPL      _15_M8_R  9| 2  .|12|        
K:  * Used     _24_M5_R 10| 1  1|11| _24_M6_             |10| .  .|11|        
    . Avail            '--+--C--+--'                     '--+--D--+--'        
    # N/A         PDQ0 | 0| 1  #|21|               PDQ15 | 0| 1  #|21|        
    0 RegIn    _3_SQD0 | 1| 2  #|20|             _8_SQD10  1| 2  #|20|        
                  PDQ1 | 2| 1  #|19|               PDQ14 | 2| 1  #|19|        
               _3_SQD1 | 3| 2  #|18|             _8_SQD11  3| 2  #|18|        
                  PDQ2 | 4| 1  #|17|              /PDQ13 | 4| 1  #|17|        
               _3_SQD2 | 5| 2  #|16|             _8_SQD12  5| 2  #|16|        
                  PDQ3 | 6| 1  2|15| _3_SQD6     _8_SQD13  6| 2  2|15| _8_SQD9
               _3_SQD3 | 7| 2  1|14| PDQ7        _8_SQD14  7| 2  1|14| PDQ8   
                  PDQ4 | 8| 1  2|13| _2_SQD7     _8_SQD15  8| 2  2|13| _8_SQD8
               _3_SQD4 | 9| 2  1|12| PDQ6        _2_ENRES  9| 1  1|12| _2_ENBE
                  PDQ5 |10| 1  2|11| _3_SQD5     _2_ENHAL 10| 1  1|11| _2_ENIN
                       '--+-u--u+--'                     '--+-u--u+--'        


*** Pin Map - The MACH210 on target header
                                                                   
                                                                   
                                                                   
                                                                   
                                 NFBERR                            
                             NENBERR  |        PDQ15               
                          NENHALT  |  |        |  PDQ14            
                      NENRESET  |  |  |        |  |  /PDQ13        
                     ICEBRK  |  |  |  |        |  |  |  .          
                          |  |  |  |  |        |  |  |  |          
                    .-----'--'--'--'--'--o-----'--'--'--'---.      
                    |                       4  4  4  4  4   |      
                    |     6  5  4  3  2  1  4  3  2  1  0   |      
              NRSTEP| 7                                   39|      
              NENIPL| 8                  G  V             38|      
                SOUT| 9                  n  c             37|      
              TRESET|10                  d  c             36|PDQ8  
                EMON|11                                   35|NLOAD 
                Gnd |12            MACH-210               34| Gnd  
                SCLK|13                                   33|SIN   
                PSQ0|14             V  G                  32|NENNMI
                PSQ1|15             c  n                  31|PDQ7  
                PSQ2|16             c  d                  30|PDQ6  
                PSQ3|17                                   29|PDQ5  
                    |   1  1  2  2  2  2  2  2  2  2  2     |      
                    |   8  9  0  1  2  3  4  5  6  7  8     |      
                    '---.--.--.--.--------.--.--.--.--.-----'      
                        |  |  |  |        |  |  |  |  |            
                     PSQ4  |  |  |        |  |  |  |  PDQ4         
                        PSQ5  |  |        |  |  |  PDQ3            
                           PSQ6  |        |  |  PDQ2               
                            JTAGOK        |  PDQ1                  
                                          PDQ0                     
The Jedec Data is  stored in ===> Th210.jed
The Placements are stored in ===> Th210.plc
The Design Doc is  stored in ===> Th210.rpt
 
%% FITR %% Error Count: 0, Warning Count: 1
%% FITR %% File Processed Successfully. - File: Th210.pds
 
