(is)pLSI Development System Plus Release 2.01.21, Jul 21 1994 16:00:06


Design Parameters
-----------------

EXTENDED_ROUTE:                 ON
IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16 ((is)pLSI1000,(is)pLSI2000), 24((is)pLSI3000)
MAX_GLB_OUT:                    4
OUTPUT_FORM:                    None
PARAM_FILE:                     None
STRATEGY:                       AREA
TIMING_FILE:                    None


Design Specification
--------------------

Design:                         l1016
Part:                           pLSI1016-60LJ44


Y1_AS_RESET:                    OFF


Number of CRIT Pins:            0
Number of Free Pins:            0
Number of Locked Pins:          33


Input Pins

    Pin Name                Pin Number              Pin Attribute

        EMON                    36                      LOCK
        EPAS                    33                      LOCK
        ICEBRK                  6                       LOCK
        NENNMI                  10                      LOCK
        NLOAD                   4                       LOCK
        NRSTEP                  7                       LOCK
        PSQ0                    14                      LOCK
        PSQ1                    15                      LOCK
        PSQ2                    16                      LOCK
        PSQ3                    17                      LOCK
        PSQ4                    18                      LOCK
        PSQ5                    19                      LOCK
        PSQ6                    20                      LOCK
        PSQ7                    21                      LOCK
        SCLK                    11                      LOCK
        SIN                     24                      LOCK


Output Pins

    Pin Name                Pin Number              Pin Attribute

        CPENAS                  40                      LOCK
        CPENDS                  38                      LOCK
        DISRST                  5                       LOCK
        NENBERR                 3                       LOCK
        NENIPL                  8                       LOCK
        PDQ0                    22                      LOCK
        PDQ1                    25                      LOCK
        PDQ11                   37                      LOCK
        PDQ13                   41                      LOCK
        PDQ14                   42                      LOCK
        PDQ15                   43                      LOCK
        PDQ2                    26                      LOCK
        PDQ3                    27                      LOCK
        PDQ4                    28                      LOCK
        PDQ5                    29                      LOCK
        PDQ8                    39                      LOCK
        SOUT                    9                       LOCK


Pre-Route Design Statistics
---------------------------

Number of GLBs:                 14
Number of I/Os:                 31
Number of Nets:                 67

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    11
Number of Locked DIs:           3
Number of Locked Outputs:       17
Number of Locked Three-States:  0
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      2


GLB Utilization (Out of 16):	87%
I/O Utilization (Out of 36):	86%
Net Utilization (Out of 100):	67%


Nets with Fanout of  1:         47
Nets with Fanout of  2:         13
Nets with Fanout of  3:         5
Nets with Fanout of  9:         1
Nets with Fanout of 10:         1

Average Fanout per Net:         1.60


GLBs with  4 Input(s):          1
GLBs with  5 Input(s):          3
GLBs with  6 Input(s):          2
GLBs with  7 Input(s):          6
GLBs with  8 Input(s):          1
GLBs with  9 Input(s):          1

Average Inputs per GLB:         6.43


GLBs with  3 Output(s):         2
GLBs with  4 Output(s):         12

Average Outputs per GLB:        3.86


Post-Route Design Implementation
--------------------------------

Number of GLBs:			16
Number of IOCs:			28
Number of DIs:			3
Number of GLB Levels:		1


Clock GLB glb0

    5 Input(s)
        _PIN_NLOAD, _PIN_NRSTEP, SQD10, SQD14, SQD15

    4 Output(s)
        _BUF_639, _ABL_PIN_PDQ15, _ABL_PIN_PDQ14, PDQ10

    5 Product Term(s)

    Output _BUF_639

        1 Input(s)
            (NLOAD.O, _PIN_NLOAD)
        7 Fanout(s)
            glb7_part1.CLK1, glb6.CLK1, glb2_part1.CLK1, glb1.CLK1,
            glb2_part2.CLK1, glb7_part2.CLK1, glb0.CLK1
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_639 = (_PIN_NLOAD)

    Output _ABL_PIN_PDQ15

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb9.O0, SQD15)
        1 Fanout(s)
            PDQ15.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ15.D = (SQD15)
        _ABL_PIN_PDQ15.C = _BUF_639
        _ABL_PIN_PDQ15.R = !_PIN_NRSTEP

    Output _ABL_PIN_PDQ14

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb9.O1, SQD14)
        1 Fanout(s)
            PDQ14.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ14.D = (SQD14)
        _ABL_PIN_PDQ14.C = _BUF_639
        _ABL_PIN_PDQ14.R = !_PIN_NRSTEP

    Output PDQ10

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb5.O3, SQD10)
        1 Fanout(s)
            glb2_part1.I12
        1 Product Term(s)
        1 GLB Level(s)

        PDQ10.D = (SQD10)
        PDQ10.C = _BUF_639
        PDQ10.R = !_PIN_NRSTEP

    GLB Location B0
    Input Location(s) I6, I3, I4, I10, I11
    Output Location(s) O0, O2, O1, O3


GLB glb1

    7 Input(s)
        _PIN_ICEBRK, _PIN_NENNMI, _PIN_NRSTEP, PDQ9, SQD11, SQD12, SQD8

    4 Output(s)
        _OR_387, _ABL_PIN_PDQ8, _ABL_PIN_PDQ11, PDQ12

    6 Product Term(s)

    Output _OR_387

        3 Input(s)
            (ICEBRK.O, _PIN_ICEBRK), (NENNMI.O, _PIN_NENNMI), 
            (glb7_part2.O0, PDQ9)
        1 Fanout(s)
            NENIPL.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_387 = (_PIN_NENNMI & !_PIN_ICEBRK
            # !_PIN_ICEBRK & !PDQ9)

    Output _ABL_PIN_PDQ8

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb11.O2, SQD8)
        1 Fanout(s)
            PDQ8.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ8.D = (SQD8)
        _ABL_PIN_PDQ8.C = _BUF_639
        _ABL_PIN_PDQ8.R = !_PIN_NRSTEP

    Output _ABL_PIN_PDQ11

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb5.O2, SQD11)
        1 Fanout(s)
            PDQ11.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ11.D = (SQD11)
        _ABL_PIN_PDQ11.C = _BUF_639
        _ABL_PIN_PDQ11.R = !_PIN_NRSTEP

    Output PDQ12

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb9.O3, SQD12)
        1 Fanout(s)
            glb3.I8
        1 Product Term(s)
        1 GLB Level(s)

        PDQ12.D = (SQD12)
        PDQ12.C = _BUF_639
        PDQ12.R = !_PIN_NRSTEP

    GLB Location B5
    Input Location(s) I4, I0, I3, I15, I5, I8, I9
    Output Location(s) O1, O2, O0, O3


GLB glb10

    7 Input(s)
        _PIN_NLOAD, _PIN_NRSTEP, SQD1, SQD2, SQD3, SQD4, SQD5

    4 Output(s)
        SQD5, SQD4, SQD3, SQD2

    9 Product Term(s)

    Output SQD5

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb10.O1, 
            SQD4), (glb10.O0, SQD5)
        3 Fanout(s)
            glb11.I7, glb10.I16, glb7_part1.I8
        2 Product Term(s)
        1 GLB Level(s)

        SQD5.D = (_PIN_NLOAD & SQD4
            # SQD5 & !_PIN_NLOAD)
        SQD5.C = _PIN_SCLK
        SQD5.R = !_PIN_NRSTEP

    Output SQD4

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb10.O2, 
            SQD3), (glb10.O1, SQD4)
        2 Fanout(s)
            glb10.I17, glb7_part1.I9
        2 Product Term(s)
        1 GLB Level(s)

        SQD4.D = (_PIN_NLOAD & SQD3
            # SQD4 & !_PIN_NLOAD)
        SQD4.C = _PIN_SCLK
        SQD4.R = !_PIN_NRSTEP

    Output SQD3

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb10.O3, 
            SQD2), (glb10.O2, SQD3)
        2 Fanout(s)
            glb10.I5, glb6.I10
        2 Product Term(s)
        1 GLB Level(s)

        SQD3.D = (_PIN_NLOAD & SQD2
            # SQD3 & !_PIN_NLOAD)
        SQD3.C = _PIN_SCLK
        SQD3.R = !_PIN_NRSTEP

    Output SQD2

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb5.O0, 
            SQD1), (glb10.O3, SQD2)
        2 Fanout(s)
            glb10.I4, glb6.I11
        2 Product Term(s)
        1 GLB Level(s)

        SQD2.D = (_PIN_NLOAD & SQD1
            # SQD2 & !_PIN_NLOAD)
        SQD2.C = _PIN_SCLK
        SQD2.R = !_PIN_NRSTEP

    GLB Location B2
    Input Location(s) I6, I3, I7, I4, I5, I17, I16
    Output Location(s) O0, O1, O2, O3


GLB glb11

    7 Input(s)
        _PIN_NLOAD, _PIN_NRSTEP, SQD5, SQD6, SQD7, SQD8, SQD9

    4 Output(s)
        SQD9, SQD8, SQD7, SQD6

    9 Product Term(s)

    Output SQD9

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb11.O2, 
            SQD8), (glb11.O1, SQD9)
        3 Fanout(s)
            glb11.I10, glb5.I5, glb7_part2.I5
        2 Product Term(s)
        1 GLB Level(s)

        SQD9.D = (_PIN_NLOAD & SQD8
            # SQD9 & !_PIN_NLOAD)
        SQD9.C = _PIN_SCLK
        SQD9.R = !_PIN_NRSTEP

    Output SQD8

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb11.O3, 
            SQD7), (glb11.O2, SQD8)
        2 Fanout(s)
            glb11.I9, glb1.I9
        2 Product Term(s)
        1 GLB Level(s)

        SQD8.D = (_PIN_NLOAD & SQD7
            # SQD8 & !_PIN_NLOAD)
        SQD8.C = _PIN_SCLK
        SQD8.R = !_PIN_NRSTEP

    Output SQD7

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb11.O0, 
            SQD6), (glb11.O3, SQD7)
        2 Fanout(s)
            glb11.I8, glb2_part2.I7
        2 Product Term(s)
        1 GLB Level(s)

        SQD7.D = (_PIN_NLOAD & SQD6
            # SQD7 & !_PIN_NLOAD)
        SQD7.C = _PIN_SCLK
        SQD7.R = !_PIN_NRSTEP

    Output SQD6

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb10.O0, 
            SQD5), (glb11.O0, SQD6)
        2 Fanout(s)
            glb11.I11, glb2_part2.I4
        2 Product Term(s)
        1 GLB Level(s)

        SQD6.D = (_PIN_NLOAD & SQD5
            # SQD6 & !_PIN_NLOAD)
        SQD6.C = _PIN_SCLK
        SQD6.R = !_PIN_NRSTEP

    GLB Location B1
    Input Location(s) I6, I3, I7, I11, I8, I9, I10
    Output Location(s) O1, O2, O3, O0


GLB glb12

    9 Input(s)
        _PIN_NLOAD, _PIN_PSQ2, _PIN_PSQ3, _PIN_PSQ4, _PIN_PSQ5,
        _ABL_REG_Q1_Q, _ABL_REG_Q2_Q, _ABL_REG_Q3_Q, _ABL_REG_Q4_Q

    4 Output(s)
        _ABL_REG_Q5_Q, _ABL_REG_Q4_Q, _ABL_REG_Q3_Q, _ABL_REG_Q2_Q

    8 Product Term(s)

    Output _ABL_REG_Q5_Q

        3 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ5.O, _PIN_PSQ5), (glb12.O1, 
            _ABL_REG_Q4_Q)
        1 Fanout(s)
            glb13.I3
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q5_Q.D = (_PIN_PSQ5 & !_PIN_NLOAD
            # _PIN_NLOAD & _ABL_REG_Q4_Q)
        _ABL_REG_Q5_Q.C = _PIN_SCLK

    Output _ABL_REG_Q4_Q

        3 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ4.O, _PIN_PSQ4), (glb12.O2, 
            _ABL_REG_Q3_Q)
        1 Fanout(s)
            glb12.I13
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q4_Q.D = (_PIN_PSQ4 & !_PIN_NLOAD
            # _PIN_NLOAD & _ABL_REG_Q3_Q)
        _ABL_REG_Q4_Q.C = _PIN_SCLK

    Output _ABL_REG_Q3_Q

        3 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ3.O, _PIN_PSQ3), (glb12.O3, 
            _ABL_REG_Q2_Q)
        1 Fanout(s)
            glb12.I14
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q3_Q.D = (_PIN_PSQ3 & !_PIN_NLOAD
            # _PIN_NLOAD & _ABL_REG_Q2_Q)
        _ABL_REG_Q3_Q.C = _PIN_SCLK

    Output _ABL_REG_Q2_Q

        3 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ2.O, _PIN_PSQ2), (glb8.O3, 
            _ABL_REG_Q1_Q)
        1 Fanout(s)
            glb12.I15
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q2_Q.D = (_PIN_PSQ2 & !_PIN_NLOAD
            # _PIN_NLOAD & _ABL_REG_Q1_Q)
        _ABL_REG_Q2_Q.C = _PIN_SCLK

    GLB Location A7
    Input Location(s) I9, I1, I2, I3, I4, I11, I15, I14, I13
    Output Location(s) O0, O1, O2, O3


GLB glb13

    7 Input(s)
        _PIN_NLOAD, _PIN_PSQ6, _PIN_PSQ7, _ABL_REG_Q5_Q, _ABL_REG_Q6_Q,
        _ABL_REG_Q7_Q, _ABL_REG_Q8_Q

    4 Output(s)
        _ABL_REG_Q9_Q, _ABL_REG_Q8_Q, _ABL_REG_Q7_Q, _ABL_REG_Q6_Q

    6 Product Term(s)

    Output _ABL_REG_Q9_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb13.O1, _ABL_REG_Q8_Q)
        1 Fanout(s)
            glb4.I3
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q9_Q.D = (_PIN_NLOAD & !_ABL_REG_Q8_Q)
            $ VCC
        _ABL_REG_Q9_Q.C = _PIN_SCLK

    Output _ABL_REG_Q8_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb13.O2, _ABL_REG_Q7_Q)
        1 Fanout(s)
            glb13.I2
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q8_Q.D = (_PIN_NLOAD & _ABL_REG_Q7_Q)
        _ABL_REG_Q8_Q.C = _PIN_SCLK

    Output _ABL_REG_Q7_Q

        3 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ7.O, _PIN_PSQ7), (glb13.O3, 
            _ABL_REG_Q6_Q)
        1 Fanout(s)
            glb13.I1
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q7_Q.D = (_PIN_PSQ7 & !_PIN_NLOAD
            # _PIN_NLOAD & _ABL_REG_Q6_Q)
        _ABL_REG_Q7_Q.C = _PIN_SCLK

    Output _ABL_REG_Q6_Q

        3 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ6.O, _PIN_PSQ6), (glb12.O0, 
            _ABL_REG_Q5_Q)
        1 Fanout(s)
            glb13.I0
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q6_Q.D = (_PIN_PSQ6 & !_PIN_NLOAD
            # _PIN_NLOAD & _ABL_REG_Q5_Q)
        _ABL_REG_Q6_Q.C = _PIN_SCLK

    GLB Location B7
    Input Location(s) I6, I10, I9, I3, I0, I1, I2
    Output Location(s) O0, O1, O2, O3


GLB glb2_part1

    5 Input(s)
        _PIN_EMON, _PIN_ICEBRK, PDQ10, _PIN_NRSTEP, SQD13

    2 Output(s)
        _AND_608, _ABL_PIN_PDQ13

    3 Product Term(s)

    Output _AND_608

        3 Input(s)
            (EMON.O, _PIN_EMON), (ICEBRK.O, _PIN_ICEBRK), (glb0.O3, 
            PDQ10)
        1 Fanout(s)
            DISRST.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_608 = (_PIN_EMON & PDQ10 & !_PIN_ICEBRK)

    Output _ABL_PIN_PDQ13

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb9.O2, SQD13)
        1 Fanout(s)
            PDQ13.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ13.D = (SQD13)
        _ABL_PIN_PDQ13.C = _BUF_639
        _ABL_PIN_PDQ13.R = !_PIN_NRSTEP

    GLB Location B6
    Input Location(s) I16, I4, I12, I3, I9
    Output Location(s) O2, O0


GLB glb2_part2

    3 Input(s)
        _PIN_NRSTEP, SQD7, SQD6

    2 Output(s)
        PDQ7, PDQ6

    3 Product Term(s)

    Output PDQ7

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb11.O3, SQD7)
        1 Fanout(s)
            glb3.I13
        1 Product Term(s)
        1 GLB Level(s)

        PDQ7.D = (SQD7)
        PDQ7.C = _BUF_639
        PDQ7.R = !_PIN_NRSTEP

    Output PDQ6

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb11.O0, SQD6)
        1 Fanout(s)
            glb3.I15
        1 Product Term(s)
        1 GLB Level(s)

        PDQ6.D = (SQD6)
        PDQ6.C = _BUF_639
        PDQ6.R = !_PIN_NRSTEP

    GLB Location A0
    Input Location(s) I12, I7, I4
    Output Location(s) O2, O0


GLB glb3

    6 Input(s)
        _PIN_EMON, _PIN_ICEBRK, _PIN_NRSTEP, PDQ12, PDQ6, PDQ7

    3 Output(s)
        _AND_610, _ABL_PIN_CPENDS, _ABL_PIN_CPENAS

    4 Product Term(s)

    Output _AND_610

        3 Input(s)
            (EMON.O, _PIN_EMON), (ICEBRK.O, _PIN_ICEBRK), (glb1.O3, 
            PDQ12)
        1 Fanout(s)
            NENBERR.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_610 = (_PIN_EMON & PDQ12 & !_PIN_ICEBRK)

    Output _ABL_PIN_CPENDS

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb2_part2.O2, PDQ7)
        1 Fanout(s)
            CPENDS.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_CPENDS.D = (PDQ7)
        _ABL_PIN_CPENDS.C = _PIN_EPAS
        _ABL_PIN_CPENDS.R = !_PIN_NRSTEP

    Output _ABL_PIN_CPENAS

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb2_part2.O0, PDQ6)
        1 Fanout(s)
            CPENAS.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_CPENAS.D = (PDQ6)
        _ABL_PIN_CPENAS.C = _PIN_EPAS
        _ABL_PIN_CPENAS.R = !_PIN_NRSTEP

    GLB Location B4
    Input Location(s) I16, I4, I3, I8, I15, I13
    Output Location(s) O0, O1, O3


GLB glb4

    5 Input(s)
        _PIN_NLOAD, _ABL_REG_Q10_Q, _ABL_REG_Q11_Q, _ABL_REG_Q14_Q,
        _ABL_REG_Q9_Q
    4 Output(s)
        _ABL_REG_Q12_Q, _ABL_REG_Q11_Q, _ABL_REG_Q10_Q, _ABL_PIN_SOUT

    4 Product Term(s)

    Output _ABL_REG_Q12_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb4.O1, _ABL_REG_Q11_Q)
        1 Fanout(s)
            glb8.I12
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q12_Q.D = (_PIN_NLOAD & _ABL_REG_Q11_Q)
        _ABL_REG_Q12_Q.C = _PIN_SCLK

    Output _ABL_REG_Q11_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb4.O3, _ABL_REG_Q10_Q)
        1 Fanout(s)
            glb4.I2
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q11_Q.D = (_PIN_NLOAD & _ABL_REG_Q10_Q)
        _ABL_REG_Q11_Q.C = _PIN_SCLK

    Output _ABL_REG_Q10_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb13.O0, _ABL_REG_Q9_Q)
        1 Fanout(s)
            glb4.I0
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q10_Q.D = (_PIN_NLOAD & !_ABL_REG_Q9_Q)
            $ VCC
        _ABL_REG_Q10_Q.C = _PIN_SCLK

    Output _ABL_PIN_SOUT

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb8.O0, _ABL_REG_Q14_Q)
        1 Fanout(s)
            SOUT.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_SOUT.D = (_PIN_NLOAD & _ABL_REG_Q14_Q)
        _ABL_PIN_SOUT.C = _PIN_SCLK

    GLB Location B3
    Input Location(s) I6, I0, I2, I7, I3
    Output Location(s) O0, O1, O3, O2


GLB glb5

    8 Input(s)
        _PIN_NLOAD, _PIN_NRSTEP, _PIN_SIN, SQD0, SQD1, SQD10, SQD11,
        SQD9
    4 Output(s)
        SQD11, SQD10, SQD1, SQD0

    9 Product Term(s)

    Output SQD11

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb5.O3, 
            SQD10), (glb5.O2, SQD11)
        3 Fanout(s)
            glb9.I10, glb5.I10, glb1.I5
        2 Product Term(s)
        1 GLB Level(s)

        SQD11.D = (_PIN_NLOAD & SQD10
            # SQD11 & !_PIN_NLOAD)
        SQD11.C = _PIN_SCLK
        SQD11.R = !_PIN_NRSTEP

    Output SQD10

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb5.O3, 
            SQD10), (glb11.O1, SQD9)
        2 Fanout(s)
            glb5.I11, glb0.I4
        2 Product Term(s)
        1 GLB Level(s)

        SQD10.D = (SQD10 & !_PIN_NLOAD
            # _PIN_NLOAD & SQD9)
        SQD10.C = _PIN_SCLK
        SQD10.R = !_PIN_NRSTEP

    Output SQD1

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb5.O1, 
            SQD0), (glb5.O0, SQD1)
        3 Fanout(s)
            glb10.I7, glb6.I8, glb5.I8
        2 Product Term(s)
        1 GLB Level(s)

        SQD1.D = (_PIN_NLOAD & SQD0
            # SQD1 & !_PIN_NLOAD)
        SQD1.C = _PIN_SCLK
        SQD1.R = !_PIN_NRSTEP

    Output SQD0

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (SIN.O, 
            _PIN_SIN), (glb5.O1, SQD0)
        2 Fanout(s)
            glb6.I9, glb5.I16
        2 Product Term(s)
        1 GLB Level(s)

        SQD0.D = (_PIN_NLOAD & _PIN_SIN
            # SQD0 & !_PIN_NLOAD)
        SQD0.C = _PIN_SCLK
        SQD0.R = !_PIN_NRSTEP

    GLB Location A2
    Input Location(s) I9, I12, I17, I16, I8, I11, I10, I5
    Output Location(s) O2, O3, O0, O1


GLB glb6

    5 Input(s)
        _PIN_NRSTEP, SQD0, SQD1, SQD2, SQD3

    4 Output(s)
        _ABL_PIN_PDQ3, _ABL_PIN_PDQ2, _ABL_PIN_PDQ1, _ABL_PIN_PDQ0

    5 Product Term(s)

    Output _ABL_PIN_PDQ3

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb10.O2, SQD3)
        1 Fanout(s)
            PDQ3.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ3.D = (SQD3)
        _ABL_PIN_PDQ3.C = _BUF_639
        _ABL_PIN_PDQ3.R = !_PIN_NRSTEP

    Output _ABL_PIN_PDQ2

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb10.O3, SQD2)
        1 Fanout(s)
            PDQ2.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ2.D = (SQD2)
        _ABL_PIN_PDQ2.C = _BUF_639
        _ABL_PIN_PDQ2.R = !_PIN_NRSTEP

    Output _ABL_PIN_PDQ1

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb5.O0, SQD1)
        1 Fanout(s)
            PDQ1.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ1.D = (SQD1)
        _ABL_PIN_PDQ1.C = _BUF_639
        _ABL_PIN_PDQ1.R = !_PIN_NRSTEP

    Output _ABL_PIN_PDQ0

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb5.O1, SQD0)
        1 Fanout(s)
            PDQ0.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ0.D = (SQD0)
        _ABL_PIN_PDQ0.C = _BUF_639
        _ABL_PIN_PDQ0.R = !_PIN_NRSTEP

    GLB Location A3
    Input Location(s) I12, I9, I8, I11, I10
    Output Location(s) O2, O1, O0, O3


GLB glb7_part1

    3 Input(s)
        _PIN_NRSTEP, SQD5, SQD4

    2 Output(s)
        _ABL_PIN_PDQ5, _ABL_PIN_PDQ4

    3 Product Term(s)

    Output _ABL_PIN_PDQ5

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb10.O0, SQD5)
        1 Fanout(s)
            PDQ5.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ5.D = (SQD5)
        _ABL_PIN_PDQ5.C = _BUF_639
        _ABL_PIN_PDQ5.R = !_PIN_NRSTEP

    Output _ABL_PIN_PDQ4

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb10.O1, SQD4)
        1 Fanout(s)
            PDQ4.IR
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_PIN_PDQ4.D = (SQD4)
        _ABL_PIN_PDQ4.C = _BUF_639
        _ABL_PIN_PDQ4.R = !_PIN_NRSTEP

    GLB Location A1
    Input Location(s) I12, I8, I9
    Output Location(s) O0, O3


GLB glb7_part2

    2 Input(s)
        _PIN_NRSTEP, SQD9

    1 Output(s)
        PDQ9

    2 Product Term(s)

    Output PDQ9

        2 Input(s)
            (NRSTEP.O, _PIN_NRSTEP), (glb11.O1, SQD9)
        1 Fanout(s)
            glb1.I15
        1 Product Term(s)
        1 GLB Level(s)

        PDQ9.D = (SQD9)
        PDQ9.C = _BUF_639
        PDQ9.R = !_PIN_NRSTEP

    GLB Location A4
    Input Location(s) I12, I5
    Output Location(s) O0


GLB glb8

    6 Input(s)
        _PIN_NLOAD, _PIN_PSQ0, _PIN_PSQ1, _ABL_REG_Q0_Q, _ABL_REG_Q12_Q,
        _ABL_REG_Q13_Q

    4 Output(s)
        _ABL_REG_Q1_Q, _ABL_REG_Q14_Q, _ABL_REG_Q13_Q, _ABL_REG_Q0_Q

    5 Product Term(s)

    Output _ABL_REG_Q1_Q

        3 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ1.O, _PIN_PSQ1), (glb8.O2, 
            _ABL_REG_Q0_Q)
        1 Fanout(s)
            glb12.I11
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q1_Q.D = (_PIN_PSQ1 & !_PIN_NLOAD
            # _PIN_NLOAD & _ABL_REG_Q0_Q)
        _ABL_REG_Q1_Q.C = _PIN_SCLK

    Output _ABL_REG_Q14_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb8.O1, _ABL_REG_Q13_Q)
        1 Fanout(s)
            glb4.I7
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q14_Q.D = (_PIN_NLOAD & _ABL_REG_Q13_Q)
        _ABL_REG_Q14_Q.C = _PIN_SCLK

    Output _ABL_REG_Q13_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (glb4.O0, _ABL_REG_Q12_Q)
        1 Fanout(s)
            glb8.I17
        1 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q13_Q.D = (_PIN_NLOAD & _ABL_REG_Q12_Q)
        _ABL_REG_Q13_Q.C = _PIN_SCLK

    Output _ABL_REG_Q0_Q

        2 Input(s)
            (NLOAD.O, _PIN_NLOAD), (PSQ0.O, _PIN_PSQ0)
        1 Fanout(s)
            glb8.I10
        2 Product Term(s)
        1 GLB Level(s)

        _ABL_REG_Q0_Q.D = (!_PIN_NLOAD & !_PIN_PSQ0)
            $ VCC
        _ABL_REG_Q0_Q.C = _PIN_SCLK

    GLB Location A6
    Input Location(s) I9, I16, I0, I10, I12, I17
    Output Location(s) O3, O0, O1, O2


GLB glb9

    7 Input(s)
        _PIN_NLOAD, _PIN_NRSTEP, SQD11, SQD12, SQD13, SQD14, SQD15

    4 Output(s)
        SQD15, SQD14, SQD13, SQD12

    9 Product Term(s)

    Output SQD15

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb9.O1, 
            SQD14), (glb9.O0, SQD15)
        2 Fanout(s)
            glb9.I4, glb0.I11
        2 Product Term(s)
        1 GLB Level(s)

        SQD15.D = (_PIN_NLOAD & SQD14
            # SQD15 & !_PIN_NLOAD)
        SQD15.C = _PIN_SCLK
        SQD15.R = !_PIN_NRSTEP

    Output SQD14

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb9.O2, 
            SQD13), (glb9.O1, SQD14)
        2 Fanout(s)
            glb9.I5, glb0.I10
        2 Product Term(s)
        1 GLB Level(s)

        SQD14.D = (_PIN_NLOAD & SQD13
            # SQD14 & !_PIN_NLOAD)
        SQD14.C = _PIN_SCLK
        SQD14.R = !_PIN_NRSTEP

    Output SQD13

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb9.O3, 
            SQD12), (glb9.O2, SQD13)
        2 Fanout(s)
            glb9.I6, glb2_part1.I9
        2 Product Term(s)
        1 GLB Level(s)

        SQD13.D = (_PIN_NLOAD & SQD12
            # SQD13 & !_PIN_NLOAD)
        SQD13.C = _PIN_SCLK
        SQD13.R = !_PIN_NRSTEP

    Output SQD12

        4 Input(s)
            (NLOAD.O, _PIN_NLOAD), (NRSTEP.O, _PIN_NRSTEP), (glb5.O2, 
            SQD11), (glb9.O3, SQD12)
        2 Fanout(s)
            glb9.I7, glb1.I8
        2 Product Term(s)
        1 GLB Level(s)

        SQD12.D = (_PIN_NLOAD & SQD11
            # SQD12 & !_PIN_NLOAD)
        SQD12.C = _PIN_SCLK
        SQD12.R = !_PIN_NRSTEP

    GLB Location A5
    Input Location(s) I9, I12, I10, I7, I6, I5, I4
    Output Location(s) O0, O1, O2, O3


Output CPENAS

    Input (glb3.O3, _ABL_PIN_CPENAS)

    CPENAS = _ABL_PIN_CPENAS

    IOC Location IO19


Output CPENDS

    Input (glb3.O1, _ABL_PIN_CPENDS)

    CPENDS = _ABL_PIN_CPENDS

    IOC Location IO17


Output DISRST

    Input (glb2_part1.O2, _AND_608)

    DISRST = !_AND_608

    IOC Location IO26


Dedicated Input EMON

    Output _PIN_EMON
        2 Fanout(s)
            glb3.I16, glb2_part1.I16

    DI Location I7


Input EPAS

    Output _PIN_EPAS
        1 Fanout(s)
            glb3.CLK2

    CLK_IOC Location IO2


Input ICEBRK

    Output _PIN_ICEBRK
        3 Fanout(s)
            glb3.I4, glb2_part1.I4, glb1.I4

    IOC Location IO27


Output NENBERR

    Input (glb3.O0, _AND_610)

    NENBERR = !_AND_610

    IOC Location IO24


Output NENIPL

    Input (glb1.O1, _OR_387)

    NENIPL = _OR_387

    IOC Location IO29


Input NENNMI

    Output _PIN_NENNMI
        1 Fanout(s)
            glb1.I0

    IOC Location IO31


Input NLOAD

    Output _PIN_NLOAD
        9 Fanout(s)
            glb13.I6, glb12.I9, glb11.I6, glb10.I6, glb9.I9, glb8.I9,
            glb5.I9, glb4.I6, glb0.I6

    IOC Location IO25


Input NRSTEP

    Output _PIN_NRSTEP
        12 Fanout(s)
            glb11.I3, glb10.I3, glb9.I12, glb7_part1.I12, glb6.I12,
            glb5.I12, glb3.I3, glb2_part1.I3, glb1.I3, glb2_part2.I12,
            glb7_part2.I12, glb0.I3

    IOC Location IO28


Output PDQ0

    Input (glb6.O3, _ABL_PIN_PDQ0)

    PDQ0 = _ABL_PIN_PDQ0

    IOC Location IO7


Output PDQ1

    Input (glb6.O0, _ABL_PIN_PDQ1)

    PDQ1 = _ABL_PIN_PDQ1

    IOC Location IO8


Output PDQ11

    Input (glb1.O0, _ABL_PIN_PDQ11)

    PDQ11 = _ABL_PIN_PDQ11

    IOC Location IO16


Output PDQ13

    Input (glb2_part1.O0, _ABL_PIN_PDQ13)

    PDQ13 = _ABL_PIN_PDQ13

    IOC Location IO20


Output PDQ14

    Input (glb0.O1, _ABL_PIN_PDQ14)

    PDQ14 = _ABL_PIN_PDQ14

    IOC Location IO21


Output PDQ15

    Input (glb0.O2, _ABL_PIN_PDQ15)

    PDQ15 = _ABL_PIN_PDQ15

    IOC Location IO22


Output PDQ2

    Input (glb6.O1, _ABL_PIN_PDQ2)

    PDQ2 = _ABL_PIN_PDQ2

    IOC Location IO9


Output PDQ3

    Input (glb6.O2, _ABL_PIN_PDQ3)

    PDQ3 = _ABL_PIN_PDQ3

    IOC Location IO10


Output PDQ4

    Input (glb7_part1.O3, _ABL_PIN_PDQ4)

    PDQ4 = _ABL_PIN_PDQ4

    IOC Location IO11


Output PDQ5

    Input (glb7_part1.O0, _ABL_PIN_PDQ5)

    PDQ5 = _ABL_PIN_PDQ5

    IOC Location IO12


Output PDQ8

    Input (glb1.O2, _ABL_PIN_PDQ8)

    PDQ8 = _ABL_PIN_PDQ8

    IOC Location IO18


Dedicated Input PSQ0

    Output _PIN_PSQ0
        1 Fanout(s)
            glb8.I16

    DI Location I5


Input PSQ1

    Output _PIN_PSQ1
        1 Fanout(s)
            glb8.I0

    IOC Location IO0


Input PSQ2

    Output _PIN_PSQ2
        1 Fanout(s)
            glb12.I1

    IOC Location IO1


Input PSQ3

    Output _PIN_PSQ3
        1 Fanout(s)
            glb12.I2

    IOC Location IO2


Input PSQ4

    Output _PIN_PSQ4
        1 Fanout(s)
            glb12.I3

    IOC Location IO3


Input PSQ5

    Output _PIN_PSQ5
        1 Fanout(s)
            glb12.I4

    IOC Location IO4


Input PSQ6

    Output _PIN_PSQ6
        1 Fanout(s)
            glb13.I10

    IOC Location IO5


Input PSQ7

    Output _PIN_PSQ7
        1 Fanout(s)
            glb13.I9

    IOC Location IO6


Input SCLK

    Output _PIN_SCLK
        8 Fanout(s)
            glb13.CLK0, glb12.CLK0, glb11.CLK0, glb10.CLK0, glb9.CLK0,
            glb8.CLK0, glb5.CLK0, glb4.CLK0

    CLK_IOC Location IO0


Dedicated Input SIN

    Output _PIN_SIN
        1 Fanout(s)
            glb5.I17

    DI Location I6


Output SOUT

    Input (glb4.O2, _ABL_PIN_SOUT)

    SOUT = _ABL_PIN_SOUT

    IOC Location IO30


Clock Assignments

    Net Name		    Clock Assignment

        _PIN_SCLK               External CLK0
        _BUF_639                Internal CLK1
        _PIN_EPAS               External CLK2


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        NENBERR                 3                       Output
        NLOAD                   4                       Input
        DISRST                  5                       Output
        ICEBRK                  6                       Input
        NRSTEP                  7                       Input
        NENIPL                  8                       Output
        SOUT                    9                       Output
        NENNMI                  10                      Input
        SCLK                    11                      Input
        PSQ0                    14                      Dedicated Input
        PSQ1                    15                      Input
        PSQ2                    16                      Input
        PSQ3                    17                      Input
        PSQ4                    18                      Input
        PSQ5                    19                      Input
        PSQ6                    20                      Input
        PSQ7                    21                      Input
        PDQ0                    22                      Output
        SIN                     24                      Dedicated Input
        PDQ1                    25                      Output
        PDQ2                    26                      Output
        PDQ3                    27                      Output
        PDQ4                    28                      Output
        PDQ5                    29                      Output
        EPAS                    33                      Input
        EMON                    36                      Dedicated Input
        PDQ11                   37                      Output
        CPENDS                  38                      Output
        PDQ8                    39                      Output
        CPENAS                  40                      Output
        PDQ13                   41                      Output
        PDQ14                   42                      Output
        PDQ15                   43                      Output


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb0, B0                 5,  4,  5          
        PDQ10                                            2,  1,  1,  1      
        _ABL_PIN_PDQ14                                   2,  1,  1,  1      
        _ABL_PIN_PDQ15                                   2,  1,  1,  1      
        _BUF_639                                         1,  7,  1,  1      

        glb1, B5                 7,  4,  6          
        PDQ12                                            2,  1,  1,  1      
        _ABL_PIN_PDQ11                                   2,  1,  1,  1      
        _ABL_PIN_PDQ8                                    2,  1,  1,  1      
        _OR_387                                          3,  1,  2,  1      

        glb10, B2                7,  4,  9          
        SQD2                                             4,  2,  2,  1      
        SQD3                                             4,  2,  2,  1      
        SQD4                                             4,  2,  2,  1      
        SQD5                                             4,  3,  2,  1      

        glb11, B1                7,  4,  9          
        SQD6                                             4,  2,  2,  1      
        SQD7                                             4,  2,  2,  1      
        SQD8                                             4,  2,  2,  1      
        SQD9                                             4,  3,  2,  1      

        glb12, A7                9,  4,  8          
        _ABL_REG_Q2_Q                                    3,  1,  2,  1      
        _ABL_REG_Q3_Q                                    3,  1,  2,  1      
        _ABL_REG_Q4_Q                                    3,  1,  2,  1      
        _ABL_REG_Q5_Q                                    3,  1,  2,  1      

        glb13, B7                7,  4,  6          
        _ABL_REG_Q6_Q                                    3,  1,  2,  1      
        _ABL_REG_Q7_Q                                    3,  1,  2,  1      
        _ABL_REG_Q8_Q                                    2,  1,  1,  1      
        _ABL_REG_Q9_Q                                    2,  1,  2,  1      

        glb2_part1, B6           5,  2,  3          
        _ABL_PIN_PDQ13                                   2,  1,  1,  1      
        _AND_608                                         3,  1,  1,  1      

        glb2_part2, A0           3,  2,  3          
        PDQ6                                             2,  1,  1,  1      
        PDQ7                                             2,  1,  1,  1      

        glb3, B4                 6,  3,  4          
        _ABL_PIN_CPENAS                                  2,  1,  1,  1      
        _ABL_PIN_CPENDS                                  2,  1,  1,  1      
        _AND_610                                         3,  1,  1,  1      

        glb4, B3                 5,  4,  4          
        _ABL_PIN_SOUT                                    2,  1,  1,  1      
        _ABL_REG_Q10_Q                                   2,  1,  2,  1      
        _ABL_REG_Q11_Q                                   2,  1,  1,  1      
        _ABL_REG_Q12_Q                                   2,  1,  1,  1      

        glb5, A2                 8,  4,  9          
        SQD0                                             4,  2,  2,  1      
        SQD1                                             4,  3,  2,  1      
        SQD10                                            4,  2,  2,  1      
        SQD11                                            4,  3,  2,  1      

        glb6, A3                 5,  4,  5          
        _ABL_PIN_PDQ0                                    2,  1,  1,  1      
        _ABL_PIN_PDQ1                                    2,  1,  1,  1      
        _ABL_PIN_PDQ2                                    2,  1,  1,  1      
        _ABL_PIN_PDQ3                                    2,  1,  1,  1      

        glb7_part1, A1           3,  2,  3          
        _ABL_PIN_PDQ4                                    2,  1,  1,  1      
        _ABL_PIN_PDQ5                                    2,  1,  1,  1      

        glb7_part2, A4           2,  1,  2          
        PDQ9                                             2,  1,  1,  1      

        glb8, A6                 6,  4,  5          
        _ABL_REG_Q0_Q                                    2,  1,  2,  1      
        _ABL_REG_Q13_Q                                   2,  1,  1,  1      
        _ABL_REG_Q14_Q                                   2,  1,  1,  1      
        _ABL_REG_Q1_Q                                    3,  1,  2,  1      

        glb9, A5                 7,  4,  9          
        SQD12                                            4,  2,  2,  1      
        SQD13                                            4,  2,  2,  1      
        SQD14                                            4,  2,  2,  1      
        SQD15                                            4,  2,  2,  1      


Design process management completed successfully
