(is)pLSI Development System Plus Release 2.1.13, Jun  5 1995 10:02:40


Design Parameters
-----------------

IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16 ((is)pLSI1000,(is)pLSI2000), 24((is)pLSI3000)
MAX_GLB_OUT:                    4
STRATEGY:                       AREA


Design Specification
--------------------

Design:                         sio328
Part:                           pLSI1016-60LJ44


Y1_AS_RESET:                    OFF


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          37


Input Pins

    Pin Name                Pin Attribute

        EMON                    LOCK 36
        EPAS                    LOCK 33
        ICEBERR                 LOCK 2
        ICEBR                   LOCK 3
        ICEBRK                  LOCK 6
        ICERESET                LOCK 31
        NENNMI                  LOCK 10
        NLOAD                   LOCK 4
        NRSTEP                  LOCK 7
        NTRESET                 LOCK 30
        PSQ0                    LOCK 14
        PSQ1                    LOCK 15
        PSQ2                    LOCK 16
        PSQ3                    LOCK 17
        PSQ4                    LOCK 18
        PSQ5                    LOCK 19
        PSQ7                    LOCK 21
        SCLK                    LOCK 11
        SIN                     LOCK 24
        TGHOLD                  LOCK 20


Output Pins

    Pin Name                Pin Attribute

        CPENAS                  LOCK 40
        CPENDS                  LOCK 38
        DLYSTB                  LOCK 43
        EPBERR                  LOCK 44
        EPBR                    LOCK 41
        EPHLTOE                 LOCK 37
        NBRESET                 LOCK 42
        NENIPL                  LOCK 8
        NEPRSTOE                LOCK 5
        PDQ0                    LOCK 22
        PDQ1                    LOCK 25
        PDQ2                    LOCK 26
        PDQ3                    LOCK 27
        PDQ4                    LOCK 28
        PDQ5                    LOCK 29
        PDQ8                    LOCK 39
        SOUT                    LOCK 9


Pre-Route Design Statistics
---------------------------

Number of GLBs:                 15
Number of I/Os:                 35
Number of Nets:                 75

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    14
Number of Locked DIs:           4
Number of Locked Outputs:       17
Number of Locked Three-States:  0
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      2


GLB Utilization (Out of 16):	93%
I/O Utilization (Out of 36):	97%
Net Utilization (Out of 100):	75%


Nets with Fanout of  1:         52
Nets with Fanout of  2:         15
Nets with Fanout of  3:         6
Nets with Fanout of  9:         1
Nets with Fanout of 10:         1

Average Fanout per Net:         1.59


GLBs with  4 Input(s):          1
GLBs with  5 Input(s):          4
GLBs with  6 Input(s):          1
GLBs with  7 Input(s):          4
GLBs with  8 Input(s):          2
GLBs with  9 Input(s):          2
GLBs with 10 Input(s):          1

Average Inputs per GLB:         6.80


GLBs with  3 Output(s):         2
GLBs with  4 Output(s):         13

Average Outputs per GLB:        3.87


Post-Route Design Implementation
--------------------------------

Number of GLBs:			16
Number of IOCs:			31
Number of DIs:			4
Number of GLB Levels:		1


Clock GLB glb0, B0

    8 Input(s)
        (EMON.O, _PIN_EMON, I16), (ICEBERR.O, _PIN_ICEBERR, I17), 
        (ICEBRK.O, _PIN_ICEBRK, I4), (NENNMI.O, _PIN_NENNMI, I0), 
        (NLOAD.O, _PIN_NLOAD, I6), (glb2.O3, PDQ12, I12), (glb8.O0, 
        PDQ9, I3), (glb12.O2, Q14_Q, I1)
    4 Output(s)
        (_OR_404, O1), (_BUF_561, O0), (_AND_467, O3), (SOUT_PIN, O2)
    5 Product Term(s)

    Output _OR_404

        3 Input(s)
            _PIN_ICEBRK, _PIN_NENNMI, PDQ9
        1 Fanout(s)
            NENIPL.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_404 = (_PIN_NENNMI & !_PIN_ICEBRK
            # !_PIN_ICEBRK & !PDQ9)

    Output _BUF_561

        1 Input(s)
            _PIN_NLOAD
        5 Fanout(s)
            glb1_part2.CLK1, glb6.CLK1, glb8.CLK1, glb7.CLK1, glb2.CLK1
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_561 = _PIN_NLOAD

    Output _AND_467

        4 Input(s)
            _PIN_EMON, _PIN_ICEBERR, _PIN_ICEBRK, PDQ12
        1 Fanout(s)
            EPBERR.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_467 = _PIN_EMON & PDQ12 & !_PIN_ICEBERR & !_PIN_ICEBRK

    Output SOUT_PIN

        2 Input(s)
            _PIN_NLOAD, Q14_Q
        1 Fanout(s)
            SOUT.IR
        1 Product Term(s)
        1 GLB Level(s)

        SOUT_PIN.D = _PIN_NLOAD & Q14_Q
        SOUT_PIN.C = _PIN_SCLK


GLB glb10, B2

    8 Input(s)
        (NLOAD.O, _PIN_NLOAD, I6), (NRSTEP.O, _PIN_NRSTEP, I3), 
        (glb9.O1, SQD12, I10), (glb10.O3, SQD13, I4), (glb10.O2, 
        SQD14, I5), (glb10.O1, SQD15, I16), (glb11.O3, SQD7, I8), 
        (glb10.O0, SQD8, I7)
    4 Output(s)
        (SQD8, O0), (SQD15, O1), (SQD14, O2), (SQD13, O3)
    9 Product Term(s)

    Output SQD8

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD7, SQD8
        3 Fanout(s)
            glb9.I8, glb10.I7, glb2.I7
        2 Product Term(s)
        1 GLB Level(s)

        SQD8.D = (_PIN_NLOAD & SQD7
            # SQD8 & !_PIN_NLOAD)
        SQD8.C = _PIN_SCLK
        SQD8.R = !_PIN_NRSTEP

    Output SQD15

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD14, SQD15
        2 Fanout(s)
            glb1_part2.I9, glb10.I16
        2 Product Term(s)
        1 GLB Level(s)

        SQD15.D = (_PIN_NLOAD & SQD14
            # SQD15 & !_PIN_NLOAD)
        SQD15.C = _PIN_SCLK
        SQD15.R = !_PIN_NRSTEP

    Output SQD14

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD13, SQD14
        2 Fanout(s)
            glb1_part2.I10, glb10.I5
        2 Product Term(s)
        1 GLB Level(s)

        SQD14.D = (_PIN_NLOAD & SQD13
            # SQD14 & !_PIN_NLOAD)
        SQD14.C = _PIN_SCLK
        SQD14.R = !_PIN_NRSTEP

    Output SQD13

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD12, SQD13
        2 Fanout(s)
            glb1_part2.I11, glb10.I4
        2 Product Term(s)
        1 GLB Level(s)

        SQD13.D = (_PIN_NLOAD & SQD12
            # SQD13 & !_PIN_NLOAD)
        SQD13.C = _PIN_SCLK
        SQD13.R = !_PIN_NRSTEP


GLB glb11, B1

    7 Input(s)
        (NLOAD.O, _PIN_NLOAD, I6), (NRSTEP.O, _PIN_NRSTEP, I3), 
        (glb4.O0, SQD3, I7), (glb11.O1, SQD4, I10), (glb11.O0, 
        SQD5, I11), (glb11.O2, SQD6, I9), (glb11.O3, SQD7, I8)
    4 Output(s)
        (SQD7, O3), (SQD6, O2), (SQD5, O0), (SQD4, O1)
    9 Product Term(s)

    Output SQD7

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD6, SQD7
        3 Fanout(s)
            glb8.I7, glb11.I8, glb10.I8
        2 Product Term(s)
        1 GLB Level(s)

        SQD7.D = (_PIN_NLOAD & SQD6
            # SQD7 & !_PIN_NLOAD)
        SQD7.C = _PIN_SCLK
        SQD7.R = !_PIN_NRSTEP

    Output SQD6

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD5, SQD6
        2 Fanout(s)
            glb8.I6, glb11.I9
        2 Product Term(s)
        1 GLB Level(s)

        SQD6.D = (_PIN_NLOAD & SQD5
            # SQD6 & !_PIN_NLOAD)
        SQD6.C = _PIN_SCLK
        SQD6.R = !_PIN_NRSTEP

    Output SQD5

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD4, SQD5
        2 Fanout(s)
            glb6.I4, glb11.I11
        2 Product Term(s)
        1 GLB Level(s)

        SQD5.D = (_PIN_NLOAD & SQD4
            # SQD5 & !_PIN_NLOAD)
        SQD5.C = _PIN_SCLK
        SQD5.R = !_PIN_NRSTEP

    Output SQD4

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD3, SQD4
        2 Fanout(s)
            glb7.I5, glb11.I10
        2 Product Term(s)
        1 GLB Level(s)

        SQD4.D = (_PIN_NLOAD & SQD3
            # SQD4 & !_PIN_NLOAD)
        SQD4.C = _PIN_SCLK
        SQD4.R = !_PIN_NRSTEP


GLB glb12, A7

    5 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (glb5.O0, Q12_Q, I0), (glb12.O3, 
        Q13_Q, I15), (glb13.O0, Q7_Q, I12), (glb12.O1, Q8_Q, I13)
    4 Output(s)
        (Q9_Q, O0), (Q8_Q, O1), (Q14_Q, O2), (Q13_Q, O3)
    4 Product Term(s)

    Output Q9_Q

        2 Input(s)
            _PIN_NLOAD, Q8_Q
        1 Fanout(s)
            glb5.I12
        2 Product Term(s)
        1 GLB Level(s)

        Q9_Q.D = (_PIN_NLOAD & !Q8_Q)
            $ VCC
        Q9_Q.C = _PIN_SCLK

    Output Q8_Q

        2 Input(s)
            _PIN_NLOAD, Q7_Q
        1 Fanout(s)
            glb12.I13
        2 Product Term(s)
        1 GLB Level(s)

        Q8_Q.D = (_PIN_NLOAD & !Q7_Q)
            $ VCC
        Q8_Q.C = _PIN_SCLK

    Output Q14_Q

        2 Input(s)
            _PIN_NLOAD, Q13_Q
        1 Fanout(s)
            glb0.I1
        1 Product Term(s)
        1 GLB Level(s)

        Q14_Q.D = _PIN_NLOAD & Q13_Q
        Q14_Q.C = _PIN_SCLK

    Output Q13_Q

        2 Input(s)
            _PIN_NLOAD, Q12_Q
        1 Fanout(s)
            glb12.I15
        1 Product Term(s)
        1 GLB Level(s)

        Q13_Q.D = _PIN_NLOAD & Q12_Q
        Q13_Q.C = _PIN_SCLK


GLB glb13, B7

    9 Input(s)
        (NLOAD.O, _PIN_NLOAD, I6), (PSQ1.O, _PIN_PSQ1, I15), (PSQ2.O, 
        _PIN_PSQ2, I14), (PSQ3.O, _PIN_PSQ3, I13), (PSQ7.O, 
        _PIN_PSQ7, I9), (glb5.O3, Q0_Q, I12), (glb13.O3, Q1_Q, I0), 
        (glb13.O2, Q2_Q, I1), (glb14.O0, Q6_Q, I11)
    4 Output(s)
        (Q7_Q, O0), (Q3_Q, O1), (Q2_Q, O2), (Q1_Q, O3)
    8 Product Term(s)

    Output Q7_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ7, Q6_Q
        1 Fanout(s)
            glb12.I12
        2 Product Term(s)
        1 GLB Level(s)

        Q7_Q.D = (_PIN_PSQ7 & !_PIN_NLOAD
            # _PIN_NLOAD & Q6_Q)
        Q7_Q.C = _PIN_SCLK

    Output Q3_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ3, Q2_Q
        1 Fanout(s)
            glb14.I2
        2 Product Term(s)
        1 GLB Level(s)

        Q3_Q.D = (_PIN_PSQ3 & !_PIN_NLOAD
            # _PIN_NLOAD & Q2_Q)
        Q3_Q.C = _PIN_SCLK

    Output Q2_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ2, Q1_Q
        1 Fanout(s)
            glb13.I1
        2 Product Term(s)
        1 GLB Level(s)

        Q2_Q.D = (_PIN_PSQ2 & !_PIN_NLOAD
            # _PIN_NLOAD & Q1_Q)
        Q2_Q.C = _PIN_SCLK

    Output Q1_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ1, Q0_Q
        1 Fanout(s)
            glb13.I0
        2 Product Term(s)
        1 GLB Level(s)

        Q1_Q.D = (_PIN_PSQ1 & !_PIN_NLOAD
            # _PIN_NLOAD & Q0_Q)
        Q1_Q.C = _PIN_SCLK


GLB glb14, B5

    7 Input(s)
        (NLOAD.O, _PIN_NLOAD, I6), (PSQ4.O, _PIN_PSQ4, I12), (PSQ5.O, 
        _PIN_PSQ5, I11), (glb13.O1, Q3_Q, I2), (glb14.O2, Q4_Q, I9), 
        (glb14.O1, Q5_Q, I16), (TGHOLD.O, _PIN_TGHOLD, I10)
    3 Output(s)
        (Q6_Q, O0), (Q5_Q, O1), (Q4_Q, O2)
    6 Product Term(s)

    Output Q6_Q

        3 Input(s)
            _PIN_NLOAD, Q5_Q, _PIN_TGHOLD
        1 Fanout(s)
            glb13.I11
        2 Product Term(s)
        1 GLB Level(s)

        Q6_Q.D = (_PIN_NLOAD & Q5_Q
            # !_PIN_TGHOLD & !_PIN_NLOAD)
        Q6_Q.C = _PIN_SCLK

    Output Q5_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ5, Q4_Q
        1 Fanout(s)
            glb14.I16
        2 Product Term(s)
        1 GLB Level(s)

        Q5_Q.D = (_PIN_PSQ5 & !_PIN_NLOAD
            # _PIN_NLOAD & Q4_Q)
        Q5_Q.C = _PIN_SCLK

    Output Q4_Q

        3 Input(s)
            _PIN_NLOAD, _PIN_PSQ4, Q3_Q
        1 Fanout(s)
            glb14.I9
        2 Product Term(s)
        1 GLB Level(s)

        Q4_Q.D = (_PIN_PSQ4 & !_PIN_NLOAD
            # _PIN_NLOAD & Q3_Q)
        Q4_Q.C = _PIN_SCLK


GLB glb1_part1, B6

    5 Input(s)
        (EMON.O, _PIN_EMON, I16), (ICEBRK.O, _PIN_ICEBRK, I4), 
        (ICERESET.O, _PIN_ICERESET, I1), (glb7.O2, PDQ10, I5), 
        (glb1_part2.O1, PDQ14, I14)
    1 Output(s)
        (_OR_400, O2)
    2 Product Term(s)

    Output _OR_400

        5 Input(s)
            _PIN_EMON, _PIN_ICEBRK, _PIN_ICERESET, PDQ10, PDQ14
        1 Fanout(s)
            NEPRSTOE.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_400 = (!PDQ14
            # _PIN_EMON & PDQ10 & !_PIN_ICEBRK & !_PIN_ICERESET)


GLB glb1_part2, A0

    4 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I12), (glb10.O1, SQD15, I9), (glb10.O2, 
        SQD14, I10), (glb10.O3, SQD13, I11)
    3 Output(s)
        (PDQ15, O0), (PDQ14, O1), (PDQ13, O3)
    4 Product Term(s)

    Output PDQ15

        2 Input(s)
            _PIN_NRSTEP, SQD15
        1 Fanout(s)
            glb3.I15
        1 Product Term(s)
        1 GLB Level(s)

        PDQ15.D = SQD15
        PDQ15.C = _BUF_561
        PDQ15.R = !_PIN_NRSTEP

    Output PDQ14

        2 Input(s)
            _PIN_NRSTEP, SQD14
        2 Fanout(s)
            glb2.I14, glb1_part1.I14
        1 Product Term(s)
        1 GLB Level(s)

        PDQ14.D = SQD14
        PDQ14.C = _BUF_561
        PDQ14.R = !_PIN_NRSTEP

    Output PDQ13

        2 Input(s)
            _PIN_NRSTEP, SQD13
        1 Fanout(s)
            glb3.I12
        1 Product Term(s)
        1 GLB Level(s)

        PDQ13.D = SQD13
        PDQ13.C = _BUF_561
        PDQ13.R = !_PIN_NRSTEP


GLB glb2, B4

    10 Input(s)
        (EMON.O, _PIN_EMON, I16), (ICEBRK.O, _PIN_ICEBRK, I4), 
        (ICERESET.O, _PIN_ICERESET, I1), (NRSTEP.O, _PIN_NRSTEP, I3), 
        (NTRESET.O, _PIN_NTRESET, I2), (glb7.O2, PDQ10, I5), (glb7.O1, 
        PDQ11, I6), (glb1_part2.O1, PDQ14, I14), (glb9.O1, SQD12, I10), 
        (glb10.O0, SQD8, I7)
    4 Output(s)
        (_OR_474, O1), (_OR_412, O0), (PDQ8_PIN, O2), (PDQ12, O3)
    7 Product Term(s)

    Output _OR_474

        6 Input(s)
            _PIN_EMON, _PIN_ICEBRK, _PIN_NRSTEP, _PIN_NTRESET, PDQ10,
            PDQ14
        1 Fanout(s)
            NBRESET.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_474 = (!_PIN_NRSTEP & !PDQ14
            # _PIN_EMON & PDQ10 & !_PIN_ICEBRK & !_PIN_NTRESET)

    Output _OR_412

        5 Input(s)
            _PIN_EMON, _PIN_ICEBRK, _PIN_ICERESET, PDQ11, PDQ14
        1 Fanout(s)
            EPHLTOE.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_412 = (!PDQ14
            # _PIN_EMON & PDQ11 & !_PIN_ICEBRK & !_PIN_ICERESET)

    Output PDQ8_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD8
        1 Fanout(s)
            PDQ8.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ8_PIN.D = SQD8
        PDQ8_PIN.C = _BUF_561
        PDQ8_PIN.R = !_PIN_NRSTEP

    Output PDQ12

        2 Input(s)
            _PIN_NRSTEP, SQD12
        1 Fanout(s)
            glb0.I12
        1 Product Term(s)
        1 GLB Level(s)

        PDQ12.D = SQD12
        PDQ12.C = _BUF_561
        PDQ12.R = !_PIN_NRSTEP


GLB glb3, B3

    6 Input(s)
        (ICEBR.O, _PIN_ICEBR, I7), (NRSTEP.O, _PIN_NRSTEP, I3), 
        (glb1_part2.O3, PDQ13, I12), (glb1_part2.O0, PDQ15, I15), 
        (glb8.O2, PDQ6, I1), (glb8.O1, PDQ7, I2)
    4 Output(s)
        (_AND_468, O0), (DLYSTB_PIN, O2), (CPENDS_PIN, O1), 
        (CPENAS_PIN, O3)
    5 Product Term(s)

    Output _AND_468

        2 Input(s)
            _PIN_ICEBR, PDQ13
        1 Fanout(s)
            EPBR.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_468 = !_PIN_ICEBR & !PDQ13

    Output DLYSTB_PIN

        2 Input(s)
            _PIN_NRSTEP, PDQ15
        1 Fanout(s)
            DLYSTB.IR
        1 Product Term(s)
        1 GLB Level(s)

        DLYSTB_PIN.D = PDQ15
        DLYSTB_PIN.C = _PIN_EPAS
        DLYSTB_PIN.R = !_PIN_NRSTEP

    Output CPENDS_PIN

        2 Input(s)
            _PIN_NRSTEP, PDQ7
        1 Fanout(s)
            CPENDS.IR
        1 Product Term(s)
        1 GLB Level(s)

        CPENDS_PIN.D = PDQ7
        CPENDS_PIN.C = _PIN_EPAS
        CPENDS_PIN.R = !_PIN_NRSTEP

    Output CPENAS_PIN

        2 Input(s)
            _PIN_NRSTEP, PDQ6
        1 Fanout(s)
            CPENAS.IR
        1 Product Term(s)
        1 GLB Level(s)

        CPENAS_PIN.D = PDQ6
        CPENAS_PIN.C = _PIN_EPAS
        CPENAS_PIN.R = !_PIN_NRSTEP


GLB glb4, A2

    7 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (NRSTEP.O, _PIN_NRSTEP, I12), 
        (SIN.O, _PIN_SIN, I17), (glb4.O3, SQD0, I11), (glb4.O2, 
        SQD1, I10), (glb4.O1, SQD2, I16), (glb4.O0, SQD3, I8)
    4 Output(s)
        (SQD3, O0), (SQD2, O1), (SQD1, O2), (SQD0, O3)
    9 Product Term(s)

    Output SQD3

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD2, SQD3
        3 Fanout(s)
            glb6.I8, glb4.I8, glb11.I7
        2 Product Term(s)
        1 GLB Level(s)

        SQD3.D = (_PIN_NLOAD & SQD2
            # SQD3 & !_PIN_NLOAD)
        SQD3.C = _PIN_SCLK
        SQD3.R = !_PIN_NRSTEP

    Output SQD2

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD1, SQD2
        2 Fanout(s)
            glb6.I9, glb4.I16
        2 Product Term(s)
        1 GLB Level(s)

        SQD2.D = (_PIN_NLOAD & SQD1
            # SQD2 & !_PIN_NLOAD)
        SQD2.C = _PIN_SCLK
        SQD2.R = !_PIN_NRSTEP

    Output SQD1

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD0, SQD1
        2 Fanout(s)
            glb4.I10, glb7.I10
        2 Product Term(s)
        1 GLB Level(s)

        SQD1.D = (_PIN_NLOAD & SQD0
            # SQD1 & !_PIN_NLOAD)
        SQD1.C = _PIN_SCLK
        SQD1.R = !_PIN_NRSTEP

    Output SQD0

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, _PIN_SIN, SQD0
        2 Fanout(s)
            glb6.I11, glb4.I11
        2 Product Term(s)
        1 GLB Level(s)

        SQD0.D = (_PIN_NLOAD & _PIN_SIN
            # SQD0 & !_PIN_NLOAD)
        SQD0.C = _PIN_SCLK
        SQD0.R = !_PIN_NRSTEP


GLB glb5, A4

    5 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (PSQ0.O, _PIN_PSQ0, I16), (glb5.O2, 
        Q10_Q, I2), (glb5.O1, Q11_Q, I1), (glb12.O0, Q9_Q, I12)
    4 Output(s)
        (Q12_Q, O0), (Q11_Q, O1), (Q10_Q, O2), (Q0_Q, O3)
    4 Product Term(s)

    Output Q12_Q

        2 Input(s)
            _PIN_NLOAD, Q11_Q
        1 Fanout(s)
            glb12.I0
        1 Product Term(s)
        1 GLB Level(s)

        Q12_Q.D = _PIN_NLOAD & Q11_Q
        Q12_Q.C = _PIN_SCLK

    Output Q11_Q

        2 Input(s)
            _PIN_NLOAD, Q10_Q
        1 Fanout(s)
            glb5.I1
        1 Product Term(s)
        1 GLB Level(s)

        Q11_Q.D = _PIN_NLOAD & Q10_Q
        Q11_Q.C = _PIN_SCLK

    Output Q10_Q

        2 Input(s)
            _PIN_NLOAD, Q9_Q
        1 Fanout(s)
            glb5.I2
        2 Product Term(s)
        1 GLB Level(s)

        Q10_Q.D = (_PIN_NLOAD & !Q9_Q)
            $ VCC
        Q10_Q.C = _PIN_SCLK

    Output Q0_Q

        2 Input(s)
            _PIN_NLOAD, _PIN_PSQ0
        1 Fanout(s)
            glb13.I12
        2 Product Term(s)
        1 GLB Level(s)

        Q0_Q.D = (!_PIN_NLOAD & !_PIN_PSQ0)
            $ VCC
        Q0_Q.C = _PIN_SCLK


GLB glb6, A1

    5 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I12), (glb4.O3, SQD0, I11), (glb4.O1, 
        SQD2, I9), (glb4.O0, SQD3, I8), (glb11.O0, SQD5, I4)
    4 Output(s)
        (PDQ5_PIN, O0), (PDQ3_PIN, O2), (PDQ2_PIN, O1), (PDQ0_PIN, O3)
    5 Product Term(s)

    Output PDQ5_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD5
        1 Fanout(s)
            PDQ5.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ5_PIN.D = SQD5
        PDQ5_PIN.C = _BUF_561
        PDQ5_PIN.R = !_PIN_NRSTEP

    Output PDQ3_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD3
        1 Fanout(s)
            PDQ3.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ3_PIN.D = SQD3
        PDQ3_PIN.C = _BUF_561
        PDQ3_PIN.R = !_PIN_NRSTEP

    Output PDQ2_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD2
        1 Fanout(s)
            PDQ2.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ2_PIN.D = SQD2
        PDQ2_PIN.C = _BUF_561
        PDQ2_PIN.R = !_PIN_NRSTEP

    Output PDQ0_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD0
        1 Fanout(s)
            PDQ0.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ0_PIN.D = SQD0
        PDQ0_PIN.C = _BUF_561
        PDQ0_PIN.R = !_PIN_NRSTEP


GLB glb7, A6

    5 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I12), (glb4.O2, SQD1, I10), (glb9.O3, 
        SQD10, I7), (glb9.O2, SQD11, I6), (glb11.O1, SQD4, I5)
    4 Output(s)
        (PDQ4_PIN, O3), (PDQ1_PIN, O0), (PDQ11, O1), (PDQ10, O2)
    5 Product Term(s)

    Output PDQ4_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD4
        1 Fanout(s)
            PDQ4.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ4_PIN.D = SQD4
        PDQ4_PIN.C = _BUF_561
        PDQ4_PIN.R = !_PIN_NRSTEP

    Output PDQ1_PIN

        2 Input(s)
            _PIN_NRSTEP, SQD1
        1 Fanout(s)
            PDQ1.IR
        1 Product Term(s)
        1 GLB Level(s)

        PDQ1_PIN.D = SQD1
        PDQ1_PIN.C = _BUF_561
        PDQ1_PIN.R = !_PIN_NRSTEP

    Output PDQ11

        2 Input(s)
            _PIN_NRSTEP, SQD11
        1 Fanout(s)
            glb2.I6
        1 Product Term(s)
        1 GLB Level(s)

        PDQ11.D = SQD11
        PDQ11.C = _BUF_561
        PDQ11.R = !_PIN_NRSTEP

    Output PDQ10

        2 Input(s)
            _PIN_NRSTEP, SQD10
        2 Fanout(s)
            glb2.I5, glb1_part1.I5
        1 Product Term(s)
        1 GLB Level(s)

        PDQ10.D = SQD10
        PDQ10.C = _BUF_561
        PDQ10.R = !_PIN_NRSTEP


GLB glb8, A3

    4 Input(s)
        (NRSTEP.O, _PIN_NRSTEP, I12), (glb11.O2, SQD6, I6), (glb11.O3, 
        SQD7, I7), (glb9.O0, SQD9, I4)
    3 Output(s)
        (PDQ9, O0), (PDQ7, O1), (PDQ6, O2)
    4 Product Term(s)

    Output PDQ9

        2 Input(s)
            _PIN_NRSTEP, SQD9
        1 Fanout(s)
            glb0.I3
        1 Product Term(s)
        1 GLB Level(s)

        PDQ9.D = SQD9
        PDQ9.C = _BUF_561
        PDQ9.R = !_PIN_NRSTEP

    Output PDQ7

        2 Input(s)
            _PIN_NRSTEP, SQD7
        1 Fanout(s)
            glb3.I2
        1 Product Term(s)
        1 GLB Level(s)

        PDQ7.D = SQD7
        PDQ7.C = _BUF_561
        PDQ7.R = !_PIN_NRSTEP

    Output PDQ6

        2 Input(s)
            _PIN_NRSTEP, SQD6
        1 Fanout(s)
            glb3.I1
        1 Product Term(s)
        1 GLB Level(s)

        PDQ6.D = SQD6
        PDQ6.C = _BUF_561
        PDQ6.R = !_PIN_NRSTEP


GLB glb9, A5

    7 Input(s)
        (NLOAD.O, _PIN_NLOAD, I9), (NRSTEP.O, _PIN_NRSTEP, I12), 
        (glb9.O3, SQD10, I7), (glb9.O2, SQD11, I6), (glb9.O1, 
        SQD12, I5), (glb10.O0, SQD8, I8), (glb9.O0, SQD9, I4)
    4 Output(s)
        (SQD9, O0), (SQD12, O1), (SQD11, O2), (SQD10, O3)
    9 Product Term(s)

    Output SQD9

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD8, SQD9
        2 Fanout(s)
            glb8.I4, glb9.I4
        2 Product Term(s)
        1 GLB Level(s)

        SQD9.D = (_PIN_NLOAD & SQD8
            # SQD9 & !_PIN_NLOAD)
        SQD9.C = _PIN_SCLK
        SQD9.R = !_PIN_NRSTEP

    Output SQD12

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD11, SQD12
        3 Fanout(s)
            glb9.I5, glb10.I10, glb2.I10
        2 Product Term(s)
        1 GLB Level(s)

        SQD12.D = (_PIN_NLOAD & SQD11
            # SQD12 & !_PIN_NLOAD)
        SQD12.C = _PIN_SCLK
        SQD12.R = !_PIN_NRSTEP

    Output SQD11

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD10, SQD11
        2 Fanout(s)
            glb9.I6, glb7.I6
        2 Product Term(s)
        1 GLB Level(s)

        SQD11.D = (_PIN_NLOAD & SQD10
            # SQD11 & !_PIN_NLOAD)
        SQD11.C = _PIN_SCLK
        SQD11.R = !_PIN_NRSTEP

    Output SQD10

        4 Input(s)
            _PIN_NLOAD, _PIN_NRSTEP, SQD10, SQD9
        2 Fanout(s)
            glb9.I7, glb7.I7
        2 Product Term(s)
        1 GLB Level(s)

        SQD10.D = (SQD10 & !_PIN_NLOAD
            # _PIN_NLOAD & SQD9)
        SQD10.C = _PIN_SCLK
        SQD10.R = !_PIN_NRSTEP


Output CPENAS, IO19

    Input (glb3.O3, CPENAS_PIN)

    CPENAS = CPENAS_PIN


Output CPENDS, IO17

    Input (glb3.O1, CPENDS_PIN)

    CPENDS = CPENDS_PIN


Output DLYSTB, IO22

    Input (glb3.O2, DLYSTB_PIN)

    DLYSTB = DLYSTB_PIN


Dedicated Input EMON, I2

    Output _PIN_EMON
        3 Fanout(s)
            glb0.I16, glb2.I16, glb1_part1.I16


Clock Input EPAS, Y2

    Output _PIN_EPAS
        1 Fanout(s)
            glb3.CLK2


Output EPBERR, IO23

    Input (glb0.O3, _AND_467)

    EPBERR = !_AND_467


Output EPBR, IO20

    Input (glb3.O0, _AND_468)

    EPBR = !_AND_468


Output EPHLTOE, IO16

    Input (glb2.O0, _OR_412)

    EPHLTOE = !_OR_412


Dedicated Input ICEBERR, I3

    Output _PIN_ICEBERR
        1 Fanout(s)
            glb0.I17


Input ICEBR, IO24

    Output _PIN_ICEBR
        1 Fanout(s)
            glb3.I7


Input ICEBRK, IO27

    Output _PIN_ICEBRK
        3 Fanout(s)
            glb0.I4, glb2.I4, glb1_part1.I4


Input ICERESET, IO14

    Output _PIN_ICERESET
        2 Fanout(s)
            glb2.I1, glb1_part1.I1


Output NBRESET, IO21

    Input (glb2.O1, _OR_474)

    NBRESET = !_OR_474


Output NENIPL, IO29

    Input (glb0.O1, _OR_404)

    NENIPL = _OR_404


Input NENNMI, IO31

    Output _PIN_NENNMI
        1 Fanout(s)
            glb0.I0


Output NEPRSTOE, IO26

    Input (glb1_part1.O2, _OR_400)

    NEPRSTOE = !_OR_400


Input NLOAD, IO25

    Output _PIN_NLOAD
        9 Fanout(s)
            glb4.I9, glb5.I9, glb9.I9, glb12.I9, glb0.I6, glb11.I6,
            glb10.I6, glb14.I6, glb13.I6


Input NRSTEP, IO28

    Output _PIN_NRSTEP
        10 Fanout(s)
            glb1_part2.I12, glb6.I12, glb4.I12, glb8.I12, glb9.I12,
            glb7.I12, glb11.I3, glb10.I3, glb3.I3, glb2.I3


Input NTRESET, IO13

    Output _PIN_NTRESET
        1 Fanout(s)
            glb2.I2


Output PDQ0, IO7

    Input (glb6.O3, PDQ0_PIN)

    PDQ0 = PDQ0_PIN


Output PDQ1, IO8

    Input (glb7.O0, PDQ1_PIN)

    PDQ1 = PDQ1_PIN


Output PDQ2, IO9

    Input (glb6.O1, PDQ2_PIN)

    PDQ2 = PDQ2_PIN


Output PDQ3, IO10

    Input (glb6.O2, PDQ3_PIN)

    PDQ3 = PDQ3_PIN


Output PDQ4, IO11

    Input (glb7.O3, PDQ4_PIN)

    PDQ4 = PDQ4_PIN


Output PDQ5, IO12

    Input (glb6.O0, PDQ5_PIN)

    PDQ5 = PDQ5_PIN


Output PDQ8, IO18

    Input (glb2.O2, PDQ8_PIN)

    PDQ8 = PDQ8_PIN


Dedicated Input PSQ0, I0

    Output _PIN_PSQ0
        1 Fanout(s)
            glb5.I16


Input PSQ1, IO0

    Output _PIN_PSQ1
        1 Fanout(s)
            glb13.I15


Input PSQ2, IO1

    Output _PIN_PSQ2
        1 Fanout(s)
            glb13.I14


Input PSQ3, IO2

    Output _PIN_PSQ3
        1 Fanout(s)
            glb13.I13


Input PSQ4, IO3

    Output _PIN_PSQ4
        1 Fanout(s)
            glb14.I12


Input PSQ5, IO4

    Output _PIN_PSQ5
        1 Fanout(s)
            glb14.I11


Input PSQ7, IO6

    Output _PIN_PSQ7
        1 Fanout(s)
            glb13.I9


Clock Input SCLK, Y0

    Output _PIN_SCLK
        9 Fanout(s)
            glb4.CLK0, glb5.CLK0, glb9.CLK0, glb12.CLK0, glb0.CLK0,
            glb11.CLK0, glb10.CLK0, glb14.CLK0, glb13.CLK0


Dedicated Input SIN, I1

    Output _PIN_SIN
        1 Fanout(s)
            glb4.I17


Output SOUT, IO30

    Input (glb0.O2, SOUT_PIN)

    SOUT = SOUT_PIN


Input TGHOLD, IO5

    Output _PIN_TGHOLD
        1 Fanout(s)
            glb14.I10


Clock Assignments

    Net Name		    Clock Assignment

        _BUF_561                Internal CLK1
        _PIN_SCLK               External CLK0
        _PIN_EPAS               External CLK2


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb0, B0                 8,  4,  5          
            SOUT_PIN                                     2,  1,  1,  1      
            _AND_467                                     4,  1,  1,  1      
            _BUF_561                                     1,  5,  1,  1      
            _OR_404                                      3,  1,  2,  1      

        glb10, B2                8,  4,  9          
            SQD13                                        4,  2,  2,  1      
            SQD14                                        4,  2,  2,  1      
            SQD15                                        4,  2,  2,  1      
            SQD8                                         4,  3,  2,  1      

        glb11, B1                7,  4,  9          
            SQD4                                         4,  2,  2,  1      
            SQD5                                         4,  2,  2,  1      
            SQD6                                         4,  2,  2,  1      
            SQD7                                         4,  3,  2,  1      

        glb12, A7                5,  4,  4          
            Q13_Q                                        2,  1,  1,  1      
            Q14_Q                                        2,  1,  1,  1      
            Q8_Q                                         2,  1,  2,  1      
            Q9_Q                                         2,  1,  2,  1      

        glb13, B7                9,  4,  8          
            Q1_Q                                         3,  1,  2,  1      
            Q2_Q                                         3,  1,  2,  1      
            Q3_Q                                         3,  1,  2,  1      
            Q7_Q                                         3,  1,  2,  1      

        glb14, B5                7,  3,  6          
            Q4_Q                                         3,  1,  2,  1      
            Q5_Q                                         3,  1,  2,  1      
            Q6_Q                                         3,  1,  2,  1      

        glb1_part1, B6           5,  1,  2          
            _OR_400                                      5,  1,  2,  1      

        glb1_part2, A0           4,  3,  4          
            PDQ13                                        2,  1,  1,  1      
            PDQ14                                        2,  2,  1,  1      
            PDQ15                                        2,  1,  1,  1      

        glb2, B4                10,  4,  7          
            PDQ12                                        2,  1,  1,  1      
            PDQ8_PIN                                     2,  1,  1,  1      
            _OR_412                                      5,  1,  2,  1      
            _OR_474                                      6,  1,  2,  1      

        glb3, B3                 6,  4,  5          
            CPENAS_PIN                                   2,  1,  1,  1      
            CPENDS_PIN                                   2,  1,  1,  1      
            DLYSTB_PIN                                   2,  1,  1,  1      
            _AND_468                                     2,  1,  1,  1      

        glb4, A2                 7,  4,  9          
            SQD0                                         4,  2,  2,  1      
            SQD1                                         4,  2,  2,  1      
            SQD2                                         4,  2,  2,  1      
            SQD3                                         4,  3,  2,  1      

        glb5, A4                 5,  4,  4          
            Q0_Q                                         2,  1,  2,  1      
            Q10_Q                                        2,  1,  2,  1      
            Q11_Q                                        2,  1,  1,  1      
            Q12_Q                                        2,  1,  1,  1      

        glb6, A1                 5,  4,  5          
            PDQ0_PIN                                     2,  1,  1,  1      
            PDQ2_PIN                                     2,  1,  1,  1      
            PDQ3_PIN                                     2,  1,  1,  1      
            PDQ5_PIN                                     2,  1,  1,  1      

        glb7, A6                 5,  4,  5          
            PDQ10                                        2,  2,  1,  1      
            PDQ11                                        2,  1,  1,  1      
            PDQ1_PIN                                     2,  1,  1,  1      
            PDQ4_PIN                                     2,  1,  1,  1      

        glb8, A3                 4,  3,  4          
            PDQ6                                         2,  1,  1,  1      
            PDQ7                                         2,  1,  1,  1      
            PDQ9                                         2,  1,  1,  1      

        glb9, A5                 7,  4,  9          
            SQD10                                        4,  2,  2,  1      
            SQD11                                        4,  2,  2,  1      
            SQD12                                        4,  3,  2,  1      
            SQD9                                         4,  2,  2,  1      


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        ICEBERR                 2                       Dedicated Input
        ICEBR                   3                       Input
        NLOAD                   4                       Input
        NEPRSTOE                5                       Output
        ICEBRK                  6                       Input
        NRSTEP                  7                       Input
        NENIPL                  8                       Output
        SOUT                    9                       Output
        NENNMI                  10                      Input
        SCLK                    11                      Clock Input
        PSQ0                    14                      Dedicated Input
        PSQ1                    15                      Input
        PSQ2                    16                      Input
        PSQ3                    17                      Input
        PSQ4                    18                      Input
        PSQ5                    19                      Input
        TGHOLD                  20                      Input
        PSQ7                    21                      Input
        PDQ0                    22                      Output
        SIN                     24                      Dedicated Input
        PDQ1                    25                      Output
        PDQ2                    26                      Output
        PDQ3                    27                      Output
        PDQ4                    28                      Output
        PDQ5                    29                      Output
        NTRESET                 30                      Input
        ICERESET                31                      Input
        EPAS                    33                      Clock Input
        EMON                    36                      Dedicated Input
        EPHLTOE                 37                      Output
        CPENDS                  38                      Output
        PDQ8                    39                      Output
        CPENAS                  40                      Output
        EPBR                    41                      Output
        NBRESET                 42                      Output
        DLYSTB                  43                      Output
        EPBERR                  44                      Output


Design process management completed successfully
