(is)pLSI Development System Plus Release 2.1.13, Jun  5 1995 10:02:40


Design Parameters
-----------------

IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16 ((is)pLSI1000,(is)pLSI2000), 24((is)pLSI3000)
MAX_GLB_OUT:                    4
PARAM_FILE:                     mcftrace
STRATEGY:                       DELAY


Design Specification
--------------------

Design:                         mcftrace
Part:                           pLSI1016-60LJ44


Y1_AS_RESET:                    OFF


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          39


Input Pins

    Pin Name                Pin Attribute

        ALE                     LOCK 33
        CEN                     LOCK 14
        CLK                     LOCK 11
        CSN                     LOCK 36
        DEN                     LOCK 2
        RDN                     LOCK 5
        TB0                     LOCK 7
        TB1                     LOCK 8
        TB2                     LOCK 9
        TB3                     LOCK 10
        WRN                     LOCK 35
        _KWD_RST                LOCK 24


Output Pins

    Pin Name                Pin Attribute

        ACTN                    LOCK 6
        TA0                     LOCK 15
        TA1                     LOCK 16
        TA10                    LOCK 27
        TA11                    LOCK 28
        TA12                    LOCK 29
        TA13                    LOCK 30
        TA14                    LOCK 31
        TA2                     LOCK 17
        TA3                     LOCK 18
        TA4                     LOCK 19
        TA5                     LOCK 20
        TA6                     LOCK 21
        TA7                     LOCK 22
        TA8                     LOCK 25
        TA9                     LOCK 26
        TB_INT                  LOCK 32
        TDEN                    LOCK 4
        TEN                     LOCK 3


Bidirectional Pins

    Pin Name                Pin Attribute

        AD0                     LOCK 37
        AD1                     LOCK 38
        AD2                     LOCK 39
        AD3                     LOCK 40
        AD4                     LOCK 41
        AD5                     LOCK 42
        AD6                     LOCK 43
        AD7                     LOCK 44


Pre-Route Design Statistics
---------------------------

Number of GLBs:                 14
Number of I/Os:                 36
Number of Nets:                 61

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    5
Number of Locked DIs:           4
Number of Locked Outputs:       4
Number of Locked Three-States:  17
Number of Locked Bidi's:        6

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      3


GLB Utilization (Out of 16):	87%
I/O Utilization (Out of 36):	100%
Net Utilization (Out of 100):	61%


Nets with Fanout of  1:         21
Nets with Fanout of  2:         11
Nets with Fanout of  3:         10
Nets with Fanout of  4:         5
Nets with Fanout of  5:         3
Nets with Fanout of  6:         4
Nets with Fanout of  7:         4
Nets with Fanout of  8:         3

Average Fanout per Net:         3.02


GLBs with  3 Input(s):          2
GLBs with  8 Input(s):          1
GLBs with 10 Input(s):          1
GLBs with 11 Input(s):          2
GLBs with 12 Input(s):          3
GLBs with 13 Input(s):          2
GLBs with 15 Input(s):          1
GLBs with 17 Input(s):          2

Average Inputs per GLB:         11.21


GLBs with  1 Output(s):         2
GLBs with  2 Output(s):         1
GLBs with  3 Output(s):         2
GLBs with  4 Output(s):         9

Average Outputs per GLB:        3.29


Output Enable Nets

    Net Name                Net Fanout

        _BUF_873                15
        AD7_OE                  8


Post-Route Design Implementation
--------------------------------

Number of GLBs:			16
Number of IOCs:			32
Number of DIs:			4
Number of GLB Levels:		2


GLB glb0, A4

    3 Input(s)
        (CEN.O, _PIN_CEN, I16), (glb6.O0, EE3, I8), (_KWD_RST.O, 
        _PIN__KWD_RST, I17)
    4 Output(s)
        (_BUF_871, O2), (_BUF_870, O1), (_BUF_869, O0), (TBBSYNC, O3)
    1 Enable Output
        _BUF_873
    6 Product Term(s)

    Output _BUF_871

        1 Input(s)
            _PIN_CEN
        1 Fanout(s)
            glb7.I13
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_871 = _PIN_CEN

    Output _BUF_870

        1 Input(s)
            _PIN__KWD_RST
        2 Fanout(s)
            glb4_part2.I1, glb3.I1
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_870 = _PIN__KWD_RST

    Output _BUF_869

        1 Input(s)
            _PIN__KWD_RST
        5 Fanout(s)
            glb1.I0, glb5.I0, glb2.I0, glb6.I0, glb12.I15
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_869 = _PIN__KWD_RST

    Output TBBSYNC

        1 Input(s)
            _PIN_CEN
        2 Fanout(s)
            glb13.I12, glb11.I12
        1 Product Term(s)
        1 GLB Level(s)

        TBBSYNC.D = _PIN_CEN
        TBBSYNC.C = _PIN_CLK
        TBBSYNC.R = !_PIN_CEN

    Enable Output _BUF_873

        1 Input(s)
            EE3
        15 Fanout(s)
            TA9.OE1, TA8.OE1, TA7.OE1, TA6.OE1, TA5.OE1, TA4.OE1,
            TA3.OE1, TA2.OE1, TA1.OE1, TA14.OE1, TA13.OE1, TA12.OE1,
            TA11.OE1, TA10.OE1, TA0.OE1
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_873 = EE3


GLB glb1, A1

    11 Input(s)
        (glb13.O1, CNTE, I5), (TB2.O, _PIN_TB2, I14), (TB3.O, 
        _PIN_TB3, I15), (glb1.O1, TD0, I16), (glb1.O0, TD1, I4), 
        (glb12.O2, TD2, I2), (glb12.O1, TD3, I1), (glb5.O0, TQ0, I12), 
        (glb5.O1, TQ1, I13), (glb1.O2, TQ2, I6), (glb0.O0, 
        _BUF_869, I0)
    3 Output(s)
        (TQ2, O2), (TD1, O0), (TD0, O1)
    12 Product Term(s)

    Output TQ2

        5 Input(s)
            CNTE, TQ0, TQ1, TQ2, _BUF_869
        8 Fanout(s)
            glb4_part2.I6, glb1.I6, glb3.I6, glb5.I6, glb2.I6, glb7.I9,
            glb10.I9, TA2.IR
        4 Product Term(s)
        2 GLB Level(s)

        TQ2.D = (TQ2 & !TQ0
            # TQ2 & !TQ1
            # TQ2 & !CNTE
            # CNTE & TQ0 & TQ1 & !TQ2)
        TQ2.C = _PIN_CLK
        TQ2.R = _BUF_869

    Output TD1

        7 Input(s)
            _PIN_TB2, _PIN_TB3, TD0, TD1, TD2, TD3, _BUF_869
        3 Fanout(s)
            glb1.I4, glb12.I11, glb13.I11
        5 Product Term(s)
        2 GLB Level(s)

        TD1.D = (TD1 & !TD0
            # TD0 & !TD1
            # _PIN_TB3 & !_PIN_TB2
            # !TD0 & !TD2 & !TD3)
            $ VCC
        TD1.C = _PIN_CLK
        TD1.R = _BUF_869

    Output TD0

        7 Input(s)
            _PIN_TB2, _PIN_TB3, TD0, TD1, TD2, TD3, _BUF_869
        3 Fanout(s)
            glb1.I16, glb12.I10, glb13.I10
        4 Product Term(s)
        2 GLB Level(s)

        TD0.D = (TD0
            # _PIN_TB3 & !_PIN_TB2
            # !TD1 & !TD2 & !TD3)
            $ VCC
        TD0.C = _PIN_CLK
        TD0.R = _BUF_869


GLB glb10, B7

    17 Input(s)
        (glb13.O1, CNTE, I10), (glb6.O2, EE2, I5), (glb10.O0, 
        TOV, I16), (glb5.O0, TQ0, I3), (glb5.O1, TQ1, I2), (glb5.O2, 
        TQ10, I1), (glb2.O3, TQ11, I8), (glb2.O0, TQ12, I11), 
        (glb15.O2, TQ13_buff1, I13), (glb1.O2, TQ2, I9), (glb5.O3, 
        TQ3, I0), (glb4_part2.O0, TQ4_part2, I15), (glb4_part2.O1, 
        TQ5_part2, I14), (glb15.O3, TQ6_buff1, I12), (glb3.O3, 
        TQ7, I4), (glb3.O0, TQ8, I7), (glb3.O1, TQ9, I6)
    1 Output(s)
        (TOV, O0)
    3 Product Term(s)

    Output TOV

        17 Input(s)
            CNTE, EE2, TOV, TQ0, TQ1, TQ10, TQ11, TQ12, TQ13_buff1, TQ2,
            TQ3, TQ4_part2, TQ5_part2, TQ6_buff1, TQ7, TQ8, TQ9
        3 Fanout(s)
            glb4_part1.I12, glb7.I3, glb10.I16
        2 Product Term(s)
        2 GLB Level(s)

        TOV.D = (TOV
            # CNTE & TQ0 & TQ1 & TQ10 & TQ11 & TQ12 & TQ13_buff1 & TQ2
            & TQ3 & TQ4_part2 & TQ5_part2 & TQ6_buff1 & TQ7 & TQ8 & TQ9
            )
        TOV.C = _PIN_CLK
        TOV.R = EE2


GLB glb11, B3

    3 Input(s)
        (TB1.O, _PIN_TB1, I2), (glb11.O0, TBB1_part2, I16), (glb0.O3, 
        TBBSYNC, I12)
    2 Output(s)
        (TBB1_part2, O0), (TBB1_part1, O2)
    2 Product Term(s)

    Output TBB1_part2

        3 Input(s)
            _PIN_TB1, TBB1_part2, TBBSYNC
        1 Fanout(s)
            glb11.I16
        2 Product Term(s)
        1 GLB Level(s)

        TBB1_part2.D = (TBB1_part2 & TBBSYNC
            # _PIN_TB1 & !TBBSYNC)
        TBB1_part2.C = _PIN_CLK

    Output TBB1_part1

        3 Input(s)
            _PIN_TB1, TBB1_part2, TBBSYNC
        1 Fanout(s)
            glb8.I1
        2 Product Term(s)
        1 GLB Level(s)

        TBB1_part1.D = (TBB1_part2 & TBBSYNC
            # _PIN_TB1 & !TBBSYNC)
        TBB1_part1.C = _PIN_CLK


GLB glb12, B0

    8 Input(s)
        (glb6.O0, EE3, I7), (TB2.O, _PIN_TB2, I1), (TB3.O, 
        _PIN_TB3, I0), (glb1.O1, TD0, I10), (glb1.O0, TD1, I11), 
        (glb12.O2, TD2, I13), (glb12.O1, TD3, I14), (glb0.O0, 
        _BUF_869, I15)
    2 Output(s)
        (TD3, O1), (TD2, O2)
    11 Product Term(s)

    Output TD3

        8 Input(s)
            EE3, _PIN_TB2, _PIN_TB3, TD0, TD1, TD2, TD3, _BUF_869
        3 Fanout(s)
            glb1.I1, glb12.I14, glb13.I14
        6 Product Term(s)
        2 GLB Level(s)

        TD3.D = (_PIN_TB2 & !TD3
            # !TD3 & !_PIN_TB3
            # _PIN_TB2 & !TD0 & !TD1 & !TD2
            # !TD0 & !TD1 & !TD2 & !_PIN_TB3
            # !EE3 & !TD0 & !TD1 & !TD2 & !TD3)
            $ VCC
        TD3.C = _PIN_CLK
        TD3.R = _BUF_869

    Output TD2

        7 Input(s)
            _PIN_TB2, _PIN_TB3, TD0, TD1, TD2, TD3, _BUF_869
        3 Fanout(s)
            glb1.I2, glb12.I13, glb13.I13
        6 Product Term(s)
        2 GLB Level(s)

        TD2.D = (TD0 & !TD2
            # TD1 & !TD2
            # !TD2 & !TD3
            # _PIN_TB3 & !_PIN_TB2
            # TD2 & !TD0 & !TD1)
            $ VCC
        TD2.C = _PIN_CLK
        TD2.R = _BUF_869


GLB glb13, B1

    13 Input(s)
        (glb6.O0, EE3, I7), (TB0.O, _PIN_TB0, I3), (TB1.O, 
        _PIN_TB1, I2), (TB2.O, _PIN_TB2, I1), (TB3.O, _PIN_TB3, I0), 
        (glb13.O0, TBB0, I16), (glb13.O3, TBB2, I8), (glb13.O2, 
        TBB3, I9), (glb0.O3, TBBSYNC, I12), (glb1.O1, TD0, I10), 
        (glb1.O0, TD1, I11), (glb12.O2, TD2, I13), (glb12.O1, 
        TD3, I14)
    4 Output(s)
        (TBB3, O2), (TBB2, O3), (TBB0, O0), (CNTE, O1)
    9 Product Term(s)

    Output TBB3

        3 Input(s)
            _PIN_TB3, TBB3, TBBSYNC
        2 Fanout(s)
            glb13.I9, glb9.I9
        2 Product Term(s)
        1 GLB Level(s)

        TBB3.D = (TBB3 & TBBSYNC
            # _PIN_TB3 & !TBBSYNC)
        TBB3.C = _PIN_CLK

    Output TBB2

        3 Input(s)
            _PIN_TB2, TBB2, TBBSYNC
        2 Fanout(s)
            glb13.I8, glb9.I8
        2 Product Term(s)
        1 GLB Level(s)

        TBB2.D = (TBB2 & TBBSYNC
            # _PIN_TB2 & !TBBSYNC)
        TBB2.C = _PIN_CLK

    Output TBB0

        3 Input(s)
            _PIN_TB0, TBB0, TBBSYNC
        2 Fanout(s)
            glb13.I16, glb7.I11
        2 Product Term(s)
        1 GLB Level(s)

        TBB0.D = (TBB0 & TBBSYNC
            # _PIN_TB0 & !TBBSYNC)
        TBB0.C = _PIN_CLK

    Output CNTE

        9 Input(s)
            EE3, _PIN_TB0, _PIN_TB1, _PIN_TB2, _PIN_TB3, TD0, TD1, TD2,
            TD3
        7 Fanout(s)
            glb4_part2.I5, glb1.I5, glb3.I5, glb5.I5, glb2.I5, glb8.I10,
            glb10.I10
        4 Product Term(s)
        1 GLB Level(s)

        CNTE.D = (!EE3 & !TD0 & !TD1 & !TD2 & !TD3
            # _PIN_TB0 & _PIN_TB1 & _PIN_TB2 & _PIN_TB3 & !TD0 & !TD1
            & !TD2 & !TD3
            # !TD0 & !TD1 & !TD2 & !TD3 & !_PIN_TB2 & !_PIN_TB3
            & !_PIN_TB0 & !_PIN_TB1)
            $ VCC
        CNTE.C = _PIN_CLK


GLB glb15, B4

    2 Input(s)
        (glb2.O1, TQ13, I10), (glb3.O2, TQ6, I5)
    2 Output(s)
        (TQ13_buff1, O2), (TQ6_buff1, O3)
    2 Product Term(s)

    Output TQ13_buff1

        1 Input(s)
            TQ13
        1 Fanout(s)
            glb10.I13
        1 Product Term(s)
        1 GLB Level(s)

        TQ13_buff1 = TQ13

    Output TQ6_buff1

        1 Input(s)
            TQ6
        1 Fanout(s)
            glb10.I12
        1 Product Term(s)
        1 GLB Level(s)

        TQ6_buff1 = TQ6


GLB glb2, A5

    17 Input(s)
        (glb13.O1, CNTE, I5), (glb5.O0, TQ0, I12), (glb5.O1, TQ1, I13), 
        (glb5.O2, TQ10, I14), (glb2.O3, TQ11, I7), (glb2.O0, 
        TQ12, I4), (glb2.O1, TQ13, I16), (glb2.O2, TQ14, I17), 
        (glb1.O2, TQ2, I6), (glb5.O3, TQ3, I15), (glb4_part2.O3, 
        TQ4_part1, I3), (glb4_part2.O1, TQ5_part2, I1), (glb3.O2, 
        TQ6, I10), (glb3.O3, TQ7, I11), (glb3.O0, TQ8, I8), (glb3.O1, 
        TQ9, I9), (glb0.O0, _BUF_869, I0)
    4 Output(s)
        (TQ14, O2), (TQ13, O1), (TQ12, O0), (TQ11, O3)
    9 Product Term(s)

    Output TQ14

        17 Input(s)
            CNTE, TQ0, TQ1, TQ10, TQ11, TQ12, TQ13, TQ14, TQ2, TQ3,
            TQ4_part1, TQ5_part2, TQ6, TQ7, TQ8, TQ9, _BUF_869
        3 Fanout(s)
            glb2.I17, glb8.I9, TA14.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ14.D = (TQ14)
            $ CNTE & TQ0 & TQ1 & TQ10 & TQ11 & TQ12 & TQ13 & TQ2 & TQ3
            & TQ4_part1 & TQ5_part2 & TQ6 & TQ7 & TQ8 & TQ9
        TQ14.C = _PIN_CLK
        TQ14.R = _BUF_869

    Output TQ13

        16 Input(s)
            CNTE, TQ0, TQ1, TQ10, TQ11, TQ12, TQ13, TQ2, TQ3, TQ4_part1,
            TQ5_part2, TQ6, TQ7, TQ8, TQ9, _BUF_869
        4 Fanout(s)
            glb2.I16, glb9.I10, glb15.I10, TA13.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ13.D = (TQ13)
            $ CNTE & TQ0 & TQ1 & TQ10 & TQ11 & TQ12 & TQ2 & TQ3
            & TQ4_part1 & TQ5_part2 & TQ6 & TQ7 & TQ8 & TQ9
        TQ13.C = _PIN_CLK
        TQ13.R = _BUF_869

    Output TQ12

        15 Input(s)
            CNTE, TQ0, TQ1, TQ10, TQ11, TQ12, TQ2, TQ3, TQ4_part1,
            TQ5_part2, TQ6, TQ7, TQ8, TQ9, _BUF_869
        4 Fanout(s)
            glb2.I4, glb9.I11, glb10.I11, TA12.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ12.D = (TQ12)
            $ CNTE & TQ0 & TQ1 & TQ10 & TQ11 & TQ2 & TQ3 & TQ4_part1
            & TQ5_part2 & TQ6 & TQ7 & TQ8 & TQ9
        TQ12.C = _PIN_CLK
        TQ12.R = _BUF_869

    Output TQ11

        14 Input(s)
            CNTE, TQ0, TQ1, TQ10, TQ11, TQ2, TQ3, TQ4_part1, TQ5_part2,
            TQ6, TQ7, TQ8, TQ9, _BUF_869
        4 Fanout(s)
            glb2.I7, glb8.I8, glb10.I8, TA11.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ11.D = (TQ11)
            $ CNTE & TQ0 & TQ1 & TQ10 & TQ2 & TQ3 & TQ4_part1
            & TQ5_part2 & TQ6 & TQ7 & TQ8 & TQ9
        TQ11.C = _PIN_CLK
        TQ11.R = _BUF_869


GLB glb3, A2

    12 Input(s)
        (glb13.O1, CNTE, I5), (glb5.O0, TQ0, I12), (glb5.O1, TQ1, I13), 
        (glb1.O2, TQ2, I6), (glb5.O3, TQ3, I15), (glb4_part2.O0, 
        TQ4_part2, I0), (glb4_part2.O2, TQ5_part1, I2), (glb3.O2, 
        TQ6, I10), (glb3.O3, TQ7, I11), (glb3.O0, TQ8, I8), (glb3.O1, 
        TQ9, I9), (glb0.O1, _BUF_870, I1)
    4 Output(s)
        (TQ9, O1), (TQ8, O0), (TQ7, O3), (TQ6, O2)
    9 Product Term(s)

    Output TQ9

        12 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, TQ5_part1, TQ6, TQ7,
            TQ8, TQ9, _BUF_870
        6 Fanout(s)
            glb3.I9, glb5.I9, glb2.I9, glb8.I6, glb10.I6, TA9.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ9.D = (TQ9)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3 & TQ4_part2 & TQ5_part1 & TQ6
            & TQ7 & TQ8
        TQ9.C = _PIN_CLK
        TQ9.R = _BUF_870

    Output TQ8

        11 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, TQ5_part1, TQ6, TQ7,
            TQ8, _BUF_870
        6 Fanout(s)
            glb3.I8, glb5.I8, glb2.I8, glb8.I7, glb10.I7, TA8.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ8.D = (TQ8)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3 & TQ4_part2 & TQ5_part1 & TQ6
            & TQ7
        TQ8.C = _PIN_CLK
        TQ8.R = _BUF_870

    Output TQ7

        10 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, TQ5_part1, TQ6, TQ7,
            _BUF_870
        6 Fanout(s)
            glb3.I11, glb5.I11, glb2.I11, glb7.I4, glb10.I4, TA7.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ7.D = (TQ7)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3 & TQ4_part2 & TQ5_part1 & TQ6
        TQ7.C = _PIN_CLK
        TQ7.R = _BUF_870

    Output TQ6

        9 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, TQ5_part1, TQ6,
            _BUF_870
        6 Fanout(s)
            glb3.I10, glb5.I10, glb2.I10, glb15.I5, glb8.I5, TA6.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ6.D = (TQ6)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3 & TQ4_part2 & TQ5_part1
        TQ6.C = _PIN_CLK
        TQ6.R = _BUF_870


GLB glb4_part1, A7

    3 Input(s)
        (glb6.O1, EE1, I9), (glb9.O2, TB_EN, I10), (glb10.O0, 
        TOV, I12)
    1 Output(s)
        (_OR_470, O3)
    2 Product Term(s)

    Output _OR_470

        3 Input(s)
            EE1, TB_EN, TOV
        1 Fanout(s)
            TB_INT.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_470 = (EE1 & TOV
            # TB_EN & TOV)


GLB glb4_part2, A0

    8 Input(s)
        (glb13.O1, CNTE, I5), (glb5.O0, TQ0, I12), (glb5.O1, TQ1, I13), 
        (glb1.O2, TQ2, I6), (glb5.O3, TQ3, I15), (glb4_part2.O0, 
        TQ4_part2, I0), (glb4_part2.O1, TQ5_part2, I16), (glb0.O1, 
        _BUF_870, I1)
    4 Output(s)
        (TQ5_part2, O1), (TQ4_part2, O0), (TQ5_part1, O2), 
        (TQ4_part1, O3)
    7 Product Term(s)

    Output TQ5_part2

        8 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, TQ5_part2, _BUF_870
        5 Fanout(s)
            glb4_part2.I16, glb5.I1, glb2.I1, glb10.I14, TA5.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ5_part2.D = (TQ5_part2)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3 & TQ4_part2
        TQ5_part2.C = _PIN_CLK
        TQ5_part2.R = _BUF_870

    Output TQ4_part2

        7 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, _BUF_870
        4 Fanout(s)
            glb4_part2.I0, glb3.I0, glb10.I15, TA4.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ4_part2.D = (TQ4_part2)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3
        TQ4_part2.C = _PIN_CLK
        TQ4_part2.R = _BUF_870

    Output TQ5_part1

        8 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, TQ5_part2, _BUF_870
        2 Fanout(s)
            glb3.I2, glb9.I13
        2 Product Term(s)
        2 GLB Level(s)

        TQ5_part1.D = (TQ5_part2)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3 & TQ4_part2
        TQ5_part1.C = _PIN_CLK
        TQ5_part1.R = _BUF_870

    Output TQ4_part1

        7 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, TQ4_part2, _BUF_870
        3 Fanout(s)
            glb5.I3, glb2.I3, glb9.I12
        2 Product Term(s)
        2 GLB Level(s)

        TQ4_part1.D = (TQ4_part2)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3
        TQ4_part1.C = _PIN_CLK
        TQ4_part1.R = _BUF_870


GLB glb5, A3

    13 Input(s)
        (glb13.O1, CNTE, I5), (glb5.O0, TQ0, I12), (glb5.O1, TQ1, I13), 
        (glb5.O2, TQ10, I14), (glb1.O2, TQ2, I6), (glb5.O3, TQ3, I15), 
        (glb4_part2.O3, TQ4_part1, I3), (glb4_part2.O1, 
        TQ5_part2, I1), (glb3.O2, TQ6, I10), (glb3.O3, TQ7, I11), 
        (glb3.O0, TQ8, I8), (glb3.O1, TQ9, I9), (glb0.O0, 
        _BUF_869, I0)
    4 Output(s)
        (TQ3, O3), (TQ10, O2), (TQ1, O1), (TQ0, O0)
    10 Product Term(s)

    Output TQ3

        6 Input(s)
            CNTE, TQ0, TQ1, TQ2, TQ3, _BUF_869
        7 Fanout(s)
            glb4_part2.I15, glb3.I15, glb5.I15, glb2.I15, glb8.I0,
            glb10.I0, TA3.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ3.D = (TQ3)
            $ CNTE & TQ0 & TQ1 & TQ2
        TQ3.C = _PIN_CLK
        TQ3.R = _BUF_869

    Output TQ10

        13 Input(s)
            CNTE, TQ0, TQ1, TQ10, TQ2, TQ3, TQ4_part1, TQ5_part2, TQ6,
            TQ7, TQ8, TQ9, _BUF_869
        5 Fanout(s)
            glb5.I14, glb2.I14, glb7.I1, glb10.I1, TA10.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ10.D = (TQ10)
            $ CNTE & TQ0 & TQ1 & TQ2 & TQ3 & TQ4_part1 & TQ5_part2 & TQ6
            & TQ7 & TQ8 & TQ9
        TQ10.C = _PIN_CLK
        TQ10.R = _BUF_869

    Output TQ1

        4 Input(s)
            CNTE, TQ0, TQ1, _BUF_869
        8 Fanout(s)
            glb4_part2.I13, glb1.I13, glb3.I13, glb5.I13, glb2.I13,
            glb8.I2, glb10.I2, TA1.IR
        3 Product Term(s)
        2 GLB Level(s)

        TQ1.D = (TQ1 & !TQ0
            # TQ1 & !CNTE
            # CNTE & TQ0 & !TQ1)
        TQ1.C = _PIN_CLK
        TQ1.R = _BUF_869

    Output TQ0

        3 Input(s)
            CNTE, TQ0, _BUF_869
        8 Fanout(s)
            glb4_part2.I12, glb1.I12, glb3.I12, glb5.I12, glb2.I12,
            glb8.I3, glb10.I3, TA0.IR
        2 Product Term(s)
        2 GLB Level(s)

        TQ0.D = (CNTE & !TQ0
            # TQ0 & !CNTE)
        TQ0.C = _PIN_CLK
        TQ0.R = _BUF_869


GLB glb6, A6

    10 Input(s)
        (AD4.O, AD4_PIN, I4), (AD5.O, AD5_PIN, I5), (AD6.O, 
        AD6_PIN, I6), (AD7.O, AD7_PIN, I7), (CEN.O, _PIN_CEN, I16), 
        (glb6.O3, EE0, I11), (glb6.O1, EE1, I9), (glb6.O2, EE2, I10), 
        (glb6.O0, EE3, I8), (glb0.O0, _BUF_869, I0)
    4 Output(s)
        (EE3, O0), (EE2, O2), (EE1, O1), (EE0, O3)
    9 Product Term(s)

    Output EE3

        4 Input(s)
            AD7_PIN, _PIN_CEN, EE3, _BUF_869
        5 Fanout(s)
            glb0.I8, glb6.I8, glb12.I7, glb13.I7, glb7.I7
        2 Product Term(s)
        2 GLB Level(s)

        EE3.D = (AD7_PIN & !_PIN_CEN
            # _PIN_CEN & EE3)
        EE3.C = _PIN_WRN
        EE3.R = _BUF_869

    Output EE2

        4 Input(s)
            AD6_PIN, _PIN_CEN, EE2, _BUF_869
        3 Fanout(s)
            glb6.I10, glb9.I5, glb10.I5
        2 Product Term(s)
        2 GLB Level(s)

        EE2.D = (AD6_PIN & !_PIN_CEN
            # _PIN_CEN & EE2)
        EE2.C = _PIN_WRN
        EE2.R = _BUF_869

    Output EE1

        4 Input(s)
            AD5_PIN, _PIN_CEN, EE1, _BUF_869
        2 Fanout(s)
            glb6.I9, glb4_part1.I9
        2 Product Term(s)
        2 GLB Level(s)

        EE1.D = (AD5_PIN & !_PIN_CEN
            # _PIN_CEN & EE1)
        EE1.C = _PIN_WRN
        EE1.R = _BUF_869

    Output EE0

        4 Input(s)
            AD4_PIN, _PIN_CEN, EE0, _BUF_869
        2 Fanout(s)
            glb6.I11, glb9.I4
        2 Product Term(s)
        2 GLB Level(s)

        EE0.D = (_PIN_CEN & EE0
            # AD4_PIN & !_PIN_CEN)
        EE0.C = _PIN_WRN
        EE0.R = _BUF_869


GLB glb7, B6

    12 Input(s)
        (AD0.O, AA0, I15), (AD1.O, AA1, I14), (CSN.O, _PIN_CSN, I16), 
        (DEN.O, _PIN_DEN, I17), (glb6.O0, EE3, I7), (RDN.O, 
        _PIN_RDN, I5), (glb13.O0, TBB0, I11), (glb10.O0, TOV, I3), 
        (glb5.O2, TQ10, I1), (glb1.O2, TQ2, I9), (glb3.O3, TQ7, I4), 
        (glb0.O2, _BUF_871, I13)
    4 Output(s)
        (_BUF_900, O0), (_AND_735, O1), (AD7_D, O3), (AD2_D, O2)
    1 Enable Output
        AD7_OE
    8 Product Term(s)

    Output _BUF_900

        1 Input(s)
            EE3
        1 Fanout(s)
            TEN.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_900 = EE3

    Output _AND_735

        2 Input(s)
            _PIN_CSN, _PIN_DEN
        1 Fanout(s)
            TDEN.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_735 = !_PIN_CSN & !_PIN_DEN

    Output AD7_D

        4 Input(s)
            AA0, AA1, TOV, TQ7
        1 Fanout(s)
            AD7.IR
        2 Product Term(s)
        1 GLB Level(s)

        AD7_D = (TQ7 & !AA0
            # AA0 & AA1 & TOV)

    Output AD2_D

        5 Input(s)
            AA0, AA1, TBB0, TQ10, TQ2
        1 Fanout(s)
            AD2.IR
        3 Product Term(s)
        1 GLB Level(s)

        AD2_D = (TQ2 & !AA0
            # AA0 & TQ10 & !AA1
            # AA0 & AA1 & TBB0)

    Enable Output AD7_OE

        2 Input(s)
            _PIN_RDN, _BUF_871
        8 Fanout(s)
            AD7.OE1, AD6.OE1, AD5.OE1, AD4.OE1, AD3.OE1, AD2.OE1,
            AD1.OE1, AD0.OE1
        1 Product Term(s)
        2 GLB Level(s)

        AD7_OE = !_PIN_RDN & !_BUF_871


GLB glb8, B5

    12 Input(s)
        (AD0.O, AA0, I15), (AD1.O, AA1, I14), (glb13.O1, CNTE, I10), 
        (glb11.O2, TBB1_part1, I1), (glb5.O0, TQ0, I3), (glb5.O1, 
        TQ1, I2), (glb2.O3, TQ11, I8), (glb2.O2, TQ14, I9), (glb5.O3, 
        TQ3, I0), (glb3.O2, TQ6, I5), (glb3.O0, TQ8, I7), (glb3.O1, 
        TQ9, I6)
    4 Output(s)
        (AD6_D, O2), (AD3_D, O3), (AD1_D, O1), (AD0_D, O0)
    10 Product Term(s)

    Output AD6_D

        5 Input(s)
            AA0, AA1, CNTE, TQ14, TQ6
        1 Fanout(s)
            AD6.IR
        3 Product Term(s)
        1 GLB Level(s)

        AD6_D = (TQ6 & !AA0
            # AA0 & AA1 & CNTE
            # AA0 & TQ14 & !AA1)

    Output AD3_D

        5 Input(s)
            AA0, AA1, TBB1_part1, TQ11, TQ3
        1 Fanout(s)
            AD3.IR
        3 Product Term(s)
        1 GLB Level(s)

        AD3_D = (TQ3 & !AA0
            # AA0 & TQ11 & !AA1
            # AA0 & AA1 & TBB1_part1)

    Output AD1_D

        4 Input(s)
            AA0, AA1, TQ1, TQ9
        1 Fanout(s)
            AD1.IR
        2 Product Term(s)
        1 GLB Level(s)

        AD1_D = (TQ1 & !AA0
            # AA0 & TQ9 & !AA1)

    Output AD0_D

        4 Input(s)
            AA0, AA1, TQ0, TQ8
        1 Fanout(s)
            AD0.IR
        2 Product Term(s)
        1 GLB Level(s)

        AD0_D = (TQ0 & !AA0
            # AA0 & TQ8 & !AA1)


GLB glb9, B2

    15 Input(s)
        (AD0.O, AA0, I15), (AD1.O, AA1, I14), (glb6.O3, EE0, I4), 
        (glb6.O2, EE2, I5), (TB0.O, _PIN_TB0, I3), (TB1.O, 
        _PIN_TB1, I2), (TB2.O, _PIN_TB2, I1), (TB3.O, _PIN_TB3, I0), 
        (glb13.O3, TBB2, I8), (glb13.O2, TBB3, I9), (glb9.O2, 
        TB_EN, I16), (glb2.O0, TQ12, I11), (glb2.O1, TQ13, I10), 
        (glb4_part2.O3, TQ4_part1, I12), (glb4_part2.O2, 
        TQ5_part1, I13)
    4 Output(s)
        (_OR_474, O3), (TB_EN, O2), (AD5_D, O1), (AD4_D, O0)
    11 Product Term(s)

    Output _OR_474

        5 Input(s)
            EE0, _PIN_TB0, _PIN_TB1, _PIN_TB2, _PIN_TB3
        1 Fanout(s)
            ACTN.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_474 = (_PIN_TB0 & _PIN_TB1 & _PIN_TB2 & _PIN_TB3 & !EE0
            # !EE0 & !_PIN_TB2 & !_PIN_TB3 & !_PIN_TB0 & !_PIN_TB1)

    Output TB_EN

        6 Input(s)
            EE2, _PIN_TB0, _PIN_TB1, _PIN_TB2, _PIN_TB3, TB_EN
        2 Fanout(s)
            glb4_part1.I10, glb9.I16
        2 Product Term(s)
        1 GLB Level(s)

        TB_EN.D = (TB_EN
            # _PIN_TB0 & _PIN_TB1 & _PIN_TB2 & !_PIN_TB3)
        TB_EN.C = _PIN_CLK
        TB_EN.R = EE2

    Output AD5_D

        5 Input(s)
            AA0, AA1, TBB3, TQ13, TQ5_part1
        1 Fanout(s)
            AD5.IR
        3 Product Term(s)
        1 GLB Level(s)

        AD5_D = (TQ5_part1 & !AA0
            # AA0 & TQ13 & !AA1
            # AA0 & AA1 & TBB3)

    Output AD4_D

        5 Input(s)
            AA0, AA1, TBB2, TQ12, TQ4_part1
        1 Fanout(s)
            AD4.IR
        3 Product Term(s)
        1 GLB Level(s)

        AD4_D = (TQ4_part1 & !AA0
            # AA0 & TQ12 & !AA1
            # AA0 & AA1 & TBB2)


Output ACTN, IO27

    Input (glb9.O3, _OR_474)

    ACTN = _OR_474


Registered Bidirectional AD0, IO16

    Input (glb8.O0, AD0_D)
    Output AA0
        3 Fanout(s)
            glb9.I15, glb8.I15, glb7.I15
    Enable (glb7.OE, AD7_OE)

    AD0 = AD0_D
    AD0.E = AD7_OE
    AD0.G = _PIN_ALE


Registered Bidirectional AD1, IO17

    Input (glb8.O1, AD1_D)
    Output AA1
        3 Fanout(s)
            glb9.I14, glb8.I14, glb7.I14
    Enable (glb7.OE, AD7_OE)

    AD1 = AD1_D
    AD1.E = AD7_OE
    AD1.G = _PIN_ALE


Three-State Output AD2, IO18

    Input (glb7.O2, AD2_D)
    Enable (glb7.OE, AD7_OE)

    AD2 = AD2_D
    AD2.E = AD7_OE


Three-State Output AD3, IO19

    Input (glb8.O3, AD3_D)
    Enable (glb7.OE, AD7_OE)

    AD3 = AD3_D
    AD3.E = AD7_OE


Bidirectional AD4, IO20

    Input (glb9.O0, AD4_D)
    Output AD4_PIN
        1 Fanout(s)
            glb6.I4
    Enable (glb7.OE, AD7_OE)

    AD4 = AD4_D
    AD4.E = AD7_OE


Bidirectional AD5, IO21

    Input (glb9.O1, AD5_D)
    Output AD5_PIN
        1 Fanout(s)
            glb6.I5
    Enable (glb7.OE, AD7_OE)

    AD5 = AD5_D
    AD5.E = AD7_OE


Bidirectional AD6, IO22

    Input (glb8.O2, AD6_D)
    Output AD6_PIN
        1 Fanout(s)
            glb6.I6
    Enable (glb7.OE, AD7_OE)

    AD6 = AD6_D
    AD6.E = AD7_OE


Bidirectional AD7, IO23

    Input (glb7.O3, AD7_D)
    Output AD7_PIN
        1 Fanout(s)
            glb6.I7
    Enable (glb7.OE, AD7_OE)

    AD7 = AD7_D
    AD7.E = AD7_OE


Clock Input ALE, Y2

    Output _PIN_ALE
        2 Fanout(s)
            AD1.CLK1, AD0.CLK1


Dedicated Input CEN, I0

    Output _PIN_CEN
        2 Fanout(s)
            glb0.I16, glb6.I16


Clock Input CLK, Y0

    Output _PIN_CLK
        11 Fanout(s)
            glb4_part2.CLK0, glb1.CLK0, glb3.CLK0, glb5.CLK0, glb0.CLK0,
            glb2.CLK0, glb12.CLK0, glb13.CLK0, glb9.CLK0, glb11.CLK0,
            glb10.CLK0


Dedicated Input CSN, I2

    Output _PIN_CSN
        1 Fanout(s)
            glb7.I16


Dedicated Input DEN, I3

    Output _PIN_DEN
        1 Fanout(s)
            glb7.I17


Input RDN, IO26

    Output _PIN_RDN
        1 Fanout(s)
            glb7.I5


Three-State Output TA0, IO0

    Input (glb5.O0, TQ0)
    Enable (glb0.OE, _BUF_873)

    TA0 = TQ0
    TA0.E = _BUF_873


Three-State Output TA1, IO1

    Input (glb5.O1, TQ1)
    Enable (glb0.OE, _BUF_873)

    TA1 = TQ1
    TA1.E = _BUF_873


Three-State Output TA10, IO10

    Input (glb5.O2, TQ10)
    Enable (glb0.OE, _BUF_873)

    TA10 = TQ10
    TA10.E = _BUF_873


Three-State Output TA11, IO11

    Input (glb2.O3, TQ11)
    Enable (glb0.OE, _BUF_873)

    TA11 = TQ11
    TA11.E = _BUF_873


Three-State Output TA12, IO12

    Input (glb2.O0, TQ12)
    Enable (glb0.OE, _BUF_873)

    TA12 = TQ12
    TA12.E = _BUF_873


Three-State Output TA13, IO13

    Input (glb2.O1, TQ13)
    Enable (glb0.OE, _BUF_873)

    TA13 = TQ13
    TA13.E = _BUF_873


Three-State Output TA14, IO14

    Input (glb2.O2, TQ14)
    Enable (glb0.OE, _BUF_873)

    TA14 = TQ14
    TA14.E = _BUF_873


Three-State Output TA2, IO2

    Input (glb1.O2, TQ2)
    Enable (glb0.OE, _BUF_873)

    TA2 = TQ2
    TA2.E = _BUF_873


Three-State Output TA3, IO3

    Input (glb5.O3, TQ3)
    Enable (glb0.OE, _BUF_873)

    TA3 = TQ3
    TA3.E = _BUF_873


Three-State Output TA4, IO4

    Input (glb4_part2.O0, TQ4_part2)
    Enable (glb0.OE, _BUF_873)

    TA4 = TQ4_part2
    TA4.E = _BUF_873


Three-State Output TA5, IO5

    Input (glb4_part2.O1, TQ5_part2)
    Enable (glb0.OE, _BUF_873)

    TA5 = TQ5_part2
    TA5.E = _BUF_873


Three-State Output TA6, IO6

    Input (glb3.O2, TQ6)
    Enable (glb0.OE, _BUF_873)

    TA6 = TQ6
    TA6.E = _BUF_873


Three-State Output TA7, IO7

    Input (glb3.O3, TQ7)
    Enable (glb0.OE, _BUF_873)

    TA7 = TQ7
    TA7.E = _BUF_873


Three-State Output TA8, IO8

    Input (glb3.O0, TQ8)
    Enable (glb0.OE, _BUF_873)

    TA8 = TQ8
    TA8.E = _BUF_873


Three-State Output TA9, IO9

    Input (glb3.O1, TQ9)
    Enable (glb0.OE, _BUF_873)

    TA9 = TQ9
    TA9.E = _BUF_873


Input TB0, IO28

    Output _PIN_TB0
        2 Fanout(s)
            glb13.I3, glb9.I3


Input TB1, IO29

    Output _PIN_TB1
        3 Fanout(s)
            glb13.I2, glb9.I2, glb11.I2


Input TB2, IO30

    Output _PIN_TB2
        4 Fanout(s)
            glb1.I14, glb12.I1, glb13.I1, glb9.I1


Input TB3, IO31

    Output _PIN_TB3
        4 Fanout(s)
            glb1.I15, glb12.I0, glb13.I0, glb9.I0


Output TB_INT, IO15

    Input (glb4_part1.O3, _OR_470)

    TB_INT = _OR_470


Output TDEN, IO25

    Input (glb7.O1, _AND_735)

    TDEN = !_AND_735


Output TEN, IO24

    Input (glb7.O0, _BUF_900)

    TEN = !_BUF_900


Clock Input WRN, Y1

    Output _PIN_WRN
        1 Fanout(s)
            glb6.CLK1


Dedicated Input _KWD_RST, I1

    Output _PIN__KWD_RST
        1 Fanout(s)
            glb0.I17


Clock Assignments

    Net Name		    Clock Assignment

        _PIN_CLK                External CLK0
        _PIN_WRN                External CLK1
        _PIN_ALE                External IOCLK1


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb0, A4                 3,  4,  6          
            TBBSYNC                                      1,  2,  1,  1      
            _BUF_869                                     1,  5,  1,  1      
            _BUF_870                                     1,  2,  1,  1      
            _BUF_871                                     1,  1,  1,  1      

        glb1, A1                11,  3, 12          
            TD0                                          7,  3,  4,  2      
            TD1                                          7,  3,  5,  2      
            TQ2                                          5,  8,  4,  2      

        glb10, B7               17,  1,  3          
            TOV                                         17,  3,  2,  2      

        glb11, B3                3,  2,  2          
            TBB1_part1                                   3,  1,  2,  1      
            TBB1_part2                                   3,  1,  2,  1      

        glb12, B0                8,  2, 11          
            TD2                                          7,  3,  6,  2      
            TD3                                          8,  3,  6,  2      

        glb13, B1               13,  4,  9          
            CNTE                                         9,  7,  4,  1      
            TBB0                                         3,  2,  2,  1      
            TBB2                                         3,  2,  2,  1      
            TBB3                                         3,  2,  2,  1      

        glb15, B4                2,  2,  2          
            TQ13_buff1                                   1,  1,  1,  1      
            TQ6_buff1                                    1,  1,  1,  1      

        glb2, A5                17,  4,  9          
            TQ11                                        14,  4,  2,  2      
            TQ12                                        15,  4,  2,  2      
            TQ13                                        16,  4,  2,  2      
            TQ14                                        17,  3,  2,  2      

        glb3, A2                12,  4,  9          
            TQ6                                          9,  6,  2,  2      
            TQ7                                         10,  6,  2,  2      
            TQ8                                         11,  6,  2,  2      
            TQ9                                         12,  6,  2,  2      

        glb4_part1, A7           3,  1,  2          
            _OR_470                                      3,  1,  2,  1      

        glb4_part2, A0           8,  4,  7          
            TQ4_part1                                    7,  3,  2,  2      
            TQ4_part2                                    7,  4,  2,  2      
            TQ5_part1                                    8,  2,  2,  2      
            TQ5_part2                                    8,  5,  2,  2      

        glb5, A3                13,  4, 10          
            TQ0                                          3,  8,  2,  2      
            TQ1                                          4,  8,  3,  2      
            TQ10                                        13,  5,  2,  2      
            TQ3                                          6,  7,  2,  2      

        glb6, A6                10,  4,  9          
            EE0                                          4,  2,  2,  2      
            EE1                                          4,  2,  2,  2      
            EE2                                          4,  3,  2,  2      
            EE3                                          4,  5,  2,  2      

        glb7, B6                12,  4,  8          
            AD2_D                                        5,  1,  3,  1      
            AD7_D                                        4,  1,  2,  1      
            _AND_735                                     2,  1,  1,  1      
            _BUF_900                                     1,  1,  1,  1      

        glb8, B5                12,  4, 10          
            AD0_D                                        4,  1,  2,  1      
            AD1_D                                        4,  1,  2,  1      
            AD3_D                                        5,  1,  3,  1      
            AD6_D                                        5,  1,  3,  1      

        glb9, B2                15,  4, 11          
            AD4_D                                        5,  1,  3,  1      
            AD5_D                                        5,  1,  3,  1      
            TB_EN                                        6,  2,  2,  1      
            _OR_474                                      5,  1,  2,  1      


Maximum-Level Trace

    GLB Level, Name, Ins    GLB Output Name

        2, glb1, 5              TQ2                 
        1, glb0                  _BUF_869            

        2, glb1, 7              TD1                 
        1, glb0                  _BUF_869            

        2, glb1, 7              TD0                 
        1, glb0                  _BUF_869            

        2, glb10, 17            TOV                 
        1, glb15                 TQ13_buff1          
        1, glb15                 TQ6_buff1           

        2, glb12, 8             TD3                 
        1, glb0                  _BUF_869            

        2, glb12, 7             TD2                 
        1, glb0                  _BUF_869            

        2, glb2, 17             TQ14                
        1, glb0                  _BUF_869            

        2, glb2, 16             TQ13                
        1, glb0                  _BUF_869            

        2, glb2, 15             TQ12                
        1, glb0                  _BUF_869            

        2, glb2, 14             TQ11                
        1, glb0                  _BUF_869            


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        DEN                     2                       Dedicated Input
        TEN                     3                       Output
        TDEN                    4                       Output
        RDN                     5                       Input
        ACTN                    6                       Output
        TB0                     7                       Input
        TB1                     8                       Input
        TB2                     9                       Input
        TB3                     10                      Input
        CLK                     11                      Clock Input
        CEN                     14                      Dedicated Input
        TA0                     15                      Three-State Output
        TA1                     16                      Three-State Output
        TA2                     17                      Three-State Output
        TA3                     18                      Three-State Output
        TA4                     19                      Three-State Output
        TA5                     20                      Three-State Output
        TA6                     21                      Three-State Output
        TA7                     22                      Three-State Output
        _KWD_RST                24                      Dedicated Input
        TA8                     25                      Three-State Output
        TA9                     26                      Three-State Output
        TA10                    27                      Three-State Output
        TA11                    28                      Three-State Output
        TA12                    29                      Three-State Output
        TA13                    30                      Three-State Output
        TA14                    31                      Three-State Output
        TB_INT                  32                      Output
        ALE                     33                      Clock Input
        WRN                     35                      Clock Input
        CSN                     36                      Dedicated Input
        AD0                     37                      Registered Bidirectional
        AD1                     38                      Registered Bidirectional
        AD2                     39                      Three-State Output
        AD3                     40                      Three-State Output
        AD4                     41                      Bidirectional
        AD5                     42                      Bidirectional
        AD6                     43                      Bidirectional
        AD7                     44                      Bidirectional


Design process management completed successfully
