(is)pLSI Development System Plus Release 2.1.13, Jun  5 1995 10:02:40


Design Parameters
-----------------

IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16 ((is)pLSI1000,(is)pLSI2000), 24((is)pLSI3000)
MAX_GLB_OUT:                    4
STRATEGY:                       AREA


Design Specification
--------------------

Design:                         BDM24B
Part:                           pLSI1024-60LJ68


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          27


Input Pins

    Pin Name                Pin Attribute

        A0                      LOCK 62
        BCLK                    LOCK 54
        CLK                     LOCK 16
        C_TEA                   LOCK 13
        DSO                     LOCK 30
        NCSCTRL                 LOCK 8
        NCSDATA                 LOCK 7
        NRD                     LOCK 22
        NWR                     LOCK 29
        RUN                     LOCK 31
        TOV                     LOCK 66
        VCC_B3                  LOCK 33
        VCC_B5                  LOCK 32


Output Pins

    Pin Name                Pin Attribute

        BKPTSYNC                LOCK 5
        DSCLK                   LOCK 6
        DSI                     LOCK 4
        ECLK                    LOCK 14
        NTEA                    LOCK 3, PULLUP
        WRTEST                  LOCK 61


Bidirectional Pins

    Pin Name                Pin Attribute

        AD0                     LOCK 37
        AD1                     LOCK 38
        AD2                     LOCK 39
        AD3                     LOCK 40
        AD4                     LOCK 47
        AD5                     LOCK 48
        AD6                     LOCK 42
        AD7                     LOCK 41


Pre-Route Design Statistics
---------------------------

Number of GLBs:                 18
Number of I/Os:                 25
Number of Nets:                 85

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    11
Number of Locked DIs:           0
Number of Locked Outputs:       5
Number of Locked Three-States:  1
Number of Locked Bidi's:        8

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      2


GLB Utilization (Out of 24):	75%
I/O Utilization (Out of 54):	46%
Net Utilization (Out of 150):	56%


Nets with Fanout of  1:         24
Nets with Fanout of  2:         39
Nets with Fanout of  3:         13
Nets with Fanout of  4:         1
Nets with Fanout of  5:         1
Nets with Fanout of  6:         1
Nets with Fanout of  7:         2
Nets with Fanout of  8:         4

Average Fanout per Net:         2.38


GLBs with  4 Input(s):          3
GLBs with  7 Input(s):          2
GLBs with  8 Input(s):          1
GLBs with  9 Input(s):          5
GLBs with 11 Input(s):          1
GLBs with 13 Input(s):          1
GLBs with 16 Input(s):          1
GLBs with 17 Input(s):          3
GLBs with 18 Input(s):          1

Average Inputs per GLB:         10.44


GLBs with  1 Output(s):         1
GLBs with  2 Output(s):         1
GLBs with  3 Output(s):         1
GLBs with  4 Output(s):         15

Average Outputs per GLB:        3.67


Output Enable Nets

    Net Name                Net Fanout

        NTEA_OE                 1
        _BUF_843                4
        _BUF_842                4


Post-Route Design Implementation
--------------------------------

Number of GLBs:			24
Number of IOCs:			25
Number of DIs:			0
Number of GLB Levels:		3


GLB glb0, B4

    13 Input(s)
        (NCSCTRL.O, _PIN_NCSCTRL, I6), (glb7.O1, SQ4, I14), (glb7.O2, 
        SQ5, I13), (glb1.O3, SQ7, I0), (glb9_part2.O2, SQC, I9), 
        (glb8_part1.O0, SQD_part2, I7), (glb6.O3, SQF, I8), (glb12.O0, 
        TEASYNC1, I3), (VCC_B3.O, _PIN_VCC_B3, I4), (glb11.O2, 
        WRTMP, I5), (glb10_part2.O1, _AND_385, I2), (glb10_part1.O0, 
        _AND_386_part2, I15), (glb13.O0, _OR_419, I11)
    4 Output(s)
        (WRDELAY, O1), (AD7_D, O0), (AD5_D, O3), (AD4_D, O2)
    1 Enable Output
        _BUF_843
    10 Product Term(s)

    Output WRDELAY

        1 Input(s)
            WRTMP
        5 Fanout(s)
            glb9_part2.I1, glb11.I14, glb12.I14, glb9_part1.I14,
            WRTEST.IR
        1 Product Term(s)
        1 GLB Level(s)

        WRDELAY.D = WRTMP
        WRDELAY.C = _PIN_BCLK

    Output AD7_D

        6 Input(s)
            _PIN_NCSCTRL, SQ7, SQF, TEASYNC1, _AND_385, _AND_386_part2
        1 Fanout(s)
            AD7.IR
        3 Product Term(s)
        2 GLB Level(s)

        AD7_D = (SQF & _AND_385
            # SQ7 & _AND_386_part2
            # TEASYNC1 & !_PIN_NCSCTRL)

    Output AD5_D

        4 Input(s)
            SQ5, SQD_part2, _AND_385, _AND_386_part2
        1 Fanout(s)
            AD5.IR
        2 Product Term(s)
        2 GLB Level(s)

        AD5_D = (SQD_part2 & _AND_385
            # SQ5 & _AND_386_part2)

    Output AD4_D

        6 Input(s)
            _PIN_NCSCTRL, SQ4, SQC, _PIN_VCC_B3, _AND_385,
            _AND_386_part2
        1 Fanout(s)
            AD4.IR
        3 Product Term(s)
        2 GLB Level(s)

        AD4_D = (SQC & _AND_385
            # SQ4 & _AND_386_part2
            # _PIN_VCC_B3 & !_PIN_NCSCTRL)

    Enable Output _BUF_843

        1 Input(s)
            _OR_419
        4 Fanout(s)
            AD7.OE1, AD6.OE1, AD5.OE1, AD4.OE1
        1 Product Term(s)
        2 GLB Level(s)

        _BUF_843 = _OR_419


GLB glb1, B3

    17 Input(s)
        (glb12.O3, B0, I15), (glb9_part1.O3, B1_part1, I3), (glb12.O2, 
        B2, I14), (glb9_part2.O0, B3, I4), (glb9_part2.O1, 
        B4_part2, I5), (glb16_part1.O3, BUF7, I11), (glb14_part2.O2, 
        BUF8, I6), (glb14_part2.O3, BUF9_part1, I7), (glb3.O2, 
        SQ0_CE, I10), (glb8_part1.O1, SQ6, I9), (glb1.O3, SQ7, I17), 
        (glb1.O2, SQ8, I16), (glb1.O0, SQ9, I12), (glb7.O0, SQE, I0), 
        (glb10_part2.O1, _AND_385, I13), (glb10_part1.O1, 
        _AND_386_part1, I1), (glb3.O0, _OR_407, I8)
    4 Output(s)
        (SQ9, O0), (SQ8, O2), (SQ7, O3), (AD6_D, O1)
    14 Product Term(s)

    Output SQ9

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part2, BUF9_part1, SQ0_CE, SQ8, SQ9,
            _OR_407
        3 Fanout(s)
            glb4_part2.I12, glb8_part2.I12, glb1.I12
        4 Product Term(s)
        3 GLB Level(s)

        SQ9.D = (SQ9 & !SQ0_CE
            # SQ8 & !_OR_407
            # B0 & B1_part1 & B4_part2 & BUF9_part1 & SQ0_CE & !B2 & !B3
            # BUF9_part1 & SQ0_CE & !B2 & !B3 & !B0 & !B1_part1
            & !B4_part2)
        SQ9.C = _PIN_BCLK

    Output SQ8

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part2, BUF8, SQ0_CE, SQ7, SQ8,
            _OR_407
        2 Fanout(s)
            glb4_part2.I14, glb1.I16
        4 Product Term(s)
        3 GLB Level(s)

        SQ8.D = (SQ8 & !SQ0_CE
            # SQ7 & !_OR_407
            # B0 & B1_part1 & B4_part2 & BUF8 & SQ0_CE & !B2 & !B3
            # BUF8 & SQ0_CE & !B2 & !B3 & !B0 & !B1_part1 & !B4_part2)
        SQ8.C = _PIN_BCLK

    Output SQ7

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part2, BUF7, SQ0_CE, SQ6, SQ7,
            _OR_407
        2 Fanout(s)
            glb1.I17, glb0.I0
        4 Product Term(s)
        3 GLB Level(s)

        SQ7.D = (SQ7 & !SQ0_CE
            # SQ6 & !_OR_407
            # B0 & B1_part1 & B4_part2 & BUF7 & SQ0_CE & !B2 & !B3
            # BUF7 & SQ0_CE & !B2 & !B3 & !B0 & !B1_part1 & !B4_part2)
        SQ7.C = _PIN_BCLK

    Output AD6_D

        4 Input(s)
            SQ6, SQE, _AND_385, _AND_386_part1
        1 Fanout(s)
            AD6.IR
        2 Product Term(s)
        2 GLB Level(s)

        AD6_D = (SQE & _AND_385
            # SQ6 & _AND_386_part1)


GLB glb10_part1, B0

    4 Input(s)
        (A0.O, _PIN_A0, I14), (NCSCTRL.O, _PIN_NCSCTRL, I9), 
        (NCSDATA.O, _PIN_NCSDATA, I8), (NWR.O, _PIN_NWR, I7)
    4 Output(s)
        (_AND_386_part2, O0), (WRTMP_AR, O3), (BUF7_CE, O2), 
        (_AND_386_part1, O1)
    4 Product Term(s)

    Output _AND_386_part2

        2 Input(s)
            _PIN_A0, _PIN_NCSCTRL
        2 Fanout(s)
            glb4_part2.I0, glb0.I15
        1 Product Term(s)
        1 GLB Level(s)

        _AND_386_part2 = _PIN_NCSCTRL & !_PIN_A0

    Output WRTMP_AR

        3 Input(s)
            _PIN_A0, _PIN_NCSDATA, _PIN_NWR
        4 Fanout(s)
            glb14_part2.I12, glb11.I12, glb15.I12, glb14_part1.I12
        1 Product Term(s)
        1 GLB Level(s)

        WRTMP_AR = _PIN_A0 & !_PIN_NCSDATA & !_PIN_NWR

    Output BUF7_CE

        3 Input(s)
            _PIN_A0, _PIN_NCSDATA, _PIN_NWR
        3 Fanout(s)
            glb17.I2, glb16_part1.I2, glb16_part2.I13
        1 Product Term(s)
        1 GLB Level(s)

        BUF7_CE = !_PIN_NCSDATA & !_PIN_NWR & !_PIN_A0

    Output _AND_386_part1

        2 Input(s)
            _PIN_A0, _PIN_NCSCTRL
        2 Fanout(s)
            glb4_part1.I1, glb1.I1
        1 Product Term(s)
        1 GLB Level(s)

        _AND_386_part1 = _PIN_NCSCTRL & !_PIN_A0


GLB glb10_part2, C3

    2 Input(s)
        (A0.O, _PIN_A0, I1), (NCSCTRL.O, _PIN_NCSCTRL, I6)
    1 Output(s)
        (_AND_385, O1)
    1 Product Term(s)

    Output _AND_385

        2 Input(s)
            _PIN_A0, _PIN_NCSCTRL
        4 Fanout(s)
            glb4_part2.I13, glb4_part1.I13, glb1.I13, glb0.I2
        1 Product Term(s)
        1 GLB Level(s)

        _AND_385 = _PIN_A0 & _PIN_NCSCTRL


GLB glb11, B6

    9 Input(s)
        (glb12.O3, B0, I0), (glb9_part1.O0, B1_part2, I15), (glb12.O2, 
        B2, I1), (glb9_part2.O0, B3, I11), (glb9_part2.O1, 
        B4_part2, I10), (RUN.O, _PIN_RUN, I6), (glb0.O1, WRDELAY, I14), 
        (glb11.O2, WRTMP, I5), (glb10_part1.O3, WRTMP_AR, I12)
    3 Output(s)
        (_BUF_841, O3), (WRTMP, O2), (BDM_BZY, O0)
    3 Product Term(s)

    Output _BUF_841

        1 Input(s)
            _PIN_RUN
        1 Fanout(s)
            glb4_part1.I11
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_841 = _PIN_RUN

    Output WRTMP

        1 Input(s)
            WRTMP_AR
        2 Fanout(s)
            glb0.I5, glb11.I5
        0 Product Term(s)
        2 GLB Level(s)

        WRTMP.D = VCC
        WRTMP.C = _PIN_BCLK
        WRTMP.R = WRTMP_AR

    Output BDM_BZY

        8 Input(s)
            B0, B1_part2, B2, B3, B4_part2, WRDELAY, WRTMP, WRTMP_AR
        1 Fanout(s)
            glb4_part2.I8
        1 Product Term(s)
        2 GLB Level(s)

        BDM_BZY.D = WRDELAY & WRTMP & !B2 & !B3 & !B0 & !B1_part2
            & !B4_part2
        BDM_BZY.C = _PIN_BCLK
        BDM_BZY.R = WRTMP_AR


GLB glb12, B7

    7 Input(s)
        (glb12.O3, B0, I0), (glb9_part1.O0, B1_part2, I15), (glb12.O2, 
        B2, I16), (C_TEA.O, _PIN_C_TEA, I1), (DSO.O, _PIN_DSO, I7), 
        (glb3.O2, SQ0_CE, I5), (glb0.O1, WRDELAY, I14)
    4 Output(s)
        (TEASYNC1, O0), (SQTMP, O1), (B2, O2), (B0, O3)
    8 Product Term(s)

    Output TEASYNC1

        1 Input(s)
            _PIN_C_TEA
        2 Fanout(s)
            glb0.I3, glb2.I3
        1 Product Term(s)
        1 GLB Level(s)

        TEASYNC1.D = _PIN_C_TEA
        TEASYNC1.C = _PIN_BCLK

    Output SQTMP

        1 Input(s)
            _PIN_DSO
        1 Fanout(s)
            glb6.I2
        1 Product Term(s)
        1 GLB Level(s)

        SQTMP.D = _PIN_DSO
        SQTMP.C = _PIN_BCLK

    Output B2

        5 Input(s)
            B0, B1_part2, B2, SQ0_CE, WRDELAY
        9 Fanout(s)
            glb7.I14, glb8_part1.I14, glb8_part2.I14, glb9_part2.I14,
            glb1.I14, glb11.I1, glb12.I16, glb6.I1, glb3.I1
        4 Product Term(s)
        2 GLB Level(s)

        B2.D = (B0 & B2 & WRDELAY
            # B1_part2 & B2 & WRDELAY
            # B2 & WRDELAY & !SQ0_CE
            # SQ0_CE & WRDELAY & !B2 & !B0 & !B1_part2)
        B2.C = _PIN_BCLK

    Output B0

        3 Input(s)
            B0, SQ0_CE, WRDELAY
        10 Fanout(s)
            glb7.I15, glb8_part1.I15, glb8_part2.I15, glb9_part2.I15,
            glb1.I15, glb11.I0, glb12.I0, glb9_part1.I0, glb6.I0,
            glb3.I0
        3 Product Term(s)
        2 GLB Level(s)

        B0.D = (B0 & SQ0_CE & WRDELAY
            # WRDELAY & !SQ0_CE & !B0)
            $ VCC
        B0.C = _PIN_BCLK


GLB glb13, B1

    4 Input(s)
        (NCSCTRL.O, _PIN_NCSCTRL, I9), (NCSDATA.O, _PIN_NCSDATA, I8), 
        (NRD.O, _PIN_NRD, I0), (glb2.O0, TEASYNC2, I4)
    2 Output(s)
        (_OR_419, O0), (TEASYNC3, O1)
    3 Product Term(s)

    Output _OR_419

        3 Input(s)
            _PIN_NCSCTRL, _PIN_NCSDATA, _PIN_NRD
        2 Fanout(s)
            glb4_part1.I4, glb0.I11
        2 Product Term(s)
        1 GLB Level(s)

        _OR_419 = (!_PIN_NCSCTRL & !_PIN_NRD
            # !_PIN_NCSDATA & !_PIN_NRD)

    Output TEASYNC3

        1 Input(s)
            TEASYNC2
        1 Fanout(s)
            glb2.I10
        1 Product Term(s)
        1 GLB Level(s)

        TEASYNC3.D = TEASYNC2
        TEASYNC3.C = _PIN_BCLK


GLB glb14_part1, C7

    5 Input(s)
        (AD7.O, AD7_PIN, I15), (glb14_part1.O0, BUFF, I16), 
        (glb10_part1.O3, WRTMP_AR, I12), (AD2.O, AD2_PIN, I1), 
        (glb14_part1.O1, BUFA, I2)
    2 Output(s)
        (BUFF, O0), (BUFA, O1)
    4 Product Term(s)

    Output BUFF

        3 Input(s)
            AD7_PIN, BUFF, WRTMP_AR
        2 Fanout(s)
            glb6.I3, glb14_part1.I16
        2 Product Term(s)
        2 GLB Level(s)

        BUFF.D = (AD7_PIN & WRTMP_AR
            # BUFF & !WRTMP_AR)
        BUFF.C = _PIN_CLK

    Output BUFA

        3 Input(s)
            AD2_PIN, BUFA, WRTMP_AR
        2 Fanout(s)
            glb8_part2.I13, glb14_part1.I2
        2 Product Term(s)
        2 GLB Level(s)

        BUFA.D = (AD2_PIN & WRTMP_AR
            # BUFA & !WRTMP_AR)
        BUFA.C = _PIN_CLK


GLB glb14_part2, B5

    5 Input(s)
        (AD1.O, AD1_PIN, I2), (glb14_part2.O1, BUF9_part2, I10), 
        (glb10_part1.O3, WRTMP_AR, I12), (AD0.O, AD0_PIN, I3), 
        (glb14_part2.O2, BUF8, I9)
    3 Output(s)
        (BUF9_part2, O1), (BUF8, O2), (BUF9_part1, O3)
    4 Product Term(s)

    Output BUF9_part2

        3 Input(s)
            AD1_PIN, BUF9_part2, WRTMP_AR
        1 Fanout(s)
            glb14_part2.I10
        2 Product Term(s)
        2 GLB Level(s)

        BUF9_part2.D = (AD1_PIN & WRTMP_AR
            # BUF9_part2 & !WRTMP_AR)
        BUF9_part2.C = _PIN_CLK

    Output BUF8

        3 Input(s)
            AD0_PIN, BUF8, WRTMP_AR
        2 Fanout(s)
            glb1.I6, glb14_part2.I9
        2 Product Term(s)
        2 GLB Level(s)

        BUF8.D = (AD0_PIN & WRTMP_AR
            # BUF8 & !WRTMP_AR)
        BUF8.C = _PIN_CLK

    Output BUF9_part1

        3 Input(s)
            AD1_PIN, BUF9_part2, WRTMP_AR
        1 Fanout(s)
            glb1.I7
        2 Product Term(s)
        2 GLB Level(s)

        BUF9_part1.D = (AD1_PIN & WRTMP_AR
            # BUF9_part2 & !WRTMP_AR)
        BUF9_part1.C = _PIN_CLK


GLB glb15, C0

    9 Input(s)
        (AD3.O, AD3_PIN, I0), (AD4.O, AD4_PIN, I9), (AD5.O, 
        AD5_PIN, I8), (AD6.O, AD6_PIN, I14), (glb15.O3, BUFB, I17), 
        (glb15.O2, BUFC, I13), (glb15.O1, BUFD, I16), (glb15.O0, 
        BUFE, I15), (glb10_part1.O3, WRTMP_AR, I12)
    4 Output(s)
        (BUFE, O0), (BUFD, O1), (BUFC, O2), (BUFB, O3)
    8 Product Term(s)

    Output BUFE

        3 Input(s)
            AD6_PIN, BUFE, WRTMP_AR
        2 Fanout(s)
            glb7.I0, glb15.I15
        2 Product Term(s)
        2 GLB Level(s)

        BUFE.D = (AD6_PIN & WRTMP_AR
            # BUFE & !WRTMP_AR)
        BUFE.C = _PIN_CLK

    Output BUFD

        3 Input(s)
            AD5_PIN, BUFD, WRTMP_AR
        2 Fanout(s)
            glb8_part1.I1, glb15.I16
        2 Product Term(s)
        2 GLB Level(s)

        BUFD.D = (AD5_PIN & WRTMP_AR
            # BUFD & !WRTMP_AR)
        BUFD.C = _PIN_CLK

    Output BUFC

        3 Input(s)
            AD4_PIN, BUFC, WRTMP_AR
        2 Fanout(s)
            glb9_part2.I2, glb15.I13
        2 Product Term(s)
        2 GLB Level(s)

        BUFC.D = (AD4_PIN & WRTMP_AR
            # BUFC & !WRTMP_AR)
        BUFC.C = _PIN_CLK

    Output BUFB

        3 Input(s)
            AD3_PIN, BUFB, WRTMP_AR
        2 Fanout(s)
            glb8_part2.I3, glb15.I17
        2 Product Term(s)
        2 GLB Level(s)

        BUFB.D = (AD3_PIN & WRTMP_AR
            # BUFB & !WRTMP_AR)
        BUFB.C = _PIN_CLK


GLB glb16_part1, B2

    7 Input(s)
        (AD7.O, AD7_PIN, I0), (glb16_part1.O3, BUF7, I11), 
        (glb10_part1.O2, BUF7_CE, I2), (AD2.O, AD2_PIN, I14), 
        (glb16_part1.O1, BUF2, I9), (AD1.O, AD1_PIN, I13), 
        (glb16_part1.O0, BUF1_part2, I8)
    4 Output(s)
        (BUF7, O3), (BUF2, O1), (BUF1_part2, O0), (BUF1_part1, O2)
    6 Product Term(s)

    Output BUF7

        3 Input(s)
            AD7_PIN, BUF7, BUF7_CE
        2 Fanout(s)
            glb16_part1.I11, glb1.I11
        2 Product Term(s)
        2 GLB Level(s)

        BUF7.D = (AD7_PIN & BUF7_CE
            # BUF7 & !BUF7_CE)
        BUF7.C = _PIN_CLK

    Output BUF2

        3 Input(s)
            AD2_PIN, BUF2, BUF7_CE
        2 Fanout(s)
            glb16_part1.I9, glb6.I6
        2 Product Term(s)
        2 GLB Level(s)

        BUF2.D = (AD2_PIN & BUF7_CE
            # BUF2 & !BUF7_CE)
        BUF2.C = _PIN_CLK

    Output BUF1_part2

        3 Input(s)
            AD1_PIN, BUF1_part2, BUF7_CE
        1 Fanout(s)
            glb16_part1.I8
        2 Product Term(s)
        2 GLB Level(s)

        BUF1_part2.D = (AD1_PIN & BUF7_CE
            # BUF1_part2 & !BUF7_CE)
        BUF1_part2.C = _PIN_CLK

    Output BUF1_part1

        3 Input(s)
            AD1_PIN, BUF1_part2, BUF7_CE
        1 Fanout(s)
            glb6.I5
        2 Product Term(s)
        2 GLB Level(s)

        BUF1_part1.D = (AD1_PIN & BUF7_CE
            # BUF1_part2 & !BUF7_CE)
        BUF1_part1.C = _PIN_CLK


GLB glb16_part2, C2

    3 Input(s)
        (AD0.O, AD0_PIN, I3), (glb16_part2.O3, BUF0, I4), 
        (glb10_part1.O2, BUF7_CE, I13)
    1 Output(s)
        (BUF0, O3)
    2 Product Term(s)

    Output BUF0

        3 Input(s)
            AD0_PIN, BUF0, BUF7_CE
        2 Fanout(s)
            glb16_part2.I4, glb6.I4
        2 Product Term(s)
        2 GLB Level(s)

        BUF0.D = (AD0_PIN & BUF7_CE
            # BUF0 & !BUF7_CE)
        BUF0.C = _PIN_CLK


GLB glb17, A3

    9 Input(s)
        (AD3.O, AD3_PIN, I15), (AD4.O, AD4_PIN, I6), (AD5.O, 
        AD5_PIN, I7), (AD6.O, AD6_PIN, I1), (glb17.O1, BUF3, I13), 
        (glb17.O0, BUF4, I12), (glb17.O2, BUF5, I14), (glb17.O3, 
        BUF6, I17), (glb10_part1.O2, BUF7_CE, I2)
    4 Output(s)
        (BUF6, O3), (BUF5, O2), (BUF4, O0), (BUF3, O1)
    8 Product Term(s)

    Output BUF6

        3 Input(s)
            AD6_PIN, BUF6, BUF7_CE
        2 Fanout(s)
            glb4_part2.I15, glb17.I17
        2 Product Term(s)
        2 GLB Level(s)

        BUF6.D = (AD6_PIN & BUF7_CE
            # BUF6 & !BUF7_CE)
        BUF6.C = _PIN_CLK

    Output BUF5

        3 Input(s)
            AD5_PIN, BUF5, BUF7_CE
        2 Fanout(s)
            glb17.I14, glb4_part1.I14
        2 Product Term(s)
        2 GLB Level(s)

        BUF5.D = (AD5_PIN & BUF7_CE
            # BUF5 & !BUF7_CE)
        BUF5.C = _PIN_CLK

    Output BUF4

        3 Input(s)
            AD4_PIN, BUF4, BUF7_CE
        2 Fanout(s)
            glb7.I12, glb17.I12
        2 Product Term(s)
        2 GLB Level(s)

        BUF4.D = (AD4_PIN & BUF7_CE
            # BUF4 & !BUF7_CE)
        BUF4.C = _PIN_CLK

    Output BUF3

        3 Input(s)
            AD3_PIN, BUF3, BUF7_CE
        2 Fanout(s)
            glb7.I13, glb17.I13
        2 Product Term(s)
        2 GLB Level(s)

        BUF3.D = (AD3_PIN & BUF7_CE
            # BUF3 & !BUF7_CE)
        BUF3.C = _PIN_CLK


GLB glb2, C1

    8 Input(s)
        (glb5.O2, BKPT, I1), (glb3.O2, SQ0_CE, I5), (glb6.O3, 
        SQF, I8), (glb2.O1, SQS, I16), (glb12.O0, TEASYNC1, I3), 
        (glb13.O1, TEASYNC3, I10), (TOV.O, _PIN_TOV, I13), (glb3.O0, 
        _OR_407, I7)
    4 Output(s)
        (_VCC_1012, O3), (TEASYNC2, O0), (SQS, O1), (BKPTSYNC_PIN, O2)
    1 Enable Output
        NTEA_OE
    5 Product Term(s)

    Output _VCC_1012

        0 Input(s)
        1 Fanout(s)
            ECLK.IR
        0 Product Term(s)
        0 GLB Level(s)

        _VCC_1012 = VCC

    Output TEASYNC2

        1 Input(s)
            TEASYNC1
        2 Fanout(s)
            glb13.I4, NTEA.IR
        1 Product Term(s)
        1 GLB Level(s)

        TEASYNC2.D = TEASYNC1
        TEASYNC2.C = _PIN_BCLK

    Output SQS

        4 Input(s)
            SQ0_CE, SQF, SQS, _OR_407
        3 Fanout(s)
            glb4_part2.I5, glb2.I16, DSI.IR
        2 Product Term(s)
        3 GLB Level(s)

        SQS.D = (SQS & !SQ0_CE
            # SQF & !_OR_407)
        SQS.C = _PIN_BCLK

    Output BKPTSYNC_PIN

        2 Input(s)
            BKPT, _PIN_TOV
        1 Fanout(s)
            BKPTSYNC.IR
        1 Product Term(s)
        1 GLB Level(s)

        BKPTSYNC_PIN.D = BKPT & !_PIN_TOV
        BKPTSYNC_PIN.C = _PIN_BCLK

    Enable Output NTEA_OE

        2 Input(s)
            TEASYNC1, TEASYNC3
        1 Fanout(s)
            NTEA.OE0
        1 Product Term(s)
        1 GLB Level(s)

        NTEA_OE = TEASYNC1 & !TEASYNC3


GLB glb3, C6

    7 Input(s)
        (glb12.O3, B0, I0), (glb9_part1.O0, B1_part2, I15), (glb12.O2, 
        B2, I1), (glb9_part2.O0, B3, I11), (glb9_part2.O1, 
        B4_part2, I10), (glb3.O2, SQ0_CE, I5), (glb3.O1, SQCLK, I6)
    4 Output(s)
        (_OR_407, O0), (SQCLK, O1), (SQ0_CE, O2), (DSCLK_PIN, O3)
    11 Product Term(s)

    Output _OR_407

        6 Input(s)
            B0, B1_part2, B2, B3, B4_part2, SQ0_CE
        7 Fanout(s)
            glb7.I8, glb8_part1.I8, glb8_part2.I8, glb9_part2.I8,
            glb1.I8, glb2.I7, glb6.I7
        3 Product Term(s)
        2 GLB Level(s)

        _OR_407 = (!SQ0_CE
            # B0 & B1_part2 & B4_part2 & !B2 & !B3
            # !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)

    Output SQCLK

        7 Input(s)
            B0, B1_part2, B2, B3, B4_part2, SQ0_CE, SQCLK
        1 Fanout(s)
            glb3.I6
        3 Product Term(s)
        2 GLB Level(s)

        SQCLK.D = (!SQ0_CE
            # !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)
            $ !B2 & !B3 & !B0 & !B1_part2 & !B4_part2 & !SQCLK
        SQCLK.C = _PIN_BCLK

    Output SQ0_CE

        6 Input(s)
            B0, B1_part2, B2, B3, B4_part2, SQCLK
        9 Fanout(s)
            glb7.I10, glb8_part1.I10, glb8_part2.I10, glb9_part2.I10,
            glb1.I10, glb12.I5, glb2.I5, glb9_part1.I5, glb3.I5
        2 Product Term(s)
        1 GLB Level(s)

        SQ0_CE = (SQCLK
            # B0 & B1_part2 & B4_part2 & !B2 & !B3)

    Output DSCLK_PIN

        6 Input(s)
            B0, B1_part2, B2, B3, B4_part2, SQCLK
        1 Fanout(s)
            DSCLK.IR
        4 Product Term(s)
        1 GLB Level(s)

        DSCLK_PIN.D = (SQCLK
            # !B2 & !B3 & !B1_part2 & !B4_part2
            # B0 & B1_part2 & B4_part2 & !B2 & !B3)
            $ VCC
        DSCLK_PIN.C = _PIN_BCLK


GLB glb4_part1, A6

    11 Input(s)
        (NCSCTRL.O, _PIN_NCSCTRL, I9), (glb7.O3, SQ3, I3), 
        (glb8_part2.O0, SQB_part2, I0), (VCC_B5.O, _PIN_VCC_B5, I10), 
        (glb10_part2.O1, _AND_385, I13), (glb10_part1.O1, 
        _AND_386_part1, I1), (glb6.O1, SQ2, I5), (glb8_part2.O2, 
        SQA, I2), (glb11.O3, _BUF_841, I11), (glb13.O0, _OR_419, I4), 
        (glb17.O2, BUF5, I14)
    3 Output(s)
        (AD3_D, O3), (AD2_D, O2), (BUF5_buff1, O1)
    1 Enable Output
        _BUF_842
    8 Product Term(s)

    Output AD3_D

        6 Input(s)
            _PIN_NCSCTRL, SQ3, SQB_part2, _PIN_VCC_B5, _AND_385,
            _AND_386_part1
        1 Fanout(s)
            AD3.IR
        3 Product Term(s)
        2 GLB Level(s)

        AD3_D = (SQ3 & _AND_386_part1
            # _PIN_VCC_B5 & !_PIN_NCSCTRL
            # SQB_part2 & _AND_385)

    Output AD2_D

        6 Input(s)
            _PIN_NCSCTRL, SQ2, SQA, _AND_385, _AND_386_part1, _BUF_841
        1 Fanout(s)
            AD2.IR
        3 Product Term(s)
        2 GLB Level(s)

        AD2_D = (SQA & _AND_385
            # SQ2 & _AND_386_part1
            # !_PIN_NCSCTRL & _BUF_841)

    Output BUF5_buff1

        1 Input(s)
            BUF5
        1 Fanout(s)
            glb7.I9
        1 Product Term(s)
        1 GLB Level(s)

        BUF5_buff1 = BUF5

    Enable Output _BUF_842

        1 Input(s)
            _OR_419
        4 Fanout(s)
            AD3.OE1, AD2.OE1, AD1.OE1, AD0.OE1
        1 Product Term(s)
        2 GLB Level(s)

        _BUF_842 = _OR_419


GLB glb4_part2, A1

    10 Input(s)
        (glb11.O0, BDM_BZY, I8), (NCSCTRL.O, _PIN_NCSCTRL, I9), 
        (glb6.O2, SQ1, I6), (glb1.O0, SQ9, I12), (glb10_part2.O1, 
        _AND_385, I13), (glb10_part1.O0, _AND_386_part2, I0), (glb6.O0, 
        SQ0, I4), (glb1.O2, SQ8, I14), (glb2.O1, SQS, I5), (glb17.O3, 
        BUF6, I15)
    3 Output(s)
        (AD1_D, O1), (AD0_D, O0), (BUF6_buff1, O3)
    7 Product Term(s)

    Output AD1_D

        6 Input(s)
            BDM_BZY, _PIN_NCSCTRL, SQ1, SQ9, _AND_385, _AND_386_part2
        1 Fanout(s)
            AD1.IR
        3 Product Term(s)
        2 GLB Level(s)

        AD1_D = (SQ9 & _AND_385
            # SQ1 & _AND_386_part2
            # !_PIN_NCSCTRL & !BDM_BZY)

    Output AD0_D

        6 Input(s)
            _PIN_NCSCTRL, SQ0, SQ8, SQS, _AND_385, _AND_386_part2
        1 Fanout(s)
            AD0.IR
        3 Product Term(s)
        2 GLB Level(s)

        AD0_D = (SQ8 & _AND_385
            # SQ0 & _AND_386_part2
            # SQS & !_PIN_NCSCTRL)

    Output BUF6_buff1

        1 Input(s)
            BUF6
        1 Fanout(s)
            glb8_part1.I7
        1 Product Term(s)
        1 GLB Level(s)

        BUF6_buff1 = BUF6


GLB glb5, A7

    4 Input(s)
        (AD0.O, AD0_PIN, I12), (glb5.O2, BKPT, I14), (NCSCTRL.O, 
        _PIN_NCSCTRL, I9), (NWR.O, _PIN_NWR, I7)
    1 Output(s)
        (BKPT, O2)
    3 Product Term(s)

    Output BKPT

        4 Input(s)
            AD0_PIN, BKPT, _PIN_NCSCTRL, _PIN_NWR
        2 Fanout(s)
            glb5.I14, glb2.I1
        3 Product Term(s)
        1 GLB Level(s)

        BKPT.D = (BKPT & _PIN_NCSCTRL
            # BKPT & _PIN_NWR
            # AD0_PIN & !_PIN_NCSCTRL & !_PIN_NWR)
        BKPT.C = _PIN_CLK


GLB glb6, C5

    17 Input(s)
        (glb12.O3, B0, I0), (glb9_part1.O3, B1_part1, I12), (glb12.O2, 
        B2, I1), (glb9_part2.O0, B3, I11), (glb9_part2.O1, 
        B4_part2, I10), (glb16_part2.O3, BUF0, I4), (glb16_part1.O2, 
        BUF1_part1, I5), (glb16_part1.O1, BUF2, I6), (glb14_part1.O0, 
        BUFF, I3), (glb6.O0, SQ0, I16), (glb9_part1.O1, 
        SQ0_CE_buff1, I14), (glb6.O2, SQ1, I9), (glb6.O1, SQ2, I17), 
        (glb7.O0, SQE, I15), (glb6.O3, SQF, I8), (glb12.O1, 
        SQTMP, I2), (glb3.O0, _OR_407, I7)
    4 Output(s)
        (SQF, O3), (SQ2, O1), (SQ1, O2), (SQ0, O0)
    16 Product Term(s)

    Output SQF

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part2, BUFF, SQ0_CE_buff1, SQE, SQF,
            _OR_407
        3 Fanout(s)
            glb0.I8, glb2.I8, glb6.I8
        4 Product Term(s)
        3 GLB Level(s)

        SQF.D = (SQF & !SQ0_CE_buff1
            # SQE & !_OR_407
            # B0 & B1_part1 & B4_part2 & BUFF & SQ0_CE_buff1 & !B2 & !B3
            # BUFF & SQ0_CE_buff1 & !B2 & !B3 & !B0 & !B1_part1
            & !B4_part2)
        SQF.C = _PIN_BCLK

    Output SQ2

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part2, BUF2, SQ0_CE_buff1, SQ1, SQ2,
            _OR_407
        3 Fanout(s)
            glb7.I5, glb4_part1.I5, glb6.I17
        4 Product Term(s)
        3 GLB Level(s)

        SQ2.D = (SQ2 & !SQ0_CE_buff1
            # SQ1 & !_OR_407
            # B0 & B1_part1 & B4_part2 & BUF2 & SQ0_CE_buff1 & !B2 & !B3
            # BUF2 & SQ0_CE_buff1 & !B2 & !B3 & !B0 & !B1_part1
            & !B4_part2)
        SQ2.C = _PIN_BCLK

    Output SQ1

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part2, BUF1_part1, SQ0,
            SQ0_CE_buff1, SQ1, _OR_407
        2 Fanout(s)
            glb4_part2.I6, glb6.I9
        4 Product Term(s)
        3 GLB Level(s)

        SQ1.D = (SQ1 & !SQ0_CE_buff1
            # SQ0 & !_OR_407
            # B0 & B1_part1 & B4_part2 & BUF1_part1 & SQ0_CE_buff1 & !B2
            & !B3
            # BUF1_part1 & SQ0_CE_buff1 & !B2 & !B3 & !B0 & !B1_part1
            & !B4_part2)
        SQ1.C = _PIN_BCLK

    Output SQ0

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part2, BUF0, SQ0, SQ0_CE_buff1,
            SQTMP, _OR_407
        2 Fanout(s)
            glb4_part2.I4, glb6.I16
        4 Product Term(s)
        3 GLB Level(s)

        SQ0.D = (SQ0 & !SQ0_CE_buff1
            # SQTMP & !_OR_407
            # B0 & B1_part1 & B4_part2 & BUF0 & SQ0_CE_buff1 & !B2 & !B3
            # BUF0 & SQ0_CE_buff1 & !B2 & !B3 & !B0 & !B1_part1
            & !B4_part2)
        SQ0.C = _PIN_BCLK


GLB glb7, A0

    17 Input(s)
        (glb12.O3, B0, I15), (glb9_part1.O3, B1_part1, I3), (glb12.O2, 
        B2, I14), (glb9_part2.O0, B3, I4), (glb9_part2.O3, 
        B4_part1, I7), (glb17.O1, BUF3, I13), (glb17.O0, BUF4, I12), 
        (glb4_part1.O1, BUF5_buff1, I9), (glb15.O0, BUFE, I0), 
        (glb3.O2, SQ0_CE, I10), (glb6.O1, SQ2, I5), (glb7.O3, 
        SQ3, I17), (glb7.O1, SQ4, I1), (glb7.O2, SQ5, I2), 
        (glb8_part1.O3, SQD_part1, I11), (glb7.O0, SQE, I16), (glb3.O0, 
        _OR_407, I8)
    4 Output(s)
        (SQE, O0), (SQ5, O2), (SQ4, O1), (SQ3, O3)
    16 Product Term(s)

    Output SQE

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part1, BUFE, SQ0_CE, SQD_part1, SQE,
            _OR_407
        3 Fanout(s)
            glb7.I16, glb1.I0, glb6.I15
        4 Product Term(s)
        3 GLB Level(s)

        SQE.D = (SQE & !SQ0_CE
            # SQD_part1 & !_OR_407
            # B0 & B1_part1 & B4_part1 & BUFE & SQ0_CE & !B2 & !B3
            # BUFE & SQ0_CE & !B2 & !B3 & !B0 & !B1_part1 & !B4_part1)
        SQE.C = _PIN_BCLK

    Output SQ5

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part1, BUF5_buff1, SQ0_CE, SQ4, SQ5,
            _OR_407
        3 Fanout(s)
            glb7.I2, glb8_part1.I2, glb0.I13
        4 Product Term(s)
        3 GLB Level(s)

        SQ5.D = (SQ5 & !SQ0_CE
            # SQ4 & !_OR_407
            # B0 & B1_part1 & B4_part1 & BUF5_buff1 & SQ0_CE & !B2 & !B3
            # BUF5_buff1 & SQ0_CE & !B2 & !B3 & !B0 & !B1_part1
            & !B4_part1)
        SQ5.C = _PIN_BCLK

    Output SQ4

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part1, BUF4, SQ0_CE, SQ3, SQ4,
            _OR_407
        2 Fanout(s)
            glb7.I1, glb0.I14
        4 Product Term(s)
        3 GLB Level(s)

        SQ4.D = (SQ4 & !SQ0_CE
            # SQ3 & !_OR_407
            # B0 & B1_part1 & B4_part1 & BUF4 & SQ0_CE & !B2 & !B3
            # BUF4 & SQ0_CE & !B2 & !B3 & !B0 & !B1_part1 & !B4_part1)
        SQ4.C = _PIN_BCLK

    Output SQ3

        10 Input(s)
            B0, B1_part1, B2, B3, B4_part1, BUF3, SQ0_CE, SQ2, SQ3,
            _OR_407
        2 Fanout(s)
            glb7.I17, glb4_part1.I3
        4 Product Term(s)
        3 GLB Level(s)

        SQ3.D = (SQ3 & !SQ0_CE
            # SQ2 & !_OR_407
            # B0 & B1_part1 & B4_part1 & BUF3 & SQ0_CE & !B2 & !B3
            # BUF3 & SQ0_CE & !B2 & !B3 & !B0 & !B1_part1 & !B4_part1)
        SQ3.C = _PIN_BCLK


GLB glb8_part1, A2

    13 Input(s)
        (glb12.O3, B0, I15), (glb9_part1.O0, B1_part2, I0), (glb12.O2, 
        B2, I14), (glb9_part2.O0, B3, I4), (glb9_part2.O1, 
        B4_part2, I5), (glb15.O1, BUFD, I1), (glb3.O2, SQ0_CE, I10), 
        (glb9_part2.O2, SQC, I6), (glb8_part1.O0, SQD_part2, I16), 
        (glb3.O0, _OR_407, I8), (glb4_part2.O3, BUF6_buff1, I7), 
        (glb7.O2, SQ5, I2), (glb8_part1.O1, SQ6, I17)
    3 Output(s)
        (SQD_part2, O0), (SQ6, O1), (SQD_part1, O3)
    8 Product Term(s)

    Output SQD_part2

        10 Input(s)
            B0, B1_part2, B2, B3, B4_part2, BUFD, SQ0_CE, SQC, SQD_part2,
            _OR_407
        2 Fanout(s)
            glb8_part1.I16, glb0.I7
        4 Product Term(s)
        3 GLB Level(s)

        SQD_part2.D = (SQD_part2 & !SQ0_CE
            # SQC & !_OR_407
            # B0 & B1_part2 & B4_part2 & BUFD & SQ0_CE & !B2 & !B3
            # BUFD & SQ0_CE & !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)
        SQD_part2.C = _PIN_BCLK

    Output SQ6

        10 Input(s)
            B0, B1_part2, B2, B3, B4_part2, BUF6_buff1, SQ0_CE, SQ5, SQ6,
            _OR_407
        2 Fanout(s)
            glb8_part1.I17, glb1.I9
        4 Product Term(s)
        3 GLB Level(s)

        SQ6.D = (SQ6 & !SQ0_CE
            # SQ5 & !_OR_407
            # B0 & B1_part2 & B4_part2 & BUF6_buff1 & SQ0_CE & !B2 & !B3
            # BUF6_buff1 & SQ0_CE & !B2 & !B3 & !B0 & !B1_part2
            & !B4_part2)
        SQ6.C = _PIN_BCLK

    Output SQD_part1

        10 Input(s)
            B0, B1_part2, B2, B3, B4_part2, BUFD, SQ0_CE, SQC, SQD_part2,
            _OR_407
        1 Fanout(s)
            glb7.I11
        4 Product Term(s)
        3 GLB Level(s)

        SQD_part1.D = (SQD_part2 & !SQ0_CE
            # SQC & !_OR_407
            # B0 & B1_part2 & B4_part2 & BUFD & SQ0_CE & !B2 & !B3
            # BUFD & SQ0_CE & !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)
        SQD_part1.C = _PIN_BCLK


GLB glb8_part2, A4

    12 Input(s)
        (glb12.O3, B0, I15), (glb9_part1.O0, B1_part2, I0), (glb12.O2, 
        B2, I14), (glb9_part2.O0, B3, I4), (glb9_part2.O1, 
        B4_part2, I5), (glb15.O3, BUFB, I3), (glb3.O2, SQ0_CE, I10), 
        (glb8_part2.O2, SQA, I2), (glb8_part2.O0, SQB_part2, I16), 
        (glb3.O0, _OR_407, I8), (glb14_part1.O1, BUFA, I13), (glb1.O0, 
        SQ9, I12)
    3 Output(s)
        (SQB_part2, O0), (SQA, O2), (SQB_part1, O3)
    8 Product Term(s)

    Output SQB_part2

        10 Input(s)
            B0, B1_part2, B2, B3, B4_part2, BUFB, SQ0_CE, SQA, SQB_part2,
            _OR_407
        2 Fanout(s)
            glb8_part2.I16, glb4_part1.I0
        4 Product Term(s)
        3 GLB Level(s)

        SQB_part2.D = (SQB_part2 & !SQ0_CE
            # SQA & !_OR_407
            # B0 & B1_part2 & B4_part2 & BUFB & SQ0_CE & !B2 & !B3
            # BUFB & SQ0_CE & !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)
        SQB_part2.C = _PIN_BCLK

    Output SQA

        10 Input(s)
            B0, B1_part2, B2, B3, B4_part2, BUFA, SQ0_CE, SQ9, SQA,
            _OR_407
        2 Fanout(s)
            glb8_part2.I2, glb4_part1.I2
        4 Product Term(s)
        3 GLB Level(s)

        SQA.D = (SQA & !SQ0_CE
            # SQ9 & !_OR_407
            # B0 & B1_part2 & B4_part2 & BUFA & SQ0_CE & !B2 & !B3
            # BUFA & SQ0_CE & !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)
        SQA.C = _PIN_BCLK

    Output SQB_part1

        10 Input(s)
            B0, B1_part2, B2, B3, B4_part2, BUFB, SQ0_CE, SQA, SQB_part2,
            _OR_407
        1 Fanout(s)
            glb9_part2.I3
        4 Product Term(s)
        3 GLB Level(s)

        SQB_part1.D = (SQB_part2 & !SQ0_CE
            # SQA & !_OR_407
            # B0 & B1_part2 & B4_part2 & BUFB & SQ0_CE & !B2 & !B3
            # BUFB & SQ0_CE & !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)
        SQB_part1.C = _PIN_BCLK


GLB glb9_part1, C4

    4 Input(s)
        (glb12.O3, B0, I0), (glb9_part1.O0, B1_part2, I15), (glb3.O2, 
        SQ0_CE, I5), (glb0.O1, WRDELAY, I14)
    3 Output(s)
        (B1_part2, O0), (SQ0_CE_buff1, O1), (B1_part1, O3)
    4 Product Term(s)

    Output B1_part2

        4 Input(s)
            B0, B1_part2, SQ0_CE, WRDELAY
        7 Fanout(s)
            glb8_part1.I0, glb8_part2.I0, glb9_part2.I0, glb11.I15,
            glb12.I15, glb9_part1.I15, glb3.I15
        4 Product Term(s)
        2 GLB Level(s)

        B1_part2.D = (B0 & WRDELAY & !B1_part2
            # WRDELAY & !SQ0_CE & !B1_part2
            # B1_part2 & SQ0_CE & WRDELAY & !B0)
            $ VCC
        B1_part2.C = _PIN_BCLK

    Output SQ0_CE_buff1

        1 Input(s)
            SQ0_CE
        1 Fanout(s)
            glb6.I14
        1 Product Term(s)
        2 GLB Level(s)

        SQ0_CE_buff1 = SQ0_CE

    Output B1_part1

        4 Input(s)
            B0, B1_part2, SQ0_CE, WRDELAY
        3 Fanout(s)
            glb7.I3, glb1.I3, glb6.I12
        4 Product Term(s)
        2 GLB Level(s)

        B1_part1.D = (B0 & WRDELAY & !B1_part2
            # WRDELAY & !SQ0_CE & !B1_part2
            # B1_part2 & SQ0_CE & WRDELAY & !B0)
            $ VCC
        B1_part1.C = _PIN_BCLK


GLB glb9_part2, A5

    11 Input(s)
        (glb12.O3, B0, I15), (glb9_part1.O0, B1_part2, I0), (glb12.O2, 
        B2, I14), (glb9_part2.O0, B3, I4), (glb9_part2.O1, 
        B4_part2, I5), (glb15.O2, BUFC, I2), (glb3.O2, SQ0_CE, I10), 
        (glb8_part2.O3, SQB_part1, I3), (glb9_part2.O2, SQC, I6), 
        (glb3.O0, _OR_407, I8), (glb0.O1, WRDELAY, I1)
    4 Output(s)
        (SQC, O2), (B4_part2, O1), (B3, O0), (B4_part1, O3)
    12 Product Term(s)

    Output SQC

        10 Input(s)
            B0, B1_part2, B2, B3, B4_part2, BUFC, SQ0_CE, SQB_part1, SQC,
            _OR_407
        3 Fanout(s)
            glb8_part1.I6, glb9_part2.I6, glb0.I9
        4 Product Term(s)
        3 GLB Level(s)

        SQC.D = (SQC & !SQ0_CE
            # SQB_part1 & !_OR_407
            # B0 & B1_part2 & B4_part2 & BUFC & SQ0_CE & !B2 & !B3
            # BUFC & SQ0_CE & !B2 & !B3 & !B0 & !B1_part2 & !B4_part2)
        SQC.C = _PIN_BCLK

    Output B4_part2

        7 Input(s)
            B0, B1_part2, B2, B3, B4_part2, SQ0_CE, WRDELAY
        7 Fanout(s)
            glb8_part1.I5, glb8_part2.I5, glb9_part2.I5, glb1.I5,
            glb11.I10, glb6.I10, glb3.I10
        7 Product Term(s)
        2 GLB Level(s)

        B4_part2.D = (B0 & WRDELAY & !B4_part2
            # B1_part2 & WRDELAY & !B4_part2
            # B2 & WRDELAY & !B4_part2
            # B3 & WRDELAY & !B4_part2
            # WRDELAY & !SQ0_CE & !B4_part2
            # B4_part2 & SQ0_CE & WRDELAY & !B2 & !B3 & !B0 & !B1_part2
            )
            $ VCC
        B4_part2.C = _PIN_BCLK

    Output B3

        6 Input(s)
            B0, B1_part2, B2, B3, SQ0_CE, WRDELAY
        8 Fanout(s)
            glb7.I4, glb8_part1.I4, glb8_part2.I4, glb9_part2.I4,
            glb1.I4, glb11.I11, glb6.I11, glb3.I11
        2 Product Term(s)
        2 GLB Level(s)

        B3.D = (SQ0_CE & WRDELAY & !B2 & !B0 & !B1_part2)
            $ B3 & WRDELAY
        B3.C = _PIN_BCLK

    Output B4_part1

        7 Input(s)
            B0, B1_part2, B2, B3, B4_part2, SQ0_CE, WRDELAY
        1 Fanout(s)
            glb7.I7
        7 Product Term(s)
        2 GLB Level(s)

        B4_part1.D = (B0 & WRDELAY & !B4_part2
            # B1_part2 & WRDELAY & !B4_part2
            # B2 & WRDELAY & !B4_part2
            # B3 & WRDELAY & !B4_part2
            # WRDELAY & !SQ0_CE & !B4_part2
            # B4_part2 & SQ0_CE & WRDELAY & !B2 & !B3 & !B0 & !B1_part2
            )
            $ VCC
        B4_part1.C = _PIN_BCLK


Input A0, IO30

    Output _PIN_A0
        2 Fanout(s)
            glb10_part1.I14, glb10_part2.I1


Bidirectional AD0, IO12

    Input (glb4_part2.O0, AD0_D)
    Output AD0_PIN
        3 Fanout(s)
            glb5.I12, glb14_part2.I3, glb16_part2.I3
    Enable (glb4_part1.OE, _BUF_842)

    AD0 = AD0_D
    AD0.E = _BUF_842


Bidirectional AD1, IO13

    Input (glb4_part2.O1, AD1_D)
    Output AD1_PIN
        2 Fanout(s)
            glb16_part1.I13, glb14_part2.I2
    Enable (glb4_part1.OE, _BUF_842)

    AD1 = AD1_D
    AD1.E = _BUF_842


Bidirectional AD2, IO14

    Input (glb4_part1.O2, AD2_D)
    Output AD2_PIN
        2 Fanout(s)
            glb16_part1.I14, glb14_part1.I1
    Enable (glb4_part1.OE, _BUF_842)

    AD2 = AD2_D
    AD2.E = _BUF_842


Bidirectional AD3, IO15

    Input (glb4_part1.O3, AD3_D)
    Output AD3_PIN
        2 Fanout(s)
            glb17.I15, glb15.I0
    Enable (glb4_part1.OE, _BUF_842)

    AD3 = AD3_D
    AD3.E = _BUF_842


Bidirectional AD4, IO22

    Input (glb0.O2, AD4_D)
    Output AD4_PIN
        2 Fanout(s)
            glb17.I6, glb15.I9
    Enable (glb0.OE, _BUF_843)

    AD4 = AD4_D
    AD4.E = _BUF_843


Bidirectional AD5, IO23

    Input (glb0.O3, AD5_D)
    Output AD5_PIN
        2 Fanout(s)
            glb17.I7, glb15.I8
    Enable (glb0.OE, _BUF_843)

    AD5 = AD5_D
    AD5.E = _BUF_843


Bidirectional AD6, IO17

    Input (glb1.O1, AD6_D)
    Output AD6_PIN
        2 Fanout(s)
            glb17.I1, glb15.I14
    Enable (glb0.OE, _BUF_843)

    AD6 = AD6_D
    AD6.E = _BUF_843


Bidirectional AD7, IO16

    Input (glb0.O0, AD7_D)
    Output AD7_PIN
        2 Fanout(s)
            glb16_part1.I0, glb14_part1.I15
    Enable (glb0.OE, _BUF_843)

    AD7 = AD7_D
    AD7.E = _BUF_843


Clock Input BCLK, Y1

    Output _PIN_BCLK
        13 Fanout(s)
            glb7.CLK1, glb8_part1.CLK1, glb8_part2.CLK1, glb9_part2.CLK1,
            glb13.CLK1, glb1.CLK1, glb0.CLK1, glb11.CLK1, glb12.CLK1,
            glb2.CLK1, glb9_part1.CLK1, glb6.CLK1, glb3.CLK1


Output BKPTSYNC, IO38

    Input (glb2.O2, BKPTSYNC_PIN)

    BKPTSYNC = BKPTSYNC_PIN


Clock Input CLK, Y0

    Output _PIN_CLK
        7 Fanout(s)
            glb17.CLK0, glb5.CLK0, glb16_part1.CLK0, glb14_part2.CLK0,
            glb15.CLK0, glb16_part2.CLK0, glb14_part1.CLK0


Input C_TEA, IO46

    Output _PIN_C_TEA
        1 Fanout(s)
            glb12.I1


Output DSCLK, IO39

    Input (glb3.O3, DSCLK_PIN)

    DSCLK = DSCLK_PIN


Output DSI, IO37

    Input (glb2.O1, SQS)

    DSI = SQS


Input DSO, IO8

    Output _PIN_DSO
        1 Fanout(s)
            glb12.I7


Output ECLK, IO47

    Input (glb2.O3, _VCC_1012)

    ECLK = _VCC_1012


Input NCSCTRL, IO41

    Output _PIN_NCSCTRL
        7 Fanout(s)
            glb4_part2.I9, glb4_part1.I9, glb5.I9, glb10_part1.I9,
            glb13.I9, glb0.I6, glb10_part2.I6


Input NCSDATA, IO40

    Output _PIN_NCSDATA
        2 Fanout(s)
            glb10_part1.I8, glb13.I8


Input NRD, IO0

    Output _PIN_NRD
        1 Fanout(s)
            glb13.I0


Three-State Output NTEA, IO36

    Input (glb2.O0, TEASYNC2)
    Enable (glb2.OE, NTEA_OE)

    NTEA = TEASYNC2
    NTEA.E = NTEA_OE


Input NWR, IO7

    Output _PIN_NWR
        2 Fanout(s)
            glb5.I7, glb10_part1.I7


Input RUN, IO9

    Output _PIN_RUN
        1 Fanout(s)
            glb11.I6


Input TOV, IO34

    Output _PIN_TOV
        1 Fanout(s)
            glb2.I13


Input VCC_B3, IO11

    Output _PIN_VCC_B3
        1 Fanout(s)
            glb0.I4


Input VCC_B5, IO10

    Output _PIN_VCC_B5
        1 Fanout(s)
            glb4_part1.I10


Output WRTEST, IO29

    Input (glb0.O1, WRDELAY)

    WRTEST = WRDELAY


Clock Assignments

    Net Name		    Clock Assignment

        _PIN_BCLK               External CLK1
        _PIN_CLK                External CLK0


GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb0, B4                13,  4, 10          
            AD4_D                                        6,  1,  3,  2      
            AD5_D                                        4,  1,  2,  2      
            AD7_D                                        6,  1,  3,  2      
            WRDELAY                                      1,  5,  1,  1      

        glb1, B3                17,  4, 14          
            AD6_D                                        4,  1,  2,  2      
            SQ7                                         10,  2,  4,  3      
            SQ8                                         10,  2,  4,  3      
            SQ9                                         10,  3,  4,  3      

        glb10_part1, B0          4,  4,  4          
            BUF7_CE                                      3,  3,  1,  1      
            WRTMP_AR                                     3,  4,  1,  1      
            _AND_386_part1                               2,  2,  1,  1      
            _AND_386_part2                               2,  2,  1,  1      

        glb10_part2, C3          2,  1,  1          
            _AND_385                                     2,  4,  1,  1      

        glb11, B6                9,  3,  3          
            BDM_BZY                                      8,  1,  1,  2      
            WRTMP                                        1,  2,  0,  2      
            _BUF_841                                     1,  1,  1,  1      

        glb12, B7                7,  4,  8          
            B0                                           3, 10,  3,  2      
            B2                                           5,  9,  4,  2      
            SQTMP                                        1,  1,  1,  1      
            TEASYNC1                                     1,  2,  1,  1      

        glb13, B1                4,  2,  3          
            TEASYNC3                                     1,  1,  1,  1      
            _OR_419                                      3,  2,  2,  1      

        glb14_part1, C7          5,  2,  4          
            BUFA                                         3,  2,  2,  2      
            BUFF                                         3,  2,  2,  2      

        glb14_part2, B5          5,  3,  4          
            BUF8                                         3,  2,  2,  2      
            BUF9_part1                                   3,  1,  2,  2      
            BUF9_part2                                   3,  1,  2,  2      

        glb15, C0                9,  4,  8          
            BUFB                                         3,  2,  2,  2      
            BUFC                                         3,  2,  2,  2      
            BUFD                                         3,  2,  2,  2      
            BUFE                                         3,  2,  2,  2      

        glb16_part1, B2          7,  4,  6          
            BUF1_part1                                   3,  1,  2,  2      
            BUF1_part2                                   3,  1,  2,  2      
            BUF2                                         3,  2,  2,  2      
            BUF7                                         3,  2,  2,  2      

        glb16_part2, C2          3,  1,  2          
            BUF0                                         3,  2,  2,  2      

        glb17, A3                9,  4,  8          
            BUF3                                         3,  2,  2,  2      
            BUF4                                         3,  2,  2,  2      
            BUF5                                         3,  2,  2,  2      
            BUF6                                         3,  2,  2,  2      

        glb2, C1                 8,  4,  5          
            BKPTSYNC_PIN                                 2,  1,  1,  1      
            SQS                                          4,  3,  2,  3      
            TEASYNC2                                     1,  2,  1,  1      
            _VCC_1012                                    0,  1,  0,  0      

        glb3, C6                 7,  4, 11          
            DSCLK_PIN                                    6,  1,  4,  1      
            SQ0_CE                                       6,  9,  2,  1      
            SQCLK                                        7,  1,  3,  2      
            _OR_407                                      6,  7,  3,  2      

        glb4_part1, A6          11,  3,  8          
            AD2_D                                        6,  1,  3,  2      
            AD3_D                                        6,  1,  3,  2      
            BUF5_buff1                                   1,  1,  1,  1      

        glb4_part2, A1          10,  3,  7          
            AD0_D                                        6,  1,  3,  2      
            AD1_D                                        6,  1,  3,  2      
            BUF6_buff1                                   1,  1,  1,  1      

        glb5, A7                 4,  1,  3          
            BKPT                                         4,  2,  3,  1      

        glb6, C5                17,  4, 16          
            SQ0                                         10,  2,  4,  3      
            SQ1                                         10,  2,  4,  3      
            SQ2                                         10,  3,  4,  3      
            SQF                                         10,  3,  4,  3      

        glb7, A0                17,  4, 16          
            SQ3                                         10,  2,  4,  3      
            SQ4                                         10,  2,  4,  3      
            SQ5                                         10,  3,  4,  3      
            SQE                                         10,  3,  4,  3      

        glb8_part1, A2          13,  3,  8          
            SQ6                                         10,  2,  4,  3      
            SQD_part1                                   10,  1,  4,  3      
            SQD_part2                                   10,  2,  4,  3      

        glb8_part2, A4          12,  3,  8          
            SQA                                         10,  2,  4,  3      
            SQB_part1                                   10,  1,  4,  3      
            SQB_part2                                   10,  2,  4,  3      

        glb9_part1, C4           4,  3,  4          
            B1_part1                                     4,  3,  4,  2      
            B1_part2                                     4,  7,  4,  2      
            SQ0_CE_buff1                                 1,  1,  1,  2      

        glb9_part2, A5          11,  4, 12          
            B3                                           6,  8,  2,  2      
            B4_part1                                     7,  1,  7,  2      
            B4_part2                                     7,  7,  7,  2      
            SQC                                         10,  3,  4,  3      


Maximum-Level Trace

    GLB Level, Name, Ins    GLB Output Name

        3, glb1, 10             SQ9                 
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb1, 10             SQ8                 
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb1, 10             SQ7                 
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb2, 8              SQS                 
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb6, 10             SQF                 
        2, glb9_part1            SQ0_CE_buff1        
        1, glb3                   SQ0_CE              
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb6, 10             SQ2                 
        2, glb9_part1            SQ0_CE_buff1        
        1, glb3                   SQ0_CE              
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb6, 10             SQ1                 
        2, glb9_part1            SQ0_CE_buff1        
        1, glb3                   SQ0_CE              
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb6, 10             SQ0                 
        2, glb9_part1            SQ0_CE_buff1        
        1, glb3                   SQ0_CE              
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb7, 11             SQE                 
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              

        3, glb7, 11             SQ5                 
        2, glb3                  _OR_407             
        1, glb3                   SQ0_CE              


Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        NTEA                    3                       Three-State Output, PULLUP
        DSI                     4                       Output
        BKPTSYNC                5                       Output
        DSCLK                   6                       Output
        NCSDATA                 7                       Input
        NCSCTRL                 8                       Input
        C_TEA                   13                      Input
        ECLK                    14                      Output
        CLK                     16                      Clock Input
        NRD                     22                      Input
        NWR                     29                      Input
        DSO                     30                      Input
        RUN                     31                      Input
        VCC_B5                  32                      Input
        VCC_B3                  33                      Input
        AD0                     37                      Bidirectional
        AD1                     38                      Bidirectional
        AD2                     39                      Bidirectional
        AD3                     40                      Bidirectional
        AD7                     41                      Bidirectional
        AD6                     42                      Bidirectional
        AD4                     47                      Bidirectional
        AD5                     48                      Bidirectional
        BCLK                    54                      Clock Input
        WRTEST                  61                      Output
        A0                      62                      Input
        TOV                     66                      Input


Design process management completed successfully
