;-------------------------------------------------------------------
; CP initializations (cpinit.def)
;-------------------------------------------------------------------

; Chip-Select Control
CS_LEN             EQU     9
UCS_START          EQU     0E000h+CSwait0   ; ROM
UCS_STOP           EQU     0FFC0h+CSen+CSmem+CSistop
LCS_START          EQU     00000h+CSwait0   ; RAM
LCS_STOP           EQU     02000h+CSen+CSmem
CS7_START          EQU     00080h+CSwait0   ; PPort
CS7_STOP           EQU     000C0h+CSen+CSrdy
CS6_START          EQU     00100h+CSwait0   ; TraceCtrl
CS6_STOP           EQU     00140h+CSen
CS5_START          EQU     08000h+CSwait0   ; TraceBuf
CS5_STOP           EQU     09000h+CSen+CSmem
CS4_START          EQU     0FFCFh           ; disable
CS4_STOP           EQU     0FFC3h
CS3_START          EQU     0FFCFh           ; disable
CS3_STOP           EQU     0FFC3h
CS2_START          EQU     00000h+CSwait0   ; BDM
CS2_STOP           EQU     00040h+CSen
CS1_START          EQU     00040h+CSwait0   ; EP
CS1_STOP           EQU     00080h+CSen

; I/O Port
P1CTRLinit         EQU     0E6h
P1LTCHinit         EQU     019h
P2DIRinit          EQU     000h
P2CTRLinit         EQU     000h
P2LTCHinit         EQU     0FFh

; Serial Port
;S0BAUDinit         EQU     SPiclk+16   ;(16MHz/(8*115200))-1
;S0BAUDinit         EQU     SPiclk+34   ;(16MHz/(8*57600))-1
;S0BAUDinit         EQU     SPiclk+103  ;(16MHz/(8*19200))-1
;S0BAUDinit         EQU     SPiclk+207  ;(16MHz/(8*9600))-1
;S0BAUDinit         EQU     10;
S0BAUDinit         EQU     SPiclk+207  ;(16MHz/(8*9600))-1
S0CTRLinit         EQU     SPcts+SPmod1

; Timer
TIME_UNIT          EQU     2500        ;(16MHz/4)*10ms/16
INT_TM0_VEC        EQU     20h
TM0_UNIT           EQU     50h         ;(50ms/10ms)*16
T0CTRLinit         EQU     TmrINH+TmrCONT+TmrINT+TmrP
T1CTRLinit         EQU     TmrINH+TmrINT+TmrP
T2CTRLinit         EQU     TmrINH+TmrCONT

; Interrupt Control
INT_MASK           EQU     8           ;mask bit in control register
INT_LVL            EQU     10h         ;level trigger
SP_INTinit         EQU     0           ;highest priority
TX_INTinit         EQU     1+INT_LVL   ;
RX_INTinit         EQU     2+INT_LVL   ;
TB_INTinit         EQU     3           ;
TR_INTinit         EQU     4           ;
TM_INTinit         EQU     5           ;lowest priority
