 
XEPLD, Version XACT-CPLD-V6.0.2a                            Xilinx Inc.
                                  Fitter Report
   Design Name: c825595
Fitting Status: Successful                          Date: 11- 7-97,  3:02PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
c825595       XC9536-7PC44      19 /36  ( 52%) 54 /180 ( 30%)  34 /34  (100%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   18          18    |  I/O              :    28        0
Output        :    9           9    |  GCK/IO           :     3        0
Bidirectional :    7           7    |  GTS/IO           :     2        0
GCK           :    0           0    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     34          34

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 19 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 19 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
CPD0                4       8       FB1_4   STD  SLOW 4    I/O       I/O
CPD1                4       8       FB1_6   STD  SLOW 8    I/O       I/O
CPD2                4       8       FB1_8   STD  SLOW 9    I/O       I/O
CPD3                3       7       FB1_2   STD  SLOW 3    I/O       O
CPD4                3       7       FB1_1   STD  SLOW 2    I/O       I/O
CPD5                3       7       FB2_1   STD  SLOW 1    I/O       I/O
CPD6                3       7       FB1_9   STD  SLOW 11   I/O       I/O
CPD7                3       7       FB2_2   STD  SLOW 44   I/O       I/O
FLASHCTL            3       3       FB2_18  STD            (b)       (b)
FLASHCTLCLK         1       4       FB2_17  STD       25   I/O       I
NFLASHWR            1       2       FB2_7   STD  SLOW 38   I/O       O
PB0                 3       3       FB2_6   STD  SLOW 39   GSR/I/O   O
PB1                 3       3       FB2_9   STD  SLOW 36   I/O       O
PB2                 3       3       FB2_10  STD  SLOW 35   I/O       O
PB4                 3       3       FB2_12  STD  SLOW 33   I/O       O
PB5                 3       3       FB2_5   STD  SLOW 40   GTS/I/O   O
PB6                 3       3       FB2_13  STD  SLOW 29   I/O       O
PB7                 3       3       FB2_4   STD  SLOW 43   I/O       O
PBCLK               1       4       FB2_16  STD       26   I/O       I

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
CPA0                                FB2_14            28   I/O       I
CPA1                                FB2_3             42   GTS/I/O   I
NCS82552                            FB1_7             7    GCK/I/O   I
NRD                                 FB1_15            20   I/O       I
NWR                                 FB1_14            19   I/O       I
PA0                                 FB1_10            12   I/O       I
PA1                                 FB1_11            13   I/O       I
PA2                                 FB1_12            14   I/O       I
PA3                                 FB2_11            34   I/O       I
PA4                                 FB1_5             6    GCK/I/O   I
PA5                                 FB2_15            27   I/O       I
PA6                                 FB2_16            26   I/O       I
PA7                                 FB2_17            25   I/O       I
PC0                                 FB1_17            24   I/O       I
PC1                                 FB1_16            22   I/O       I
PC2                                 FB1_3             5    GCK/I/O   I
PC3                                 FB2_8             37   I/O       I
RESET                               FB1_13            18   I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           6          20          20           21         1/5       17   
FB2          13          20          20           33         8/2       17   
            ----                                -----       -----     ----- 
             19                                   54         9/7       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               20/16
Number of signals used by logic mapping into function block:  20
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
CPD4                  3       0     0   2     FB1_1   STD   2   I/O     I/O
CPD3                  3       0     0   2     FB1_2   STD   3   I/O     O
(unused)              0       0     0   5     FB1_3         5   GCK/I/O I
CPD0                  4       0     0   1     FB1_4   STD   4   I/O     I/O
(unused)              0       0     0   5     FB1_5         6   GCK/I/O I
CPD1                  4       0     0   1     FB1_6   STD   8   I/O     I/O
(unused)              0       0     0   5     FB1_7         7   GCK/I/O I
CPD2                  4       0     0   1     FB1_8   STD   9   I/O     I/O
CPD6                  3       0     0   2     FB1_9   STD   11  I/O     I/O
(unused)              0       0     0   5     FB1_10        12  I/O     I
(unused)              0       0     0   5     FB1_11        13  I/O     I
(unused)              0       0     0   5     FB1_12        14  I/O     I
(unused)              0       0     0   5     FB1_13        18  I/O     I
(unused)              0       0     0   5     FB1_14        19  I/O     I
(unused)              0       0     0   5     FB1_15        20  I/O     I
(unused)              0       0     0   5     FB1_16        22  I/O     I
(unused)              0       0     0   5     FB1_17        24  I/O     I
(unused)              0       0     0   5     FB1_18            (b)     

Signals Used by Logic in Function Block
  1: CPA0               8: PA3               15: PB6              
  2: CPA1               9: PA4               16: PC0              
  3: NCS82552          10: PA6               17: PC1              
  4: NRD               11: PB0               18: PC2              
  5: PA0               12: PB1               19: PC3              
  6: PA1               13: PB2               20: RESET            
  7: PA2               14: PB4              

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
CPD4                 XXXX....X....X.....X.................... 7       7
CPD3                 XXXX...X..........XX.................... 7       7
CPD0                 XXXXX.....X....X...X.................... 8       8
CPD1                 XXXX.X.....X....X..X.................... 8       8
CPD2                 XXXX..X.....X....X.X.................... 8       8
CPD6                 XXXX.....X....X....X.................... 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               20/16
Number of signals used by logic mapping into function block:  20
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
CPD5                  3       0     0   2     FB2_1   STD   1   I/O     I/O
CPD7                  3       0     0   2     FB2_2   STD   44  I/O     I/O
(unused)              0       0     0   5     FB2_3         42  GTS/I/O I
PB7                   3       0     0   2     FB2_4   STD   43  I/O     O
PB5                   3       0     0   2     FB2_5   STD   40  GTS/I/O O
PB0                   3       0     0   2     FB2_6   STD   39  GSR/I/O O
NFLASHWR              1       0     0   4     FB2_7   STD   38  I/O     O
(unused)              0       0     0   5     FB2_8         37  I/O     I
PB1                   3       0     0   2     FB2_9   STD   36  I/O     O
PB2                   3       0     0   2     FB2_10  STD   35  I/O     O
(unused)              0       0     0   5     FB2_11        34  I/O     I
PB4                   3       0     0   2     FB2_12  STD   33  I/O     O
PB6                   3       0     0   2     FB2_13  STD   29  I/O     O
(unused)              0       0     0   5     FB2_14        28  I/O     I
(unused)              0       0     0   5     FB2_15        27  I/O     I
PBCLK                 1       0     0   4     FB2_16  STD   26  I/O     I
FLASHCTLCLK           1       0     0   4     FB2_17  STD   25  I/O     I
FLASHCTL              3       0     0   2     FB2_18  STD       (b)     (b)

Signals Used by Logic in Function Block
  1: CPA0               8: CPD6.PIN          15: PA5              
  2: CPA1               9: CPD7.PIN          16: PA7              
  3: CPD0.PIN          10: FLASHCTL          17: PB5              
  4: CPD1.PIN          11: FLASHCTLCLK       18: PB7              
  5: CPD2.PIN          12: NCS82552          19: PBCLK            
  6: CPD4.PIN          13: NRD               20: RESET            
  7: CPD5.PIN          14: NWR              

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
CPD5                 XX.........XX.X.X..X.................... 7       7
CPD7                 XX.........XX..X.X.X.................... 7       7
PB7                  ........X.........XX.................... 3       3
PB5                  ......X...........XX.................... 3       3
PB0                  ..X...............XX.................... 3       3
NFLASHWR             .........X...X.......................... 2       2
PB1                  ...X..............XX.................... 3       3
PB2                  ....X.............XX.................... 3       3
PB4                  .....X............XX.................... 3       3
PB6                  .......X..........XX.................... 3       3
PBCLK                XX.........X.X.......................... 4       4
FLASHCTLCLK          XX.........X.X.......................... 4       4
FLASHCTL             ..X.......X........X.................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/CPD0  = /CPA0 * CPA1 */PC0
       +  CPA0 */CPA1 */PB0
       + /CPA0 */CPA1 */PA0    
   CPD0.TRST = /NCS82552 */NRD */RESET

 CPD1  = /CPA0 * CPA1 * PC1
       +  CPA0 */CPA1 * PB1
       + /CPA0 */CPA1 * PA1    
   CPD1.TRST = /NCS82552 */NRD */RESET

/CPD2  = /CPA0 * CPA1 */PC2
       +  CPA0 */CPA1 */PB2
       + /CPA0 */CPA1 */PA2    
   CPD2.TRST = /NCS82552 */NRD */RESET

 CPD4  =  CPA0 */CPA1 * PB4
       + /CPA0 */CPA1 * PA4    
   CPD4.TRST = /NCS82552 */NRD */RESET

 CPD5  =  CPA0 */CPA1 * PB5
       + /CPA0 */CPA1 * PA5    
   CPD5.TRST = /NCS82552 */NRD */RESET

 CPD6  =  CPA0 */CPA1 * PB6
       + /CPA0 */CPA1 * PA6    
   CPD6.TRST = /NCS82552 */NRD */RESET

 CPD7  =  CPA0 */CPA1 * PB7
       + /CPA0 */CPA1 * PA7    
   CPD7.TRST = /NCS82552 */NRD */RESET

/CPD3  = /CPA0 * CPA1 */PC3
       + /CPA0 */CPA1 */PA3    
   CPD3.TRST = /NCS82552 */NRD */RESET

/NFLASHWR  = /NWR */FLASHCTL    

/PB0 := /CPD0.PIN    
   PB0.CLKF =  PBCLK
   PB0.SETF =  RESET
   PB0.PRLD =  GND


/PB1 := /CPD1.PIN    
   PB1.CLKF =  PBCLK
   PB1.SETF =  RESET
   PB1.PRLD =  GND


/PB2 := /CPD2.PIN    
   PB2.CLKF =  PBCLK
   PB2.SETF =  RESET
   PB2.PRLD =  GND


/PB4 := /CPD4.PIN    
   PB4.CLKF =  PBCLK
   PB4.SETF =  RESET
   PB4.PRLD =  GND


/PB5 := /CPD5.PIN    
   PB5.CLKF =  PBCLK
   PB5.SETF =  RESET
   PB5.PRLD =  GND


/PB6 := /CPD6.PIN    
   PB6.CLKF =  PBCLK
   PB6.SETF =  RESET
   PB6.PRLD =  GND


/PB7 := /CPD7.PIN    
   PB7.CLKF =  PBCLK
   PB7.SETF =  RESET
   PB7.PRLD =  GND


/FLASHCTL := /CPD0.PIN    
   FLASHCTL.CLKF =  FLASHCTLCLK
   FLASHCTL.SETF =  RESET
   FLASHCTL.PRLD =  GND


/FLASHCTLCLK  = /CPA0 * CPA1 */NCS82552 */NWR    

/PBCLK  =  CPA0 */CPA1 */NCS82552 */NWR    

****************************  Device Pin Out ****************************

Device : XC9536-7PC44


                 C  C  C  C  C     C        
           P  P  P  P  P  P  P  P  P  V  P  
           A  C  D  D  D  D  D  B  A  C  B  
           4  2  0  3  4  5  7  7  1  C  5  
           --------------------------------  
          /6  5  4  3  2  1  44 43 42 41 40 \
NCS82552 | 7                             39 | PB0
    CPD1 | 8                             38 | NFLASHWR
    CPD2 | 9                             37 | PC3
     GND | 10                            36 | PB1
    CPD6 | 11         XC9536-7PC44       35 | PB2
     PA0 | 12                            34 | PA3
     PA1 | 13                            33 | PB4
     PA2 | 14                            32 | VCC
     TDI | 15                            31 | GND
     TMS | 16                            30 | TDO
     TCK | 17                            29 | PB6
         \ 18 19 20 21 22 23 24 25 26 27 28 /
           --------------------------------  
           R  N  N  V  P  G  P  P  P  P  C  
           E  W  R  C  C  N  C  A  A  A  P  
           S  R  D  C  1  D  0  7  6  5  A  
           E                             0  
           T                                


Legend : N.C. = Pin Not Connected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device Selection Mode                       : Single
Device(s) Specified                         : 9536-7PC44
Global Clock Optimization                   : INDESIGN - ON
Global Output Enable Optimization           : INDESIGN - ON
UIM Optimization                            : INDESIGN - ON
Timing Optimization                         : OFF
Ignore Tspecs                               : OFF
Create Programmable Ground Pins             : OFF
Guide File Used                             : NONE
Ignore Pin Assignments                      : OFF
Restore Pin Assignments After Optimizations : ON
Collapsing pterm limit                      : 15
Collapsing input limit                      : 36
