 
XEPLD, Version XACT-CPLD-V6.0.2a                            Xilinx Inc.
                                  Fitter Report
   Design Name: instr95
Fitting Status: Successful                          Date: 11-27-97, 12:55PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
instr95       XC9536-5PC44      27 /36  ( 75%) 119/180 ( 66%)  34 /34  (100%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   24          24    |  I/O              :    28        0
Output        :    9           9    |  GCK/IO           :     3        0
Bidirectional :    0           0    |  GTS/IO           :     2        0
GCK           :    1           1    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     34          34

GLOBAL RESOURCES:

Signal 'EPSENN' mapped onto global clock net GCK1.
The complement of 'EPSENN' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 27 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 27 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
DCLR                2       4       FB1_3   STD       5    GCK/I/O   GCK/I
EA0                 3       2       FB2_1   STD       1    I/O       I
EPCLKD              3       1       FB1_13  STD       18   I/O       I
M1CTL0              3       4       FB1_4   STD  FAST 4    I/O       O
M1CTL1              3       4       FB2_4   STD  FAST 43   I/O       O
M1CTL2              3       4       FB1_8   STD  FAST 9    I/O       O
M2CTL0              3       4       FB2_9   STD  FAST 36   I/O       O
M2CTL1              3       4       FB2_14  STD  FAST 28   I/O       O
M2CTL2              2       2       FB2_3   STD  FAST 42   GTS/I/O   O
MUXOUT1             2       6       FB2_5   STD       40   GTS/I/O   I
MUXOUT2             10      16      FB1_14  STD       19   I/O       I
MUXOUT2D            3       2       FB1_11  STD       13   I/O       I
MUXOUT3             8       16      FB2_7   STD       38   I/O       I
MUXOUT3D            3       2       FB1_10  STD       12   I/O       I
MUXOUT4             13      11      FB2_16  STD       26   I/O       I
MUXOUT4D            3       2       FB1_9   STD       11   I/O       I
MUXOUT5             11      10      FB2_11  STD       34   I/O       I
MUXOUT5D            3       2       FB1_7   STD       7    GCK/I/O   I
MUXOUT6             7       10      FB2_2   STD       44   I/O       I
MUXOUT6D            3       2       FB1_6   STD       8    I/O       I
NDTRN               1       1       FB2_8   STD  FAST 37   I/O       O
NEPSENND            3       1       FB1_5   STD       6    GCK/I/O   I
SYNC0               4       6       FB1_12  STD  FAST 14   I/O       O
SYNC0AR             2       3       FB1_2   STD       3    I/O       I
SYNC0HIT            13      17      FB2_13  STD       29   I/O       I
SYNC1               3       4       FB1_16  STD  FAST 22   I/O       O
SYNC1AR             2       8       FB1_1   STD       2    I/O       I

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
BUSIZE                              FB1_9             11   I/O       I
CFGRDY                              FB2_6             39   GSR/I/O   I
DTRN                                FB2_11            34   I/O       I
EA0X                                FB2_10            35   I/O       I
ECYC0                               FB1_6             8    I/O       I
ECYC1                               FB1_10            12   I/O       I
EPCLK                               FB1_5             6    GCK/I/O   I
EPSENN                              FB1_3             5    GCK/I/O   GCK/I
FLUSHX                              FB1_11            13   I/O       I
NCSINS                              FB2_5             40   GTS/I/O   I
RAMA0                               FB2_7             38   I/O       I
RAMA1                               FB2_12            33   I/O       I
RAMA2                               FB2_13            29   I/O       I
RAMB0                               FB1_13            18   I/O       I
RAMB1                               FB2_17            25   I/O       I
RAMB2                               FB1_14            19   I/O       I
RAMC0                               FB2_15            27   I/O       I
RAMC1                               FB2_1             1    I/O       I
RAMC2                               FB1_2             3    I/O       I
RAMC3                               FB1_17            24   I/O       I
RAMC4                               FB1_15            20   I/O       I
RAMC5                               FB2_16            26   I/O       I
RAMC6                               FB1_1             2    I/O       I
RAMC7                               FB2_2             44   I/O       I
SPOONRUN                            FB1_7             7    GCK/I/O   I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          15          36          36           50         4/0       17   
FB2          12          26          26           69         5/0       17   
            ----                                -----       -----     ----- 
             27                                  119         9/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
SYNC1AR               2       0     0   3     FB1_1   STD   2   I/O     I
SYNC0AR               2       0     0   3     FB1_2   STD   3   I/O     I
DCLR                  2       0     0   3     FB1_3   STD   5   GCK/I/O GCK/I
M1CTL0                3       0     0   2     FB1_4   STD   4   I/O     O
NEPSENND              3       0     0   2     FB1_5   STD   6   GCK/I/O I
MUXOUT6D              3       0     0   2     FB1_6   STD   8   I/O     I
MUXOUT5D              3       0     0   2     FB1_7   STD   7   GCK/I/O I
M1CTL2                3       0     0   2     FB1_8   STD   9   I/O     O
MUXOUT4D              3       0     0   2     FB1_9   STD   11  I/O     I
MUXOUT3D              3       0     0   2     FB1_10  STD   12  I/O     I
MUXOUT2D              3       0     0   2     FB1_11  STD   13  I/O     I
SYNC0                 4       0     0   1     FB1_12  STD   14  I/O     O
EPCLKD                3       0   \/2   0     FB1_13  STD   18  I/O     I
MUXOUT2              10       5<-   0   0     FB1_14  STD   19  I/O     I
(unused)              0       0   /\3   2     FB1_15        20  I/O     I
SYNC1                 3       0     0   2     FB1_16  STD   22  I/O     O
(unused)              0       0     0   5     FB1_17        24  I/O     I
(unused)              0       0     0   5     FB1_18            (b)     

Signals Used by Logic in Function Block
  1: BUSIZE            13: MUXOUT4           25: RAMB2            
  2: CFGRDY            14: MUXOUT4D          26: RAMC0            
  3: DCLR              15: MUXOUT5           27: RAMC1            
  4: EA0               16: MUXOUT6           28: RAMC2            
  5: ECYC0             17: MUXOUT6D          29: RAMC3            
  6: ECYC1             18: NCSINS            30: RAMC5            
  7: EPCLK             19: NEPSENND          31: RAMC6            
  8: EPSENN            20: RAMA0             32: RAMC7            
  9: FLUSHX            21: RAMA1             33: SPOONRUN         
 10: MUXOUT1           22: RAMA2             34: SYNC0AR          
 11: MUXOUT2           23: RAMB0             35: SYNC0HIT         
 12: MUXOUT3           24: RAMB1             36: SYNC1AR          

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SYNC1AR              XX.X..X.X..........XXX.................. 8       8
SYNC0AR              .X.....X..........X..................... 3       3
DCLR                 .X..XX..X............................... 4       4
M1CTL0               ..X..........X...X..............X....... 4       4
NEPSENND             .......X................................ 1       1
MUXOUT6D             ......X........X........................ 2       2
MUXOUT5D             ......X.......X......................... 2       2
M1CTL2               ..X.............XX..............X....... 4       4
MUXOUT4D             ......X.....X........................... 2       2
MUXOUT3D             ......X....X............................ 2       2
MUXOUT2D             ......X...X............................. 2       2
SYNC0                X..X....X.......................XXX..... 6       6
EPCLKD               ......X................................. 1       1
MUXOUT2              X..X....X..........XXXXXXXXXXXXX........ 16      16
SYNC1                .X....X..X.........................X.... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               26/10
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
EA0                   3       0   \/1   1     FB2_1   STD   1   I/O     I
MUXOUT6               7       2<-   0   0     FB2_2   STD   44  I/O     I
M2CTL2                2       0   /\1   2     FB2_3   STD   42  GTS/I/O O
M1CTL1                3       0     0   2     FB2_4   STD   43  I/O     O
MUXOUT1               2       0     0   3     FB2_5   STD   40  GTS/I/O I
(unused)              0       0   \/1   4     FB2_6         39  GSR/I/O I
MUXOUT3               8       3<-   0   0     FB2_7   STD   38  I/O     I
NDTRN                 1       0   /\2   2     FB2_8   STD   37  I/O     O
M2CTL0                3       0   \/2   0     FB2_9   STD   36  I/O     O
(unused)              0       0   \/5   0     FB2_10        35  I/O     I
MUXOUT5              11       7<- \/1   0     FB2_11  STD   34  I/O     I
(unused)              0       0   \/5   0     FB2_12        33  I/O     I
SYNC0HIT             13       8<-   0   0     FB2_13  STD   29  I/O     I
M2CTL1                3       0   /\2   0     FB2_14  STD   28  I/O     O
(unused)              0       0   \/5   0     FB2_15        27  I/O     I
MUXOUT4              13       8<-   0   0     FB2_16  STD   26  I/O     I
(unused)              0       0   /\3   2     FB2_17        25  I/O     I
(unused)              0       0     0   5     FB2_18            (b)     

Signals Used by Logic in Function Block
  1: BUSIZE            10: MUXOUT5D          19: RAMC1            
  2: DCLR              11: NCSINS            20: RAMC2            
  3: DTRN              12: RAMA0             21: RAMC3            
  4: EA0               13: RAMA1             22: RAMC4            
  5: EA0X              14: RAMA2             23: RAMC5            
  6: EPCLKD            15: RAMB0             24: RAMC6            
  7: FLUSHX            16: RAMB1             25: RAMC7            
  8: MUXOUT2D          17: RAMB2             26: SPOONRUN         
  9: MUXOUT3D          18: RAMC0            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
EA0                  ....XX.................................. 2       2
MUXOUT6              X..X..X....XXX..X.....XXX............... 10      10
M2CTL2               ..........X..............X.............. 2       2
M1CTL1               .X.......XX..............X.............. 4       4
MUXOUT1              X..X..X....XXX.......................... 6       6
MUXOUT3              X..X..X....XXXXXXXXXX.XXX............... 16      16
NDTRN                ..X..................................... 1       1
M2CTL0               .X.....X..X..............X.............. 4       4
MUXOUT5              X..X..X....XXX.X..X.X..X................ 10      10
SYNC0HIT             X..X..X....XXXXXXXXXXXXXX............... 17      17
M2CTL1               .X......X.X..............X.............. 4       4
MUXOUT4              X..X..X....XXXX..X.X.XX................. 11      11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/M1CTL0 := /MUXOUT4D    
   M1CTL0.CLKF =  EPSENN
   M1CTL0.RSTF =  DCLR
   M1CTL0.TRST =  NCSINS */SPOONRUN
   M1CTL0.PRLD =  GND


/M1CTL1 := /MUXOUT5D    
   M1CTL1.CLKF =  EPSENN
   M1CTL1.RSTF =  DCLR
   M1CTL1.TRST =  NCSINS */SPOONRUN
   M1CTL1.PRLD =  GND


/M1CTL2 := /MUXOUT6D    
   M1CTL2.CLKF =  EPSENN
   M1CTL2.RSTF =  DCLR
   M1CTL2.TRST =  NCSINS */SPOONRUN
   M1CTL2.PRLD =  GND


/M2CTL0 := /MUXOUT2D    
   M2CTL0.CLKF =  EPSENN
   M2CTL0.RSTF =  DCLR
   M2CTL0.TRST =  NCSINS */SPOONRUN
   M2CTL0.PRLD =  GND


/M2CTL1 := /MUXOUT3D    
   M2CTL1.CLKF =  EPSENN
   M2CTL1.RSTF =  DCLR
   M2CTL1.TRST =  NCSINS */SPOONRUN
   M2CTL1.PRLD =  GND


/M2CTL2 := Vcc    
   M2CTL2.CLKF = Gnd
   M2CTL2.TRST =  NCSINS */SPOONRUN
   M2CTL2.PRLD =  GND


/NDTRN  =  DTRN    

/SYNC0 := /BUSIZE * EA0
       + /FLUSHX * SPOONRUN
       + /FLUSHX */SYNC0HIT    
   SYNC0.CLKF = / EPSENN
   SYNC0.RSTF =  SYNC0AR
   SYNC0.PRLD =  GND


/SYNC1 := Vcc    
   SYNC1.CLKF = Gnd
   SYNC1.RSTF =  SYNC1AR
   SYNC1.SETF =  CFGRDY * EPCLK * MUXOUT1
   SYNC1.PRLD =  GND


 DCLR  = /CFGRDY
       +  ECYC0 */ECYC1 * FLUSHX    

/EA0 := Vcc    
   EA0.CLKF = Gnd
   EA0.RSTF = /EA0X */EPCLKD
   EA0.SETF =  EA0X */EPCLKD
   EA0.PRLD =  GND


/EPCLKD := Vcc    
   EPCLKD.CLKF = Gnd
   EPCLKD.RSTF = /EPCLK
   EPCLKD.SETF =  EPCLK
   EPCLKD.PRLD =  GND


 MUXOUT1  = /BUSIZE * FLUSHX * EA0
       + /BUSIZE */RAMA0 */RAMA1 */RAMA2    

 MUXOUT2  = /BUSIZE */FLUSHX * RAMA0 * RAMA1 */RAMA2
       + /BUSIZE * RAMA0 * RAMA1 */RAMA2 */EA0
       + /BUSIZE */FLUSHX * RAMA0 * RAMA1 */RAMC0 * RAMC1
       + /BUSIZE * RAMA0 * RAMA1 */RAMC0 * RAMC1 */EA0
       + /BUSIZE * FLUSHX */RAMB0 * RAMB1 */RAMB2 * EA0    
;Imported pterms
       + /BUSIZE */RAMA0 * RAMA1 * RAMA2 */RAMC2 * RAMC3 */EA0
       + /BUSIZE */RAMA0 */RAMA1 */RAMA2 */RAMB0 * RAMB1 */RAMB2
;Imported pterms
       + /BUSIZE */FLUSHX */RAMA0 * RAMA1 * RAMA2 */RAMC2 * RAMC3
       + /BUSIZE */FLUSHX */RAMA0 */RAMA1 * RAMA2 */RAMC5 * RAMC6
           */RAMC7
       + /BUSIZE */RAMA0 */RAMA1 * RAMA2 */RAMC5 * RAMC6 */RAMC7
           */EA0    

/MUXOUT2D := Vcc    
   MUXOUT2D.CLKF = Gnd
   MUXOUT2D.RSTF =  EPCLK */MUXOUT2
   MUXOUT2D.SETF =  EPCLK * MUXOUT2
   MUXOUT2D.PRLD =  GND


 MUXOUT3  = /BUSIZE * FLUSHX * RAMB0 * RAMB1 */RAMB2 * EA0
       + /BUSIZE */FLUSHX * RAMA0 * RAMA1 * RAMA2 * RAMC0 * RAMC1
       + /BUSIZE * RAMA0 * RAMA1 * RAMA2 * RAMC0 * RAMC1 */EA0
       + /BUSIZE */RAMA0 * RAMA1 * RAMA2 * RAMC2 * RAMC3 */EA0
       + /BUSIZE */RAMA0 */RAMA1 */RAMA2 * RAMB0 * RAMB1 */RAMB2    
;Imported pterms
       + /BUSIZE */FLUSHX */RAMA0 * RAMA1 * RAMA2 * RAMC2 * RAMC3    
;Imported pterms
       + /BUSIZE */FLUSHX */RAMA0 */RAMA1 * RAMA2 * RAMC5 * RAMC6
           */RAMC7
       + /BUSIZE */RAMA0 */RAMA1 * RAMA2 * RAMC5 * RAMC6 */RAMC7
           */EA0

/MUXOUT3D := Vcc    
   MUXOUT3D.CLKF = Gnd
   MUXOUT3D.RSTF =  EPCLK */MUXOUT3
   MUXOUT3D.SETF =  EPCLK * MUXOUT3
   MUXOUT3D.PRLD =  GND


 MUXOUT4  =  BUSIZE * RAMA0
       + /BUSIZE */RAMA0 */RAMA2 * RAMB0
       + /BUSIZE * FLUSHX * RAMB0 * EA0
       + /BUSIZE */RAMA0 * RAMA1 */RAMA2 */EA0
       + /BUSIZE */RAMA0 * RAMA1 * RAMC2 */EA0    
;Imported pterms
       + /BUSIZE */FLUSHX */RAMA0 * RAMA1 */RAMA2
       + /BUSIZE */FLUSHX */RAMA0 * RAMA1 * RAMC2
       + /FLUSHX * RAMA0 * RAMA1 * RAMA2 * RAMC0
       +  RAMA0 * RAMA1 * RAMA2 * RAMC0 */EA0
       +  RAMA0 */RAMA1 * RAMA2 * RAMC4 */EA0    
;Imported pterms
       + /FLUSHX * RAMA0 */RAMA1 * RAMA2 * RAMC4
       + /BUSIZE */FLUSHX */RAMA0 */RAMA1 * RAMA2 * RAMC5
       + /BUSIZE */RAMA0 */RAMA1 * RAMA2 * RAMC5 */EA0    

/MUXOUT4D := Vcc    
   MUXOUT4D.CLKF = Gnd
   MUXOUT4D.RSTF =  EPCLK */MUXOUT4
   MUXOUT4D.SETF =  EPCLK * MUXOUT4
   MUXOUT4D.PRLD =  GND


 MUXOUT5  =  BUSIZE * RAMA1
       + /BUSIZE * FLUSHX * RAMB1 * EA0
       +  RAMA0 * RAMA1 */RAMA2 */EA0
       +  RAMA0 * RAMA1 * RAMC1 */EA0    
;Imported pterms
       + /FLUSHX * RAMA0 * RAMA1 */RAMA2
       + /FLUSHX * RAMA0 * RAMA1 * RAMC1
       + /BUSIZE */RAMA0 */RAMA1 */RAMA2 * RAMB1
       + /FLUSHX */RAMA0 * RAMA1 * RAMA2 * RAMC3
       + /RAMA0 * RAMA1 * RAMA2 * RAMC3 */EA0    
;Imported pterms
       + /BUSIZE */FLUSHX */RAMA0 */RAMA1 * RAMA2 * RAMC6
       + /BUSIZE */RAMA0 */RAMA1 * RAMA2 * RAMC6 */EA0

/MUXOUT5D := Vcc    
   MUXOUT5D.CLKF = Gnd
   MUXOUT5D.RSTF =  EPCLK */MUXOUT5
   MUXOUT5D.SETF =  EPCLK * MUXOUT5
   MUXOUT5D.PRLD =  GND


 MUXOUT6  =  BUSIZE * RAMA2
       + /BUSIZE * FLUSHX * RAMB2 * EA0
       + /BUSIZE */RAMA0 */RAMA1 */RAMA2 * RAMB2
       + /RAMA0 */RAMA1 * RAMA2 * RAMC5 * RAMC7 */EA0
       + /RAMA0 */RAMA1 * RAMA2 * RAMC6 * RAMC7 */EA0    
;Imported pterms
       + /FLUSHX */RAMA0 */RAMA1 * RAMA2 * RAMC5 * RAMC7
;Imported pterms
       + /FLUSHX */RAMA0 */RAMA1 * RAMA2 * RAMC6 * RAMC7

/MUXOUT6D := Vcc    
   MUXOUT6D.CLKF = Gnd
   MUXOUT6D.RSTF =  EPCLK */MUXOUT6
   MUXOUT6D.SETF =  EPCLK * MUXOUT6
   MUXOUT6D.PRLD =  GND


/NEPSENND := Vcc    
   NEPSENND.CLKF = Gnd
   NEPSENND.RSTF =  EPSENN
   NEPSENND.SETF = /EPSENN
   NEPSENND.PRLD =  GND


/SYNC0AR  =  CFGRDY */EPSENN
       +  CFGRDY */NEPSENND    

 SYNC0HIT :=  BUSIZE */RAMA0 */RAMA1 */RAMA2
       + /BUSIZE */FLUSHX * RAMA0 */RAMA1 */RAMC4
       + /BUSIZE * RAMA0 */RAMA1 */RAMC4 */EA0
       + /BUSIZE */FLUSHX * RAMA0 */RAMA1 */RAMA2
       + /BUSIZE * RAMA0 */RAMA1 */RAMA2 */EA0    
;Imported pterms
       + /BUSIZE */RAMA1 */RAMA2 */RAMB0 */RAMB1 */RAMB2
       + /BUSIZE * FLUSHX */RAMB0 */RAMB1 */RAMB2 * EA0
       + /BUSIZE */FLUSHX * RAMA0 * RAMA1 * RAMA2 */RAMC0 */RAMC1
       + /BUSIZE * RAMA0 * RAMA1 * RAMA2 */RAMC0 */RAMC1 */EA0
       + /BUSIZE */RAMA0 * RAMA1 * RAMA2 */RAMC2 */RAMC3 */EA0    
;Imported pterms
       + /BUSIZE */FLUSHX */RAMA0 */RAMA1 * RAMA2 */RAMC5 */RAMC6
           */RAMC7
;Imported pterms
       + /BUSIZE */FLUSHX */RAMA0 * RAMA1 * RAMA2 */RAMC2 */RAMC3
       + /BUSIZE */RAMA0 */RAMA1 * RAMA2 */RAMC5 */RAMC6 */RAMC7
           */EA0
   SYNC0HIT.CLKF =  EPSENN
   SYNC0HIT.PRLD =  GND


/SYNC1AR  = /BUSIZE * CFGRDY * EPCLK * FLUSHX * EA0
       + /BUSIZE * CFGRDY * EPCLK */RAMA0 */RAMA1 */RAMA2    

****************************  Device Pin Out ****************************

Device : XC9536-5PC44


              E  M              M  M     N  
           E  P  1  R  R  R  R  1  2     C  
           P  S  C  A  A  A  A  C  C     S  
           C  E  T  M  M  M  M  T  T  V  I  
           L  N  L  C  C  C  C  L  L  C  N  
           K  N  0  2  6  1  7  1  2  C  S  
           --------------------------------  
          /6  5  4  3  2  1  44 43 42 41 40 \
SPOONRUN | 7                             39 | CFGRDY
   ECYC0 | 8                             38 | RAMA0
  M1CTL2 | 9                             37 | NDTRN
     GND | 10                            36 | M2CTL0
  BUSIZE | 11         XC9536-5PC44       35 | EA0X
   ECYC1 | 12                            34 | DTRN
  FLUSHX | 13                            33 | RAMA1
   SYNC0 | 14                            32 | VCC
     TDI | 15                            31 | GND
     TMS | 16                            30 | TDO
     TCK | 17                            29 | RAMA2
         \ 18 19 20 21 22 23 24 25 26 27 28 /
           --------------------------------  
           R  R  R  V  S  G  R  R  R  R  M  
           A  A  A  C  Y  N  A  A  A  A  2  
           M  M  M  C  N  D  M  M  M  M  C  
           B  B  C     C     C  B  C  C  T  
           0  2  4     1     3  1  5  0  L  


Legend : N.C. = Pin Not Connected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device Selection Mode                       : Single
Device(s) Specified                         : 9536-5PC44
Global Clock Optimization                   : INDESIGN - ON
Global Output Enable Optimization           : INDESIGN - ON
UIM Optimization                            : INDESIGN - ON
Timing Optimization                         : OFF
Ignore Tspecs                               : OFF
Create Programmable Ground Pins             : OFF
Guide File Used                             : NONE
Ignore Pin Assignments                      : OFF
Restore Pin Assignments After Optimizations : ON
Collapsing pterm limit                      : 15
Collapsing input limit                      : 36
