 
XEPLD, Version XACT-CPLD-V6.0.2a                            Xilinx Inc.
                                  Fitter Report
   Design Name: e953605
Fitting Status: Successful                          Date:  1-16-98,  2:40PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
e953605       XC9536-7PC44      36 /36  (100%) 106/180 ( 58%)  34 /34  (100%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   17          17    |  I/O              :    28        0
Output        :   16          16    |  GCK/IO           :     3        0
Bidirectional :    0           0    |  GTS/IO           :     2        0
GCK           :    1           1    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     34          34

GLOBAL RESOURCES:

Signal 'EPCLK' mapped onto global clock net GCK1.
The complement of 'EPCLK' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 36 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 36 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
ALEI                4       6       FB2_12  STD       33   I/O       I
ALEIARST            3       6       FB2_11  STD       34   I/O       I
BUSIZE8             4       7       FB2_17  STD  SLOW 25   I/O       O
BUSIZE8D            3       1       FB1_18  STD            (b)       (b)
CODENDATA           3       5       FB1_17  STD  FAST 24   I/O       O
CODENDATAD          3       1       FB1_7   STD  SLOW 7    GCK/I/O   O
CODENDATAD0         3       1       FB1_16  STD       22   I/O       I
DATALE              3       6       FB2_6   STD       39   GSR/I/O   I
DATALEDATA          2       6       FB1_10  STD       12   I/O       I
DATALEOUT           2       2       FB1_9   STD       11   I/O       I
ECYC4               3       2       FB1_15  STD       20   I/O       I
EPALE               4       6       FB2_13  STD  SLOW 29   I/O       O
EPALEARST           6       9       FB2_18  STD            (b)       (b)
EPCLKCNT0           2       2       FB1_8   STD       9    I/O       I
EPCLKCNT1           2       2       FB1_6   STD       8    I/O       I
EPPSEN              2       5       FB2_14  STD  SLOW 28   I/O       O
EPRD                2       5       FB2_15  STD  SLOW 27   I/O       O
EPROMCYC            2       3       FB2_5   STD  FAST 40   GTS/I/O   O
EPWR                2       6       FB2_16  STD  SLOW 26   I/O       O
FLUSH               2       3       FB2_10  STD  SLOW 35   I/O       O
FLUSHCLK            3       6       FB1_14  STD       19   I/O       I
FLUSHI              3       4       FB1_13  STD       18   I/O       I
FLUSHIAR            2       4       FB1_5   STD       6    GCK/I/O   I
FLUSHJ              3       3       FB1_11  STD       13   I/O       I
NADVALID            5       14      FB2_7   STD  SLOW 38   I/O       O
NCODE               3       9       FB2_1   STD       1    I/O       I
NCODEAP             2       3       FB1_4   STD       4    I/O       I
NCODEAR             2       6       FB1_3   STD       5    GCK/I/O   GCK/I
NCODEARPRE          2       1       FB1_2   STD       3    I/O       I
NCODEARPREAR        1       3       FB1_1   STD       2    I/O       I
NDATAVALID          5       14      FB2_4   STD  FAST 43   I/O       O
NSTROBE             5       14      FB2_9   STD  FAST 36   I/O       O
NSTSVALID           5       14      FB2_8   STD  SLOW 37   I/O       O
RDWRPSEN            3       6       FB1_12  STD  FAST 14   I/O       O
TPSEN               1       3       FB2_2   STD  FAST 44   I/O       O
WNR                 4       8       FB2_3   STD  SLOW 42   GTS/I/O   O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
BOUTRDY                             FB1_15            20   I/O       I
CFGRDY                              FB1_16            22   I/O       I
ECYC0                               FB1_6             8    I/O       I
ECYC1                               FB1_8             9    I/O       I
ECYC2                               FB1_9             11   I/O       I
ECYC3                               FB1_10            12   I/O       I
ECYC4X                              FB1_11            13   I/O       I
EPCLK                               FB1_3             5    GCK/I/O   GCK/I
EPSENPAGE                           FB1_14            19   I/O       I
NMHERE                              FB2_12            33   I/O       I
NPAGE                               FB1_13            18   I/O       I
NXALE                               FB1_4             4    I/O       I
SPOONRUN                            FB2_6             39   GSR/I/O   I
TMP10K2A                            FB2_11            34   I/O       I
TPSENOUT                            FB1_5             6    GCK/I/O   I
WAIT0                               FB2_1             1    I/O       I
WAIT1                               FB1_1             2    I/O       I
WAIT2                               FB1_2             3    I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          18          27          27           44         3/0       17   
FB2          18          35          35           62        13/0       17   
            ----                                -----       -----     ----- 
             36                                  106        16/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               27/9
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
NCODEARPREAR          1       0     0   4     FB1_1   STD   2   I/O     I
NCODEARPRE            2       0     0   3     FB1_2   STD   3   I/O     I
NCODEAR               2       0     0   3     FB1_3   STD   5   GCK/I/O GCK/I
NCODEAP               2       0     0   3     FB1_4   STD   4   I/O     I
FLUSHIAR              2       0     0   3     FB1_5   STD   6   GCK/I/O I
EPCLKCNT1             2       0     0   3     FB1_6   STD   8   I/O     I
CODENDATAD            3       0     0   2     FB1_7   STD   7   GCK/I/O O
EPCLKCNT0             2       0     0   3     FB1_8   STD   9   I/O     I
DATALEOUT             2       0     0   3     FB1_9   STD   11  I/O     I
DATALEDATA            2       0     0   3     FB1_10  STD   12  I/O     I
FLUSHJ                3       0     0   2     FB1_11  STD   13  I/O     I
RDWRPSEN              3       0     0   2     FB1_12  STD   14  I/O     O
FLUSHI                3       0     0   2     FB1_13  STD   18  I/O     I
FLUSHCLK              3       0     0   2     FB1_14  STD   19  I/O     I
ECYC4                 3       0     0   2     FB1_15  STD   20  I/O     I
CODENDATAD0           3       0     0   2     FB1_16  STD   22  I/O     I
CODENDATA             3       0     0   2     FB1_17  STD   24  I/O     O
BUSIZE8D              3       0     0   2     FB1_18  STD       (b)     (b)

Signals Used by Logic in Function Block
  1: ALEI              10: ECYC1             19: EPSENPAGE        
  2: ALEIARST          11: ECYC2             20: EPWR             
  3: BOUTRDY           12: ECYC3             21: FLUSHCLK         
  4: BUSIZE8           13: ECYC4             22: FLUSHI           
  5: CFGRDY            14: ECYC4X            23: FLUSHIAR         
  6: CODENDATA         15: EPCLK             24: NCODE            
  7: CODENDATAD0       16: EPCLKCNT0         25: NCODEARPRE       
  8: DATALE            17: EPPSEN            26: NCODEARPREAR     
  9: ECYC0             18: EPRD              27: NPAGE            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
NCODEARPREAR         ........XX..X........................... 3       3
NCODEARPRE           .........................X.............. 1       1
NCODEAR              ...XX...XX..X...........X............... 6       6
NCODEAP              ...XX.........X......................... 3       3
FLUSHIAR             ..X.....XX....X......................... 4       4
EPCLKCNT1            .X.............X........................ 2       2
CODENDATAD           ......X................................. 1       1
EPCLKCNT0            XX...................................... 2       2
DATALEOUT            X......X................................ 2       2
DATALEDATA           ..X.....XXXXX........................... 6       6
FLUSHJ               ...X................XX.................. 3       3
RDWRPSEN             ..X.....XXXXX........................... 6       6
FLUSHI               ........XX....X.......X................. 4       4
FLUSHCLK             ...X............XXXX......X............. 6       6
ECYC4                .............XX......................... 2       2
CODENDATAD0          .....X.................................. 1       1
CODENDATA            ...X..........X...X....X..X............. 5       5
BUSIZE8D             ...X.................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               35/1
Number of signals used by logic mapping into function block:  35
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
NCODE                 3       0     0   2     FB2_1   STD   1   I/O     I
TPSEN                 1       0     0   4     FB2_2   STD   44  I/O     O
WNR                   4       0     0   1     FB2_3   STD   42  GTS/I/O O
NDATAVALID            5       0     0   0     FB2_4   STD   43  I/O     O
EPROMCYC              2       0     0   3     FB2_5   STD   40  GTS/I/O O
DATALE                3       0     0   2     FB2_6   STD   39  GSR/I/O I
NADVALID              5       0     0   0     FB2_7   STD   38  I/O     O
NSTSVALID             5       0     0   0     FB2_8   STD   37  I/O     O
NSTROBE               5       0     0   0     FB2_9   STD   36  I/O     O
FLUSH                 2       0     0   3     FB2_10  STD   35  I/O     O
ALEIARST              3       0     0   2     FB2_11  STD   34  I/O     I
ALEI                  4       0     0   1     FB2_12  STD   33  I/O     I
EPALE                 4       0     0   1     FB2_13  STD   29  I/O     O
EPPSEN                2       0     0   3     FB2_14  STD   28  I/O     O
EPRD                  2       0     0   3     FB2_15  STD   27  I/O     O
EPWR                  2       0     0   3     FB2_16  STD   26  I/O     O
BUSIZE8               4       0   \/1   0     FB2_17  STD   25  I/O     O
EPALEARST             6       1<-   0   0     FB2_18  STD       (b)     (b)

Signals Used by Logic in Function Block
  1: ALEI              13: ECYC4             25: NCODEAR          
  2: ALEIARST          14: EPALEARST         26: NMHERE           
  3: BOUTRDY           15: EPCLK             27: NPAGE            
  4: BUSIZE8           16: EPCLKCNT0         28: NSTROBE          
  5: BUSIZE8D          17: EPCLKCNT1         29: NXALE            
  6: CFGRDY            18: EPPSEN            30: SPOONRUN         
  7: DATALEDATA        19: EPRD              31: TMP10K2A         
  8: DATALEOUT         20: EPSENPAGE         32: TPSENOUT         
  9: ECYC0             21: EPWR              33: WAIT0            
 10: ECYC1             22: FLUSHI            34: WAIT1            
 11: ECYC2             23: FLUSHJ            35: WAIT2            
 12: ECYC3             24: NCODEAP          

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
NCODE                ...X.X.XXXX...X........XX............... 9       9
TPSEN                .....X...........X.............X........ 3       3
WNR                  ....................X....X.X.XX.XXX..... 8       8
NDATAVALID           X..X.X..XXXXX.X..XXXX.....X............. 14      14
EPROMCYC             ........XX..X........................... 3       3
DATALE               ......X.XXXXX........................... 6       6
NADVALID             X..X.X..XXXXX.X..XXXX.....X............. 14      14
NSTSVALID            X..X.X..XXXXX.X..XXXX.....X............. 14      14
NSTROBE              X..X.X..XXXXX.X..XXXX.....X............. 14      14
FLUSH                ....X................XX................. 3       3
ALEIARST             ..X.....XXXXX........................... 6       6
ALEI                 .X......XXXXX........................... 6       6
EPALE                ........XXXXXX.......................... 6       6
EPPSEN               ..X.....XXXX............................ 5       5
EPRD                 ..X.....XXXX............................ 5       5
EPWR                 ..X.....XXXXX........................... 6       6
BUSIZE8              ....X...XXXXX.X......................... 7       7
EPALEARST            ..X.....XXXXX..XX...........X........... 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/BUSIZE8 := /ECYC0 */ECYC4
       + /ECYC1 */ECYC4
       +  ECYC2 * ECYC3 */BUSIZE8D */ECYC4    
   BUSIZE8.CLKF = / EPCLK
   BUSIZE8.SETF =  ECYC0 * ECYC1 * ECYC2 * ECYC3 */EPCLK */ECYC4
   BUSIZE8.PRLD =  GND


/CODENDATA  =  NPAGE */NCODE
       + /BUSIZE8 */NCODE
       +  EPCLK * EPSENPAGE */NPAGE * BUSIZE8    

/CODENDATAD := Vcc    
   CODENDATAD.CLKF = Gnd
   CODENDATAD.RSTF = /CODENDATAD0
   CODENDATAD.SETF =  CODENDATAD0
   CODENDATAD.PRLD =  GND


/EPALE := /ECYC4
       +  ECYC0 * ECYC1 */ECYC2
       +  ECYC0 * ECYC1 */ECYC3    
   EPALE.CLKF = / EPCLK
   EPALE.RSTF =  EPALEARST
   EPALE.PRLD =  GND


/EPPSEN :=  ECYC0 * ECYC1 */ECYC2 */ECYC3    
   EPPSEN.CLKF = / EPCLK
   EPPSEN.SETF = /BOUTRDY
   EPPSEN.PRLD =  VCC


/EPRD :=  ECYC0 * ECYC1 */ECYC2 * ECYC3    
   EPRD.CLKF = / EPCLK
   EPRD.SETF = /BOUTRDY
   EPRD.PRLD =  VCC


/EPROMCYC :=  ECYC4
       +  ECYC0 * ECYC1    
   EPROMCYC.CLKF = / EPCLK
   EPROMCYC.PRLD =  GND


/EPWR :=  ECYC0 * ECYC1 * ECYC2 */ECYC3 * ECYC4    
   EPWR.CLKF = / EPCLK
   EPWR.SETF = /BOUTRDY
   EPWR.PRLD =  VCC


/FLUSH  = /FLUSHI */FLUSHJ
       + /BUSIZE8D */FLUSHI    

/NADVALID  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * EPCLK * EPSENPAGE */NPAGE */ALEI
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 * ECYC3 * BUSIZE8 */EPRD
           */ALEI
       +  CFGRDY * ECYC0 * ECYC1 * ECYC2 */ECYC3 * BUSIZE8 */EPWR
           */ALEI * ECYC4
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 */ECYC3 * NPAGE * BUSIZE8
           */EPPSEN */ALEI    

/NDATAVALID  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * EPCLK * EPSENPAGE */NPAGE */ALEI
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 * ECYC3 * BUSIZE8 */EPRD
           */ALEI
       +  CFGRDY * ECYC0 * ECYC1 * ECYC2 */ECYC3 * BUSIZE8 */EPWR
           */ALEI * ECYC4
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 */ECYC3 * NPAGE * BUSIZE8
           */EPPSEN */ALEI    

/NSTROBE  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * EPCLK * EPSENPAGE */NPAGE */ALEI
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 * ECYC3 * BUSIZE8 */EPRD
           */ALEI
       +  CFGRDY * ECYC0 * ECYC1 * ECYC2 */ECYC3 * BUSIZE8 */EPWR
           */ALEI * ECYC4
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 */ECYC3 * NPAGE * BUSIZE8
           */EPPSEN */ALEI    

/NSTSVALID  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * EPCLK * EPSENPAGE */NPAGE */ALEI
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 * ECYC3 * BUSIZE8 */EPRD
           */ALEI
       +  CFGRDY * ECYC0 * ECYC1 * ECYC2 */ECYC3 * BUSIZE8 */EPWR
           */ALEI * ECYC4
       +  CFGRDY * ECYC0 * ECYC1 */ECYC2 */ECYC3 * NPAGE * BUSIZE8
           */EPPSEN */ALEI    

 RDWRPSEN :=  ECYC0 * ECYC1 */ECYC2
       +  ECYC0 * ECYC1 */ECYC3 * ECYC4    
   RDWRPSEN.CLKF = / EPCLK
   RDWRPSEN.RSTF = /BOUTRDY
   RDWRPSEN.PRLD =  GND


/TPSEN  =  CFGRDY */TPSENOUT */EPPSEN    

 WNR :=  NMHERE * SPOONRUN * TMP10K2A * WAIT0 * WAIT1 * WAIT2    
   WNR.CLKF = Gnd
   WNR.RSTF = /EPWR
   WNR.SETF =  NSTROBE
   WNR.PRLD =  GND


/ALEI := /ECYC4
       +  ECYC0 * ECYC1 */ECYC2
       +  ECYC0 * ECYC1 */ECYC3    
   ALEI.CLKF = / EPCLK
   ALEI.RSTF =  ALEIARST
   ALEI.PRLD =  GND


/ALEIARST  =  BOUTRDY */ECYC0 * ECYC4
       +  BOUTRDY */ECYC1 * ECYC4
       +  BOUTRDY * ECYC2 * ECYC3 * ECYC4    

/BUSIZE8D := Vcc    
   BUSIZE8D.CLKF = Gnd
   BUSIZE8D.RSTF = /BUSIZE8
   BUSIZE8D.SETF =  BUSIZE8
   BUSIZE8D.PRLD =  GND


/CODENDATAD0 := Vcc    
   CODENDATAD0.CLKF = Gnd
   CODENDATAD0.RSTF = /CODENDATA
   CODENDATAD0.SETF =  CODENDATA
   CODENDATAD0.PRLD =  GND


 DATALE := /ECYC0 * ECYC1 * ECYC4
       +  ECYC1 * ECYC2 * ECYC3 * ECYC4    
   DATALE.CLKF = / EPCLK
   DATALE.RSTF =  DATALEDATA
   DATALE.PRLD =  GND


/DATALEDATA  =  BOUTRDY */ECYC0 * ECYC1 * ECYC4
       +  BOUTRDY * ECYC1 * ECYC2 * ECYC3 * ECYC4    

/DATALEOUT := Vcc    
   DATALEOUT.CLKF =  ALEI
   DATALEOUT.SETF =  DATALE
   DATALEOUT.PRLD =  GND


/ECYC4 := Vcc    
   ECYC4.CLKF = Gnd
   ECYC4.RSTF = /ECYC4X * EPCLK
   ECYC4.SETF =  ECYC4X * EPCLK
   ECYC4.PRLD =  GND


/EPALEARST  =  BOUTRDY */ECYC0 * NXALE * ECYC4 */EPCLKCNT0
       +  BOUTRDY */ECYC0 */NXALE * ECYC4 */EPCLKCNT1
       +  BOUTRDY */ECYC1 * NXALE * ECYC4 */EPCLKCNT0
       +  BOUTRDY */ECYC1 */NXALE * ECYC4 */EPCLKCNT1
       +  BOUTRDY * ECYC2 * ECYC3 */NXALE * ECYC4 */EPCLKCNT1    
;Imported pterms
       +  BOUTRDY * ECYC2 * ECYC3 * NXALE * ECYC4 */EPCLKCNT0

/EPCLKCNT0 := /ALEI    
   EPCLKCNT0.CLKF =  EPCLK
   EPCLKCNT0.RSTF =  ALEIARST
   EPCLKCNT0.PRLD =  GND


/EPCLKCNT1 := /EPCLKCNT0    
   EPCLKCNT1.CLKF =  EPCLK
   EPCLKCNT1.RSTF =  ALEIARST
   EPCLKCNT1.PRLD =  GND


 FLUSHCLK  =  NPAGE * EPPSEN * EPRD * EPWR
       + /BUSIZE8 * EPPSEN * EPRD * EPWR
       + /EPSENPAGE */NPAGE * BUSIZE8 * EPRD * EPWR    

/FLUSHI := Vcc    
   FLUSHI.CLKF = Gnd
   FLUSHI.RSTF =  FLUSHIAR
   FLUSHI.SETF =  ECYC0 */ECYC1 */EPCLK
   FLUSHI.PRLD =  GND


/FLUSHIAR  =  BOUTRDY * EPCLK
       +  BOUTRDY * ECYC0 */ECYC1    

/FLUSHJ := Vcc    
   FLUSHJ.CLKF =  FLUSHCLK
   FLUSHJ.RSTF = /BUSIZE8
   FLUSHJ.SETF =  FLUSHI
   FLUSHJ.PRLD =  GND


/NCODE :=  CFGRDY * ECYC0 * ECYC1 */ECYC2 * BUSIZE8 */DATALEOUT    
   NCODE.CLKF = / EPCLK
   NCODE.RSTF =  EPCLK * NCODEAR
   NCODE.SETF =  NCODEAP
   NCODE.PRLD =  GND


/NCODEAP  =  CFGRDY * EPCLK
       +  CFGRDY * BUSIZE8    

 NCODEAR  =  CFGRDY */BUSIZE8 * NCODEARPRE
       +  CFGRDY */ECYC0 */ECYC1 */BUSIZE8 */ECYC4    

/NCODEARPRE :=  NCODEARPREAR    
   NCODEARPRE.CLKF = / EPCLK
   NCODEARPRE.RSTF =  NCODEARPREAR
   NCODEARPRE.PRLD =  GND


/NCODEARPREAR  =  ECYC0 */ECYC1 */ECYC4    

****************************  Device Pin Out ****************************

Device : XC9536-7PC44


                                  N           
                                  D           
             T                    A        E  
             P                    T        P  
             S                    A        R  
             E  E  N  W  W  W  T  V        O  
             N  P  X  A  A  A  P  A        M  
             O  C  A  I  I  I  S  L  W  V  C  
             U  L  L  T  T  T  E  I  N  C  Y  
             T  K  E  2  1  0  N  D  R  C  C  
             --------------------------------  
            /6  5  4  3  2  1  44 43 42 41 40 \
CODENDATAD | 7                             39 | SPOONRUN
     ECYC0 | 8                             38 | NADVALID
     ECYC1 | 9                             37 | NSTSVALID
       GND | 10                            36 | NSTROBE
     ECYC2 | 11         XC9536-7PC44       35 | FLUSH
     ECYC3 | 12                            34 | TMP10K2A
    ECYC4X | 13                            33 | NMHERE
  RDWRPSEN | 14                            32 | VCC
       TDI | 15                            31 | GND
       TMS | 16                            30 | TDO
       TCK | 17                            29 | EPALE
           \ 18 19 20 21 22 23 24 25 26 27 28 /
             --------------------------------  
             N  E  B  V  C  G  C  B  E  E  E  
             P  P  O  C  F  N  O  U  P  P  P  
             A  S  U  C  G  D  D  S  W  R  P  
             G  E  T     R     E  I  R  D  S  
             E  N  R     D     N  Z        E  
                P  D     Y     D  E        N  
                A  Y           A  8           
                G              T              
                E              A              


Legend : N.C. = Pin Not Connected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device Selection Mode                       : Single
Device(s) Specified                         : 9536-7PC44
Global Clock Optimization                   : ON
Global Output Enable Optimization           : INDESIGN - ON
UIM Optimization                            : INDESIGN - ON
Timing Optimization                         : ON
Ignore Tspecs                               : OFF
Create Programmable Ground Pins             : OFF
Guide File Used                             : NONE
Ignore Pin Assignments                      : OFF
Restore Pin Assignments After Optimizations : ON
Collapsing pterm limit                      : 15
Collapsing input limit                      : 36
