 
XEPLD, Version XACT-CPLD-V6.0.2a                            Xilinx Inc.
                                  Fitter Report
   Design Name: e9536ots
Fitting Status: Successful                          Date:  9-26-97, 12:16PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
e9536ots      XC9536-5PC44      29 /36  ( 80%) 73 /180 ( 40%)  29 /34  ( 85%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   14          14    |  I/O              :    28        0
Output        :   14          14    |  GCK/IO           :     1        2
Bidirectional :    0           0    |  GTS/IO           :     0        2
GCK           :    1           1    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     29          29

GLOBAL RESOURCES:

The complement of 'EPCLK' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 29 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 29 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
ALEIARST            3       6       FB2_18  STD            (b)       (b)
BUSIZE8             4       7       FB2_17  STD  SLOW 25   I/O       O
BUSIZE8D            3       1       FB1_9   STD       11   I/O       I
DATALE              3       6       FB2_12  STD       33   I/O       I
DATALEDATA          2       6       FB2_5   STD       40   GTS/I/O   (b)
DATALEOUT           2       2       FB1_5   STD       6    GCK/I/O   (b)
ECYC4               3       2       FB1_8   STD       9    I/O       I
EPALE               4       6       FB2_13  STD  SLOW 29   I/O       O
EPPSEN              2       5       FB2_14  STD  SLOW 28   I/O       O
EPRD                2       5       FB2_15  STD  SLOW 27   I/O       O
EPWR                2       6       FB2_16  STD  SLOW 26   I/O       O
FLUSH               2       3       FB2_10  STD  SLOW 35   I/O       O
FLUSHCLK            3       6       FB1_7   STD       7    GCK/I/O   (b)
FLUSHI              3       4       FB2_11  STD       34   I/O       I
FLUSHIAR            2       4       FB2_3   STD       42   GTS/I/O   (b)
FLUSHJ              3       3       FB1_6   STD       8    I/O       I
NADVALID            2       5       FB2_7   STD  FAST 38   I/O       O
NCODE               3       9       FB2_6   STD       39   GSR/I/O   (b)
NCODEAP             2       3       FB1_3   STD       5    GCK/I/O   GCK/I
NCODEAR             2       6       FB2_1   STD       1    I/O       I
NCODEARPRE          2       1       FB1_2   STD       3    I/O       I
NCODEARPREAR        1       3       FB1_1   STD       2    I/O       I
NCODEX              3       5       FB1_17  STD  FAST 24   I/O       O
NDATAVALID          2       5       FB2_4   STD  FAST 43   I/O       O
NSTROBE             2       5       FB2_9   STD  SLOW 36   I/O       O
NSTSVALID           2       5       FB2_8   STD  SLOW 37   I/O       O
RDWRPSEN            3       6       FB1_12  STD  FAST 14   I/O       O
TPSEN               2       5       FB2_2   STD  SLOW 44   I/O       O
WNR                 4       8       FB1_4   STD  SLOW 4    I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
BOUTRDY                             FB1_15            20   I/O       I
CFGRDY                              FB1_16            22   I/O       I
EA16                                FB2_11            34   I/O       I
EA17                                FB2_12            33   I/O       I
ECYC0                               FB1_6             8    I/O       I
ECYC1                               FB1_8             9    I/O       I
ECYC2                               FB1_9             11   I/O       I
ECYC3                               FB1_10            12   I/O       I
ECYC4X                              FB1_11            13   I/O       I
EPCLK                               FB1_3             5    GCK/I/O   GCK/I
EPSENPAGE                           FB1_14            19   I/O       I
NPAGE                               FB1_13            18   I/O       I
WAIT0                               FB2_1             1    I/O       I
WAIT1                               FB1_1             2    I/O       I
WAIT2                               FB1_2             3    I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          11          27          27           29         3/0       17   
FB2          18          22          22           44        11/0       17   
            ----                                -----       -----     ----- 
             29                                   73        14/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               27/9
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
NCODEARPREAR          1       0     0   4     FB1_1   STD   2   I/O     I
NCODEARPRE            2       0     0   3     FB1_2   STD   3   I/O     I
NCODEAP               2       0     0   3     FB1_3   STD   5   GCK/I/O GCK/I
WNR                   4       0     0   1     FB1_4   STD   4   I/O     O
DATALEOUT             2       0     0   3     FB1_5   STD   6   GCK/I/O (b)
FLUSHJ                3       0     0   2     FB1_6   STD   8   I/O     I
FLUSHCLK              3       0     0   2     FB1_7   STD   7   GCK/I/O (b)
ECYC4                 3       0     0   2     FB1_8   STD   9   I/O     I
BUSIZE8D              3       0     0   2     FB1_9   STD   11  I/O     I
(unused)              0       0     0   5     FB1_10        12  I/O     I
(unused)              0       0     0   5     FB1_11        13  I/O     I
RDWRPSEN              3       0     0   2     FB1_12  STD   14  I/O     O
(unused)              0       0     0   5     FB1_13        18  I/O     I
(unused)              0       0     0   5     FB1_14        19  I/O     I
(unused)              0       0     0   5     FB1_15        20  I/O     I
(unused)              0       0     0   5     FB1_16        22  I/O     I
NCODEX                3       0     0   2     FB1_17  STD   24  I/O     O
(unused)              0       0     0   5     FB1_18            (b)     

Signals Used by Logic in Function Block
  1: BOUTRDY           10: ECYC3             19: FLUSHCLK         
  2: BUSIZE8           11: ECYC4             20: FLUSHI           
  3: CFGRDY            12: ECYC4X            21: NADVALID         
  4: DATALE            13: EPALE             22: NCODE            
  5: EA16              14: EPCLK             23: NCODEARPREAR     
  6: EA17              15: EPPSEN            24: NPAGE            
  7: ECYC0             16: EPRD              25: WAIT0            
  8: ECYC1             17: EPSENPAGE         26: WAIT1            
  9: ECYC2             18: EPWR              27: WAIT2            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
NCODEARPREAR         ......XX..X............................. 3       3
NCODEARPRE           ......................X................. 1       1
NCODEAP              .XX..........X.......................... 3       3
WNR                  ....XX......X....X..X...XXX............. 8       8
DATALEOUT            ...X........X........................... 2       2
FLUSHJ               .X................XX.................... 3       3
FLUSHCLK             .X............XXXX.....X................ 6       6
ECYC4                ...........X.X.......................... 2       2
BUSIZE8D             .X...................................... 1       1
RDWRPSEN             X.....XXXXX............................. 6       6
NCODEX               .X...........X..X....X.X................ 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               22/14
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
NCODEAR               2       0     0   3     FB2_1   STD   1   I/O     I
TPSEN                 2       0     0   3     FB2_2   STD   44  I/O     O
FLUSHIAR              2       0     0   3     FB2_3   STD   42  GTS/I/O (b)
NDATAVALID            2       0     0   3     FB2_4   STD   43  I/O     O
DATALEDATA            2       0     0   3     FB2_5   STD   40  GTS/I/O (b)
NCODE                 3       0     0   2     FB2_6   STD   39  GSR/I/O (b)
NADVALID              2       0     0   3     FB2_7   STD   38  I/O     O
NSTSVALID             2       0     0   3     FB2_8   STD   37  I/O     O
NSTROBE               2       0     0   3     FB2_9   STD   36  I/O     O
FLUSH                 2       0     0   3     FB2_10  STD   35  I/O     O
FLUSHI                3       0     0   2     FB2_11  STD   34  I/O     I
DATALE                3       0     0   2     FB2_12  STD   33  I/O     I
EPALE                 4       0     0   1     FB2_13  STD   29  I/O     O
EPPSEN                2       0     0   3     FB2_14  STD   28  I/O     O
EPRD                  2       0     0   3     FB2_15  STD   27  I/O     O
EPWR                  2       0     0   3     FB2_16  STD   26  I/O     O
BUSIZE8               4       0     0   1     FB2_17  STD   25  I/O     O
ALEIARST              3       0     0   2     FB2_18  STD       (b)     (b)

Signals Used by Logic in Function Block
  1: ALEIARST           9: ECYC1             16: FLUSHIAR         
  2: BOUTRDY           10: ECYC2             17: FLUSHJ           
  3: BUSIZE8           11: ECYC3             18: NCODEAP          
  4: BUSIZE8D          12: ECYC4             19: NCODEAR          
  5: CFGRDY            13: EPALE             20: NCODEARPRE       
  6: DATALEDATA        14: EPCLK             21: NDATAVALID       
  7: DATALEOUT         15: FLUSHI            22: RDWRPSEN         
  8: ECYC0            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
NCODEAR              ..X.X..XX..X.......X.................... 6       6
TPSEN                .X.....XXXX............................. 5       5
FLUSHIAR             .X.....XX....X.......................... 4       4
NDATAVALID           ..X.X.......XX.......X.................. 5       5
DATALEDATA           .X.....XXXXX............................ 6       6
NCODE                ..X.X.XXXX...X...XX..................... 9       9
NADVALID             ..X.X.......XX.......X.................. 5       5
NSTSVALID            ..X.X.......XX.......X.................. 5       5
NSTROBE              ..X.X.......XX.......X.................. 5       5
FLUSH                ...X..........X.X....................... 3       3
FLUSHI               .......XX....X.X........................ 4       4
DATALE               .....X.XXXXX............................ 6       6
EPALE                X......XXXXX............................ 6       6
EPPSEN               .X.....XXXX............................. 5       5
EPRD                 .X.....XXXX............................. 5       5
EPWR                 .X.....XXXXX............................ 6       6
BUSIZE8              ...X...XXXXX........X................... 7       7
ALEIARST             .X.....XXXXX............................ 6       6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/BUSIZE8 := /ECYC1 */ECYC4
       + /ECYC0 */ECYC4
       +  ECYC2 * ECYC3 */BUSIZE8D */ECYC4    
   BUSIZE8.CLKF = / EPCLK
   BUSIZE8.SETF =  ECYC0 * ECYC1 * ECYC2 * ECYC3 * NDATAVALID */ECYC4
   BUSIZE8.PRLD =  GND


/EPALE := /ECYC4
       +  ECYC0 * ECYC1 */ECYC3
       +  ECYC0 * ECYC1 */ECYC2    
   EPALE.CLKF = / EPCLK
   EPALE.RSTF =  ALEIARST
   EPALE.PRLD =  GND


/EPPSEN :=  ECYC0 * ECYC1 */ECYC2 */ECYC3    
   EPPSEN.CLKF = / EPCLK
   EPPSEN.SETF = /BOUTRDY
   EPPSEN.PRLD =  VCC


/EPRD :=  ECYC0 * ECYC1 */ECYC2 * ECYC3    
   EPRD.CLKF = / EPCLK
   EPRD.SETF = /BOUTRDY
   EPRD.PRLD =  VCC


/EPWR :=  ECYC0 * ECYC1 * ECYC2 */ECYC3 * ECYC4    
   EPWR.CLKF = / EPCLK
   EPWR.SETF = /BOUTRDY
   EPWR.PRLD =  VCC


/FLUSH  = /FLUSHI */FLUSHJ
       + /BUSIZE8D */FLUSHI    

/NADVALID  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * BUSIZE8 */EPALE * RDWRPSEN    

/NCODEX  = /BUSIZE8 */NCODE
       +  NPAGE */NCODE
       +  EPCLK * EPSENPAGE */NPAGE * BUSIZE8    

/NDATAVALID  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * BUSIZE8 */EPALE * RDWRPSEN    

/NSTROBE  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * BUSIZE8 */EPALE * RDWRPSEN    

/NSTSVALID  =  CFGRDY * EPCLK */BUSIZE8
       +  CFGRDY * BUSIZE8 */EPALE * RDWRPSEN    

 RDWRPSEN :=  ECYC0 * ECYC1 */ECYC2
       +  ECYC0 * ECYC1 */ECYC3 * ECYC4    
   RDWRPSEN.CLKF = / EPCLK
   RDWRPSEN.RSTF = /BOUTRDY
   RDWRPSEN.PRLD =  GND


/TPSEN :=  ECYC0 * ECYC1 */ECYC2 */ECYC3    
   TPSEN.CLKF = / EPCLK
   TPSEN.SETF = /BOUTRDY
   TPSEN.PRLD =  VCC


 WNR :=  EA16 * EA17 * WAIT0 * WAIT1 * WAIT2 * EPALE    
   WNR.CLKF = Gnd
   WNR.RSTF = /EPWR
   WNR.SETF =  NADVALID
   WNR.PRLD =  GND


/ALEIARST  =  BOUTRDY */ECYC1 * ECYC4
       +  BOUTRDY */ECYC0 * ECYC4
       +  BOUTRDY * ECYC2 * ECYC3 * ECYC4    

/BUSIZE8D := Vcc    
   BUSIZE8D.CLKF = Gnd
   BUSIZE8D.RSTF = /BUSIZE8
   BUSIZE8D.SETF =  BUSIZE8
   BUSIZE8D.PRLD =  GND


 DATALE := /ECYC0 * ECYC1 * ECYC4
       +  ECYC1 * ECYC2 * ECYC3 * ECYC4    
   DATALE.CLKF = / EPCLK
   DATALE.RSTF =  DATALEDATA
   DATALE.PRLD =  GND


/DATALEDATA  =  BOUTRDY */ECYC0 * ECYC1 * ECYC4
       +  BOUTRDY * ECYC1 * ECYC2 * ECYC3 * ECYC4    

/DATALEOUT := Vcc    
   DATALEOUT.CLKF =  EPALE
   DATALEOUT.SETF =  DATALE
   DATALEOUT.PRLD =  GND


/ECYC4 := Vcc    
   ECYC4.CLKF = Gnd
   ECYC4.RSTF = /ECYC4X * EPCLK
   ECYC4.SETF =  ECYC4X * EPCLK
   ECYC4.PRLD =  GND


 FLUSHCLK  = /BUSIZE8 * EPPSEN * EPRD * EPWR
       +  NPAGE * EPPSEN * EPRD * EPWR
       + /EPSENPAGE */NPAGE * BUSIZE8 * EPRD * EPWR    

/FLUSHI := Vcc    
   FLUSHI.CLKF = Gnd
   FLUSHI.RSTF =  FLUSHIAR
   FLUSHI.SETF =  ECYC0 */ECYC1 */EPCLK
   FLUSHI.PRLD =  GND


/FLUSHIAR  =  BOUTRDY * EPCLK
       +  BOUTRDY * ECYC0 */ECYC1    

/FLUSHJ := Vcc    
   FLUSHJ.CLKF =  FLUSHCLK
   FLUSHJ.RSTF = /BUSIZE8
   FLUSHJ.SETF =  FLUSHI
   FLUSHJ.PRLD =  GND


/NCODE :=  CFGRDY * ECYC0 * ECYC1 */ECYC2 * BUSIZE8 */DATALEOUT    
   NCODE.CLKF = / EPCLK
   NCODE.RSTF =  EPCLK * NCODEAR
   NCODE.SETF =  NCODEAP
   NCODE.PRLD =  GND


/NCODEAP  =  CFGRDY * EPCLK
       +  CFGRDY * BUSIZE8    

 NCODEAR  =  CFGRDY */BUSIZE8 * NCODEARPRE
       +  CFGRDY */ECYC0 */ECYC1 */BUSIZE8 */ECYC4    

/NCODEARPRE :=  NCODEARPREAR    
   NCODEARPRE.CLKF = / EPCLK
   NCODEARPRE.RSTF =  NCODEARPREAR
   NCODEARPRE.PRLD =  GND


/NCODEARPREAR  =  ECYC0 */ECYC1 */ECYC4    

****************************  Device Pin Out ****************************

Device : XC9536-5PC44


                                N           
                                D           
                                A           
                                T           
                                A           
              E     W  W  W  T  V           
           N  P     A  A  A  P  A  N     N  
           .  C  W  I  I  I  S  L  .  V  .  
           C  L  N  T  T  T  E  I  C  C  C  
           .  K  R  2  1  0  N  D  .  C  .  
           --------------------------------  
          /6  5  4  3  2  1  44 43 42 41 40 \
    N.C. | 7                             39 | N.C.
   ECYC0 | 8                             38 | NADVALID
   ECYC1 | 9                             37 | NSTSVALID
     GND | 10                            36 | NSTROBE
   ECYC2 | 11         XC9536-5PC44       35 | FLUSH
   ECYC3 | 12                            34 | EA16
  ECYC4X | 13                            33 | EA17
RDWRPSEN | 14                            32 | VCC
     TDI | 15                            31 | GND
     TMS | 16                            30 | TDO
     TCK | 17                            29 | EPALE
         \ 18 19 20 21 22 23 24 25 26 27 28 /
           --------------------------------  
           N  E  B  V  C  G  N  B  E  E  E  
           P  P  O  C  F  N  C  U  P  P  P  
           A  S  U  C  G  D  O  S  W  R  P  
           G  E  T     R     D  I  R  D  S  
           E  N  R     D     E  Z        E  
              P  D     Y     X  E        N  
              A  Y              8           
              G                             
              E                             


Legend : N.C. = Pin Not Connected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device Selection Mode                       : Single
Device(s) Specified                         : 9536-5PC44
Global Clock Optimization                   : INDESIGN - ON
Global Output Enable Optimization           : INDESIGN - ON
UIM Optimization                            : INDESIGN - ON
Timing Optimization                         : OFF
Ignore Tspecs                               : OFF
Create Programmable Ground Pins             : OFF
Guide File Used                             : NONE
Ignore Pin Assignments                      : OFF
Restore Pin Assignments After Optimizations : ON
Collapsing pterm limit                      : 15
Collapsing input limit                      : 36
