 
XEPLD, Version XACT-CPLD-V6.0.2a                            Xilinx Inc.
                                  Fitter Report
   Design Name: e953615
Fitting Status: Successful                          Date:  2-12-98,  9:32AM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
e953615       XC9536-7PC44      15 /36  ( 41%) 33 /180 ( 18%)  30 /34  ( 88%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   17          17    |  I/O              :    24        4
Output        :   13          13    |  GCK/IO           :     3        0
Bidirectional :    0           0    |  GTS/IO           :     2        0
GCK           :    0           0    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     30          30

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 15 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 15 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
CPDEN               1       2       FB2_16  STD  SLOW 26   I/O       O
EPCLKD              3       1       FB2_2   STD       44   I/O       I
EPCLKD1             3       1       FB2_1   STD       1    I/O       I
LEEPAH              1       3       FB2_9   STD  SLOW 36   I/O       O
LEEPAL              3       5       FB2_10  STD  SLOW 35   I/O       O
LEEPROMAH           1       4       FB2_7   STD  SLOW 38   I/O       O
NENINT              1       2       FB2_11  STD  SLOW 34   I/O       O
NOEEPAH             1       3       FB2_12  STD  SLOW 33   I/O       O
NOEEPAL             1       2       FB1_5   STD  SLOW 6    GCK/I/O   O
NOEEPDH             1       6       FB1_3   STD  SLOW 5    GCK/I/O   O
NOEEPDL             7       12      FB1_17  STD  SLOW 24   I/O       O
NOEEPROMAH          1       3       FB2_8   STD  SLOW 37   I/O       O
PCHANGE             1       2       FB2_13  STD  SLOW 29   I/O       O
RWEPD               6       9       FB2_5   STD  SLOW 40   GTS/I/O   O
TPSENOUT            2       5       FB2_3   STD  SLOW 42   GTS/I/O   O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
BUSIZE                              FB1_6             8    I/O       I
CANTRIG                             FB2_4             43   I/O       I
CFGRDY                              FB1_2             3    I/O       I
CPCSX                               FB2_14            28   I/O       I
CPRST                               FB2_1             1    I/O       I
CPURUN                              FB2_2             44   I/O       I
EPALE                               FB1_14            19   I/O       I
EPCLK                               FB1_1             2    I/O       I
EPPSEN                              FB1_13            18   I/O       I
EPRD                                FB1_7             7    GCK/I/O   I
EPROMCYC                            FB1_4             4    I/O       I
EPWR                                FB1_15            20   I/O       I
ISOEP                               FB1_8             9    I/O       I
MOVXRMAPT                           FB2_15            27   I/O       I
NMHERE                              FB1_10            12   I/O       I
NPSWAP                              FB1_11            13   I/O       I
SPOONRUN                            FB2_6             39   GSR/I/O   I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           3          12          12            9         3/0       17   
FB2          12          18          18           24        10/0       17   
            ----                                -----       -----     ----- 
             15                                   33        13/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               12/24
Number of signals used by logic mapping into function block:  12
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
(unused)              0       0     0   5     FB1_1         2   I/O     I
(unused)              0       0     0   5     FB1_2         3   I/O     I
NOEEPDH               1       0     0   4     FB1_3   STD   5   GCK/I/O O
(unused)              0       0     0   5     FB1_4         4   I/O     I
NOEEPAL               1       0     0   4     FB1_5   STD   6   GCK/I/O O
(unused)              0       0     0   5     FB1_6         8   I/O     I
(unused)              0       0     0   5     FB1_7         7   GCK/I/O I
(unused)              0       0     0   5     FB1_8         9   I/O     I
(unused)              0       0     0   5     FB1_9         11  I/O     
(unused)              0       0     0   5     FB1_10        12  I/O     I
(unused)              0       0     0   5     FB1_11        13  I/O     I
(unused)              0       0     0   5     FB1_12        14  I/O     
(unused)              0       0     0   5     FB1_13        18  I/O     I
(unused)              0       0     0   5     FB1_14        19  I/O     I
(unused)              0       0     0   5     FB1_15        20  I/O     I
(unused)              0       0   \/1   4     FB1_16        22  I/O     (b)
NOEEPDL               7       2<-   0   0     FB1_17  STD   24  I/O     O
(unused)              0       0   /\1   4     FB1_18            (b)     (b)

Signals Used by Logic in Function Block
  1: BUSIZE             5: CPURUN             9: EPWR             
  2: CANTRIG            6: EPCLK             10: ISOEP            
  3: CFGRDY             7: EPPSEN            11: NMHERE           
  4: CPRST              8: EPRD              12: SPOONRUN         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
NOEEPDH              X.XX.X...X.X............................ 6       6
NOEEPAL              ...X.....X.............................. 2       2
NOEEPDL              XXXXXXXXXXXX............................ 12      12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
EPCLKD1               3       0     0   2     FB2_1   STD   1   I/O     I
EPCLKD                3       0     0   2     FB2_2   STD   44  I/O     I
TPSENOUT              2       0     0   3     FB2_3   STD   42  GTS/I/O O
(unused)              0       0   \/1   4     FB2_4         43  I/O     I
RWEPD                 6       1<-   0   0     FB2_5   STD   40  GTS/I/O O
(unused)              0       0     0   5     FB2_6         39  GSR/I/O I
LEEPROMAH             1       0     0   4     FB2_7   STD   38  I/O     O
NOEEPROMAH            1       0     0   4     FB2_8   STD   37  I/O     O
LEEPAH                1       0     0   4     FB2_9   STD   36  I/O     O
LEEPAL                3       0     0   2     FB2_10  STD   35  I/O     O
NENINT                1       0     0   4     FB2_11  STD   34  I/O     O
NOEEPAH               1       0     0   4     FB2_12  STD   33  I/O     O
PCHANGE               1       0     0   4     FB2_13  STD   29  I/O     O
(unused)              0       0     0   5     FB2_14        28  I/O     I
(unused)              0       0     0   5     FB2_15        27  I/O     I
CPDEN                 1       0     0   4     FB2_16  STD   26  I/O     O
(unused)              0       0     0   5     FB2_17        25  I/O     
(unused)              0       0     0   5     FB2_18            (b)     

Signals Used by Logic in Function Block
  1: BUSIZE             7: EPALE             13: EPROMCYC         
  2: CANTRIG            8: EPCLK             14: ISOEP            
  3: CFGRDY             9: EPCLKD            15: MOVXRMAPT        
  4: CPCSX             10: EPCLKD1           16: NMHERE           
  5: CPRST             11: EPPSEN            17: NPSWAP           
  6: CPURUN            12: EPRD              18: SPOONRUN         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
EPCLKD1              ........X............................... 1       1
EPCLKD               .......X................................ 1       1
TPSENOUT             .XX..X.........X.X...................... 5       5
RWEPD                XX...X.X..XX..XX.X...................... 9       9
LEEPROMAH            .......XXX..X........................... 4       4
NOEEPROMAH           ....X.......XX.......................... 3       3
LEEPAH               X.....XX................................ 3       3
LEEPAL               X.....XXX.......X....................... 5       5
NENINT               ..X....X................................ 2       2
NOEEPAH              ....X.......XX.......................... 3       3
PCHANGE              X...............X....................... 2       2
CPDEN                ...X.........X.......................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/CPDEN  = /CPCSX * ISOEP    

 LEEPAH  =  BUSIZE * EPALE */EPCLK    

 LEEPAL  =  BUSIZE */EPCLK */NPSWAP
       + /BUSIZE */EPCLK */EPCLKD
       +  BUSIZE * EPALE * NPSWAP    

 LEEPROMAH  = /EPCLK * EPROMCYC */EPCLKD */EPCLKD1    

/NENINT  =  CFGRDY * EPCLK    

/NOEEPAH  = /CPRST */EPROMCYC */ISOEP    

/NOEEPAL  = /CPRST */ISOEP    

/NOEEPDH  = /BUSIZE * CFGRDY */CPRST * EPCLK */ISOEP */SPOONRUN    

 NOEEPDL  =  CPRST
       +  ISOEP
       + /CFGRDY
       +  SPOONRUN
       + /BUSIZE */EPCLK    
;Imported pterms
       +  BUSIZE * CANTRIG */CPURUN * NMHERE    
;Imported pterms
       +  BUSIZE * EPPSEN * EPRD * EPWR    

/NOEEPROMAH  = /CPRST * EPROMCYC */ISOEP    

 PCHANGE  =  BUSIZE */NPSWAP    

 RWEPD  = /BUSIZE */EPCLK
       +  BUSIZE * CPURUN * NMHERE
       +  BUSIZE * CANTRIG * NMHERE
       +  BUSIZE */CPURUN * SPOONRUN
       +  BUSIZE * CPURUN * MOVXRMAPT    
;Imported pterms
       +  BUSIZE * EPPSEN * EPRD    

/TPSENOUT  =  CFGRDY * CPURUN * NMHERE
       +  CANTRIG * CFGRDY * NMHERE */SPOONRUN    

/EPCLKD := Vcc    
   EPCLKD.CLKF = Gnd
   EPCLKD.RSTF = /EPCLK
   EPCLKD.SETF =  EPCLK
   EPCLKD.PRLD =  GND


/EPCLKD1 := Vcc    
   EPCLKD1.CLKF = Gnd
   EPCLKD1.RSTF = /EPCLKD
   EPCLKD1.SETF =  EPCLKD
   EPCLKD1.PRLD =  GND


****************************  Device Pin Out ****************************

Device : XC9536-7PC44


               E                 T        
         N  N  P              C  P        
         O  O  R  C        C  A  S        
         E  E  O  F  E  C  P  N  E     R  
         E  E  M  G  P  P  U  T  N     W  
         P  P  C  R  C  R  R  R  O  V  E  
         A  D  Y  D  L  S  U  I  U  C  P  
         L  H  C  Y  K  T  N  G  T  C  D  
         --------------------------------  
        /6  5  4  3  2  1  44 43 42 41 40 \
  EPRD | 7                             39 | SPOONRUN
BUSIZE | 8                             38 | LEEPROMAH
 ISOEP | 9                             37 | NOEEPROMAH
   GND | 10                            36 | LEEPAH
  N.C. | 11         XC9536-7PC44       35 | LEEPAL
NMHERE | 12                            34 | NENINT
NPSWAP | 13                            33 | NOEEPAH
  N.C. | 14                            32 | VCC
   TDI | 15                            31 | GND
   TMS | 16                            30 | TDO
   TCK | 17                            29 | PCHANGE
       \ 18 19 20 21 22 23 24 25 26 27 28 /
         --------------------------------  
         E  E  E  V  N  G  N  N  C  M  C  
         P  P  P  C  .  N  O  .  P  O  P  
         P  A  W  C  C  D  E  C  D  V  C  
         S  L  R     .     E  .  E  X  S  
         E  E              P     N  R  X  
         N                 D        M     
                           L        A     
                                    P     
                                    T     


Legend : N.C. = Pin Not Connected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device Selection Mode                       : Single
Device(s) Specified                         : 9536-7PC44
Global Clock Optimization                   : INDESIGN - ON
Global Output Enable Optimization           : INDESIGN - ON
UIM Optimization                            : INDESIGN - ON
Timing Optimization                         : ON
Ignore Tspecs                               : OFF
Create Programmable Ground Pins             : OFF
Guide File Used                             : NONE
Ignore Pin Assignments                      : OFF
Restore Pin Assignments After Optimizations : ON
Collapsing pterm limit                      : 15
Collapsing input limit                      : 36
