 
XEPLD, Version XACT-CPLD-V6.0.0                             Xilinx Inc.
                                  Fitter Report
   Design Name: cpio
Fitting Status: Successful                          Date: 12- 9-96,  4:32PM

****************************  Resource Summary  ****************************

Design        Device            Macrocells     Product Terms   Pins            
Name          Used              Used           Used            Used            
cpio          XC9536-7PC44      25 /36  ( 69%) 67 /180 ( 37%)  33 /34  ( 97%) 

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :   17          17    |  I/O              :    28        0
Output        :   15          15    |  GCK/IO           :     3        0
Bidirectional :    1           1    |  GTS/IO           :     1        1
GCK           :    0           0    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     33          33

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 25 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 25 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
ARDY                5       7       FB2_16  STD  SLOW 26   I/O       O
CPD7                4       10      FB1_15  STD  SLOW 20   I/O       I/O
CS                  3       10      FB2_6   STD  SLOW 39   GSR/I/O   O
FCLK1A              4       5       FB2_15  STD  FAST 27   I/O       O
FCLK1B              3       5       FB2_17  STD  FAST 25   I/O       O
FCLKSEL0            3       10      FB2_12  STD       33   I/O       I
FCLKSEL1            3       10      FB2_11  STD       34   I/O       I
G0_SV0              5       8       FB2_18  STD            (b)       (b)
G0_SV1              4       7       FB2_14  STD       28   I/O       I
G0_SV2              4       7       FB2_13  STD       29   I/O       I
LA0                 2       3       FB2_7   STD  FAST 38   I/O       O
LA0A1NOE            3       10      FB1_8   STD  SLOW 9    I/O       O
LA1                 1       2       FB2_8   STD  FAST 37   I/O       O
NRDP4               1       6       FB1_17  STD  SLOW 24   I/O       O
NRDPXMN             2       5       FB1_16  STD  SLOW 22   I/O       O
NWRMN               2       7       FB1_9   STD  FAST 11   I/O       O
NWRP0               1       6       FB1_5   STD  FAST 6    GCK/I/O   O
NWRP1               1       6       FB1_4   STD  FAST 4    I/O       O
NWRP2               1       6       FB1_10  STD  FAST 12   I/O       O
NWRP3               1       6       FB1_11  STD  FAST 13   I/O       O
NWRP4               2       7       FB1_12  STD  FAST 14   I/O       O
WB0                 3       10      FB2_10  STD       35   I/O       I
WB1                 3       10      FB2_9   STD       36   I/O       I
WB2                 3       10      FB2_5   STD       40   GTS/I/O   (b)
WRITEBC             3       10      FB1_18  STD            (b)       (b)

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
CPA2                                FB1_6             8    I/O       I
CPA3                                FB2_14            28   I/O       I
CPA4                                FB2_3             42   GTS/I/O   I
CPA5                                FB1_7             7    GCK/I/O   I
CPA6                                FB1_2             3    I/O       I
CPCLK                               FB2_9             36   I/O       I
DONEP4                              FB2_10            35   I/O       I
DOUT                                FB2_11            34   I/O       I
FCLK1                               FB1_1             2    I/O       I
FFCLK                               FB2_12            33   I/O       I
NBEN0                               FB2_1             1    I/O       I
NBEN1                               FB2_2             44   I/O       I
NBEN2                               FB2_4             43   I/O       I
NCPRD                               FB1_3             5    GCK/I/O   I
NCPWR                               FB1_14            19   I/O       I
NPCS6                               FB1_13            18   I/O       I
RDYNBSYP4                           FB2_13            29   I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          11          15          15           21         9/1       17   
FB2          14          23          23           46         6/0       17   
            ----                                -----       -----     ----- 
             25                                   67        15/1       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               15/21
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
(unused)              0       0     0   5     FB1_1         2   I/O     I
(unused)              0       0     0   5     FB1_2         3   I/O     I
(unused)              0       0     0   5     FB1_3         5   GCK/I/O I
NWRP1                 1       0     0   4     FB1_4   STD   4   I/O     O
NWRP0                 1       0     0   4     FB1_5   STD   6   GCK/I/O O
(unused)              0       0     0   5     FB1_6         8   I/O     I
(unused)              0       0     0   5     FB1_7         7   GCK/I/O I
LA0A1NOE              3       0     0   2     FB1_8   STD   9   I/O     O
NWRMN                 2       0     0   3     FB1_9   STD   11  I/O     O
NWRP2                 1       0     0   4     FB1_10  STD   12  I/O     O
NWRP3                 1       0     0   4     FB1_11  STD   13  I/O     O
NWRP4                 2       0     0   3     FB1_12  STD   14  I/O     O
(unused)              0       0     0   5     FB1_13        18  I/O     I
(unused)              0       0     0   5     FB1_14        19  I/O     I
CPD7                  4       0     0   1     FB1_15  STD   20  I/O     I/O
NRDPXMN               2       0     0   3     FB1_16  STD   22  I/O     O
NRDP4                 1       0     0   4     FB1_17  STD   24  I/O     O
WRITEBC               3       0     0   2     FB1_18  STD       (b)     (b)

Signals Used by Logic in Function Block
  1: CPA2               6: CPCLK             11: NCPRD            
  2: CPA3               7: CPD7.PIN          12: NCPWR            
  3: CPA4               8: DONEP4            13: NPCS6            
  4: CPA5               9: DOUT              14: RDYNBSYP4        
  5: CPA6              10: LA0A1NOE          15: WRITEBC          

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
NWRP1                .XXXX......XX........................... 6       6
NWRP0                .XXXX......XX........................... 6       6
LA0A1NOE             XXXXXXX..X.XX........................... 10      10
NWRMN                .XXXX......XX.X......................... 7       7
NWRP2                .XXXX......XX........................... 6       6
NWRP3                .XXXX......XX........................... 6       6
NWRP4                .XXXX......XX.X......................... 7       7
CPD7                 XXXXX..XX..XXX.......................... 10      10
NRDPXMN              ..XXX.....X.X........................... 5       5
NRDP4                .XXXX.....X.X........................... 6       6
WRITEBC              XXXXXXX....XX.X......................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               23/13
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #  Type    Use
(unused)              0       0     0   5     FB2_1         1   I/O     I
(unused)              0       0     0   5     FB2_2         44  I/O     I
(unused)              0       0     0   5     FB2_3         42  GTS/I/O I
(unused)              0       0     0   5     FB2_4         43  I/O     I
WB2                   3       0     0   2     FB2_5   STD   40  GTS/I/O (b)
CS                    3       0     0   2     FB2_6   STD   39  GSR/I/O O
LA0                   2       0     0   3     FB2_7   STD   38  I/O     O
LA1                   1       0     0   4     FB2_8   STD   37  I/O     O
WB1                   3       0     0   2     FB2_9   STD   36  I/O     I
WB0                   3       0     0   2     FB2_10  STD   35  I/O     I
FCLKSEL1              3       0     0   2     FB2_11  STD   34  I/O     I
FCLKSEL0              3       0     0   2     FB2_12  STD   33  I/O     I
G0_SV2                4       0     0   1     FB2_13  STD   29  I/O     I
G0_SV1                4       0     0   1     FB2_14  STD   28  I/O     I
FCLK1A                4       0     0   1     FB2_15  STD   27  I/O     O
ARDY                  5       0     0   0     FB2_16  STD   26  I/O     O
FCLK1B                3       0     0   2     FB2_17  STD   25  I/O     O
G0_SV0                5       0     0   0     FB2_18  STD       (b)     (b)

Signals Used by Logic in Function Block
  1: CPA2               9: FCLK1             17: NBEN1            
  2: CPA3              10: FCLKSEL0          18: NBEN2            
  3: CPA4              11: FCLKSEL1          19: NCPWR            
  4: CPA5              12: FFCLK             20: NPCS6            
  5: CPA6              13: G0_SV0            21: WB0              
  6: CPCLK             14: G0_SV1            22: WB1              
  7: CPD7.PIN          15: G0_SV2            23: WB2              
  8: CS                16: NBEN0            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
WB2                  XXXXXXX...........XX..X................. 10      10
CS                   XXXXXXXX..........XX.................... 10      10
LA0                  ...............XXX...................... 3       3
LA1                  ...............XX....................... 2       2
WB1                  XXXXXXX...........XX.X.................. 10      10
WB0                  XXXXXXX...........XXX................... 10      10
FCLKSEL1             XXXXXXX...X.......XX.................... 10      10
FCLKSEL0             XXXXXXX..X........XX.................... 10      10
G0_SV2               .....X......XXX...X..XX................. 7       7
G0_SV1               .....X......XXX...X..XX................. 7       7
FCLK1A               .....X..XXXX............................ 5       5
ARDY                 .....X......XXX.....XXX................. 7       7
FCLK1B               .....X..XXXX............................ 5       5
G0_SV0               .....X......XXX...X.XXX................. 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X - Signal used as input to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

 CPD7  =  CPA2 * CPA3 * CPA4 * CPA5 */CPA6 * DOUT
       +  CPA2 */CPA3 * CPA4 * CPA5 */CPA6 * DONEP4
       + /CPA2 */CPA3 * CPA4 * CPA5 */CPA6 * RDYNBSYP4    
   CPD7.TRST =  CPA4 * CPA5 */CPA6 * NCPWR */NPCS6

 ARDY :=  G0_SV0 */G0_SV1 */G0_SV2
       + /G0_SV0 * G0_SV1 */G0_SV2
       + /G0_SV0 */G0_SV2 * WB0 * WB1 * WB2
       + /G0_SV0 */G0_SV2 */WB0 */WB1 */WB2    
   ARDY.CLKF =  CPCLK
   ARDY.PRLD =  GND


 CS.T  =  CPA2 * CPA3 */CPA4 * CPA5 * CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */CS
       +  CPA2 * CPA3 */CPA4 * CPA5 * CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * CS    
   CS.CLKF =  CPCLK
   CS.PRLD =  GND


/FCLK1A  = /CPCLK * FCLKSEL0 */FCLKSEL1
       + /CPCLK */FCLKSEL0 * FCLKSEL1
       + /FFCLK * FCLKSEL0 * FCLKSEL1
       + /FCLK1 */FCLKSEL0 */FCLKSEL1    

/FCLK1B  = /FCLK1 */FCLKSEL1
       + /CPCLK */FCLKSEL0 * FCLKSEL1
       + /FFCLK * FCLKSEL0 * FCLKSEL1    

/LA0  = /NBEN0
       +  NBEN1 */NBEN2    

 LA0A1NOE.T  =  CPA2 * CPA3 * CPA4 * CPA5 */CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */LA0A1NOE
       +  CPA2 * CPA3 * CPA4 * CPA5 */CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * LA0A1NOE    
   LA0A1NOE.CLKF =  CPCLK
   LA0A1NOE.PRLD =  GND


 LA1  =  NBEN0 * NBEN1    

/NRDP4  = /CPA3 */CPA4 * CPA5 */CPA6 */NCPRD */NPCS6    

/NRDPXMN  = /CPA4 */CPA6 */NCPRD */NPCS6
       + /CPA5 */CPA6 */NCPRD */NPCS6    

/NWRMN  = /CPA5 */CPA6 */NCPWR */NPCS6 * WRITEBC
       +  CPA3 */CPA4 * CPA5 */CPA6 */NCPWR */NPCS6 */WRITEBC    

/NWRP0  = /CPA3 */CPA4 */CPA5 */CPA6 */NCPWR */NPCS6    

/NWRP1  =  CPA3 */CPA4 */CPA5 */CPA6 */NCPWR */NPCS6    

/NWRP2  = /CPA3 * CPA4 */CPA5 */CPA6 */NCPWR */NPCS6    

/NWRP3  =  CPA3 * CPA4 */CPA5 */CPA6 */NCPWR */NPCS6    

/NWRP4  = /CPA5 */CPA6 */NCPWR */NPCS6 * WRITEBC
       + /CPA3 */CPA4 * CPA5 */CPA6 */NCPWR */NPCS6 */WRITEBC    

 FCLKSEL0.T  = /CPA2 */CPA3 * CPA4 * CPA5 */CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */FCLKSEL0
       + /CPA2 */CPA3 * CPA4 * CPA5 */CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * FCLKSEL0    
   FCLKSEL0.CLKF =  CPCLK
   FCLKSEL0.PRLD =  GND


 FCLKSEL1.T  =  CPA2 */CPA3 * CPA4 * CPA5 */CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */FCLKSEL1
       +  CPA2 */CPA3 * CPA4 * CPA5 */CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * FCLKSEL1    
   FCLKSEL1.CLKF =  CPCLK
   FCLKSEL1.PRLD =  GND


 G0_SV0 := /G0_SV0 * G0_SV1
       + /G0_SV0 * G0_SV2
       + /NCPWR */G0_SV0 * WB0 * WB1 */WB2
       + /NCPWR */G0_SV0 * WB0 */WB1 * WB2    
   G0_SV0.CLKF =  CPCLK
   G0_SV0.PRLD =  GND


 G0_SV1.T  =  G0_SV0 */G0_SV2
       + /G0_SV0 * G0_SV1 * G0_SV2
       + /NCPWR */G0_SV1 */G0_SV2 */WB1 * WB2    
   G0_SV1.CLKF =  CPCLK
   G0_SV1.PRLD =  GND


 G0_SV2.T  = /G0_SV0 */G0_SV1 * G0_SV2
       + /NCPWR */G0_SV0 */G0_SV1 * WB1 */WB2
       + /NCPWR */G0_SV0 */G0_SV1 */WB1 * WB2    
   G0_SV2.CLKF =  CPCLK
   G0_SV2.PRLD =  GND


 WB0.T  = /CPA2 */CPA3 */CPA4 * CPA5 * CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */WB0
       + /CPA2 */CPA3 */CPA4 * CPA5 * CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * WB0    
   WB0.CLKF =  CPCLK
   WB0.PRLD =  GND


 WB1.T  =  CPA2 */CPA3 */CPA4 * CPA5 * CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */WB1
       +  CPA2 */CPA3 */CPA4 * CPA5 * CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * WB1    
   WB1.CLKF =  CPCLK
   WB1.PRLD =  GND


 WB2.T  = /CPA2 * CPA3 */CPA4 * CPA5 * CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */WB2
       + /CPA2 * CPA3 */CPA4 * CPA5 * CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * WB2    
   WB2.CLKF =  CPCLK
   WB2.PRLD =  GND


 WRITEBC.T  = /CPA2 * CPA3 * CPA4 * CPA5 */CPA6 * CPD7.PIN */NCPWR
           */NPCS6 */WRITEBC
       + /CPA2 * CPA3 * CPA4 * CPA5 */CPA6 */CPD7.PIN */NCPWR
           */NPCS6 * WRITEBC    
   WRITEBC.CLKF =  CPCLK
   WRITEBC.PRLD =  GND


****************************  Device Pin Out ****************************

Device : XC9536-7PC44


           N  N  N     F  N  N  N           
           W  C  W  C  C  B  B  B  C     N  
           R  P  R  P  L  E  E  E  P  V  .  
           P  R  P  A  K  N  N  N  A  C  C  
           0  D  1  6  1  0  1  2  4  C  .  
           --------------------------------  
          /6  5  4  3  2  1  44 43 42 41 40 \
    CPA5 | 7                             39 | CS
    CPA2 | 8                             38 | LA0
LA0A1NOE | 9                             37 | LA1
     GND | 10                            36 | CPCLK
   NWRMN | 11         XC9536-7PC44       35 | DONEP4
   NWRP2 | 12                            34 | DOUT
   NWRP3 | 13                            33 | FFCLK
   NWRP4 | 14                            32 | VCC
     TDI | 15                            31 | GND
     TMS | 16                            30 | TDO
     TCK | 17                            29 | RDYNBSYP4
         \ 18 19 20 21 22 23 24 25 26 27 28 /
           --------------------------------  
           N  N  C  V  N  G  N  F  A  F  C  
           P  C  P  C  R  N  R  C  R  C  P  
           C  P  D  C  D  D  D  L  D  L  A  
           S  W  7     P     P  K  Y  K  3  
           6  R        X     4  1     1     
                       M        B     A     
                       N                    


Legend : N.C. = Pin Not Connected
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device Selection Mode                       : Single
Device(s) Specified                         : 9536-7PC44
Global Clock Optimization                   : INDESIGN - ON
Global Output Enable Optimization           : INDESIGN - ON
UIM Optimization                            : INDESIGN - ON
Timing Optimization                         : OFF
Ignore Tspecs                               : OFF
Create Programmable Ground Pins             : OFF
Guide File Used                             : NONE
Ignore Pin Assignments                      : OFF
Restore Pin Assignments After Optimizations : ON
Collapsing pterm limit                      : 15
Collapsing input limit                      : 34
