
EasyPack/SLD80C196F Readme
============================

This File Contains:
1. File list
2. Firmware Version and CPU Modules
3. Supported Tool Chains
4. Samples containing bank switching
5. Limitation and Sollution

1. Files List:
------------------------------
    EP196    EXE
    FWSETUP  EXE
    BANKSET  EXE
    DIAGNO   EXE
    SRCDLL   DLL
    BPTDLL   DLL
    MUSCROLL DLL
    GOSVR    DLL
    STEPDLL  DLL
    ABI196   DLL
    ADDRDLL  DLL
    MFC250   DLL
    METER    DLL
    LOADDLL  DLL
    SYMSVR   DLL
    INIT196  DLL
    REGMAP   DLL
    ICE_SYM1 DLL
    ICE_ERR  DLL
    ICE9X    DLL
    ICE196KA DLL
    CTL3D    DLL
    REGTBL   DAT
    CMDLIST  DAT
    COMMAND  DAT
    HINTS    DAT
    INFOR    DAT
    EP196    HLP
    README   TXT
    COMM     DRV


2. Firmware Version and CPU Modules:
-------------------------------------
   1. Supported by Firmware 1.00
   2. Support Cpu Module
        8xC196MC,
        8xC196MD,
        8xC196MH,
        8xC196KC,
        8xC196KB,
        8xC196KA,
        8x96,
        8x98,

3. Supported Tool Chains:
------------------------------------
   1. Format:  .ABS (OMF96)
      Company: BSO Tasking Software Inc.
      Version: (for windows)
               C196.EXE,     V5.0
               ASM196.EXE,   V5.0
               RL196.EXE,    V5.0
      Options:
               C196: model(kc)     -- select memory model: KC
                     debug         -- include symbolic debugging
                                      information
                     ot(0)         -- forbit optimization
                     code          -- generates or suppresses pseudo-assembly
                                      language code listing in print file
                     diagnostic(level)    -- specifies level of diagnostic messages,
                                             level is the value 0,1, or 2.
                     type          -- generates or suppresses type information in
                                      the object module
               RL196:

   2. Format:  .D32 (ICC196)
      Company: IAR Systems
      Version: (for windows) V2.0
               ICC196.EXE,  V5.20B
               A196.EXE,    V1.10A
               XLINK.EXE,   V4.48B
      Options:
               ICC196:
                        -v0    -- processors supported is 8x196KB, 8x198
                        -v1    -- processors supported is 8x196KC, 8x16KD
                        -ms    -- select memory model: small
                        -ml    -- select memory model: large
                        -mb    -- select memory model: banked
                        -D     -- define symbols
                        -l     -- generates list file
                        -q     -- insert mnemonics
                        -r     -- generates debug information
               XLINK:   -f     -- extend command line with <.xcl> file

   3. Format:  .HEX (Intel)

4. Samples containing bank switching:
------------------------------------
  1. Format: *.d32(ICC196)
     Company: IAR Systems

     Bank numbers you specified in your linker control file can not exceed four
     banks. Port P1 is defaultly specified to switch bank.
     If you want to change it into P3 or others,
         Firstly, you should modify L07.s32(in directory of compiler),
                  then compile it;
         Secondly,you should use XLIB and substitute module named L07 of CL8051b.r32
                  with L07.s32 generating from last step.
         Then   , you should rebulid or link your samples again.

5. Limitation and Sollution
1). About Timer
The timer count value will be counted within halt state, and cause
Timer overflow. User can not use "Step" or "Step Over" command to
debug timer. We suggest user use "Go" and "Breakpoint" to get right timer.

2). Breakpoint after "Trap" instruction
If there is a "Trap" instruction, and setting a breakpoint below the
"Trap" location less than 4 bytes and then  "Go" , the CPU will stop
at the "TRAP" instruction.

3). INPEND register
User can not use the "LD", "ST" instruction to operate the "INPEND"
register. Please refer to the CPU data book, and use the "AND", "OR"
to operate the "INPEND" register.

4). Interrupt will not be serviced in the "Step"command.

5). Stack and Local Variable
Because UBROF file format does not provide information about stack structure and 
principle, when user debugs such files, sometimes the stack window may be displayed 
incorrectly, nor do some local variables. 
 
6). Watchdog
Please do not enable the watchdog when debugging.

7). 196Mx's ROM type CPU
In 196Mx's ROM type CPU, some addresses have been moved.
 CPU register name  Old address           EasyPack support name  New address
 CPU:P3_REG:           1FFCH      ------->   EP:P3_REG:           FFFCH
 CPU:P4_REG:           1FFDH      ------->   EP:P4_REG:           FFFDH
 CPU:P3_PIN:           1FFEH      ------->   EP:P3_PIN:           FFFEH
 CPU:P4_PIN:           1FFFH      ------->   EP:P4_PIN:           FFFFH
 CPU:P5_REG:           1FF5H      ------->   EP:P5_REG:           FFF5H
 CPU:P5_PIN:           1FF7H      ------->   EP:P5_PIN:           FFF7H
 CPU:P5_MODE:          1FF1H      ------->   EP:P5_MODE:          FFF1H
 CPU:P5_DIR:           1FF3H      ------->   EP:P5_DIR:           FFF3H
For examples: When user wants to write a data to the CPU:P3_REG(1FFCH), user
shall modify his/her program: to write the data to EP:P3_REG(FFFCH)

8) About P5_MODE,P5_DIR
The register EP:P5_MODE(FFF1H) and EP:P5_DIR(FFF3H) do not function really.
These values are only for show.
In user's program, User shall not change the registers: CPU:P5_MODE(1FF1) and
CPU:P5_DIR  (1FF3H).

9) About WDE bit in the CCR1
The WDE(Watch timer enable) is forced to function:  "1 = enabled first time
it is cleared"
