;-------------------------------------------------------------------
; CP initializations (cpinit.def)
;-------------------------------------------------------------------

; Chip-Select Control
CS_LEN             EQU     10
UCS_START          EQU     0E000h+CSwait0   ; ROM0
UCS_STOP           EQU     0FFC0h+CSen+CSmem+CSistop

LCS_START          EQU     00000h+CSwait0   ; RAM0
LCS_STOP           EQU     02000h+CSen+CSmem

CS7_START          EQU     0C000h+CSwait0   ; ROM1
CS7_STOP           EQU     0E000h+CSen+CSmem

CS6_START          EQU     02000h+CSwait0   ; RAM1
CS6_STOP           EQU     04000h+CSen+CSmem

CS5_START          EQU     0FFCFh           ; disable
CS5_STOP           EQU     0FFC3h

CS4_START          EQU     0FFCFh           ; disable
CS4_STOP           EQU     0FFC3h

CS3_START          EQU     0FFCFh           ; disable
CS3_STOP           EQU     0FFC3h

CS2_START          EQU     0A000h+CSwait0   ; JTAG_BUF
CS2_STOP           EQU     0A100h+CSen+CSmem

CS1_START          EQU     00040h+CSwait0   ; JTAG_DATA
CS1_STOP           EQU     00080h+CSen+CSrdy

CS0_START          EQU     00000h+CSwait0   ; JTAG_CTRL
CS0_STOP           EQU     00040h+CSen

; I/O Port
P1CTRLinit         EQU     0C7h
P1LTCHinit         EQU     018h
P2DIRinit          EQU     000h
P2CTRLinit         EQU     00Bh
P2LTCHinit         EQU     0FFh

; Serial Port
;S0BAUDinit         EQU     SPiclk+16   ;(16MHz/(8*115200))-1
;S0BAUDinit         EQU     SPiclk+34   ;(16MHz/(8*57600))-1
;S0BAUDinit         EQU     SPiclk+103  ;(16MHz/(8*19200))-1
;S0BAUDinit         EQU     SPiclk+207  ;(16MHz/(8*9600))-1
;S0BAUDinit         EQU     10;
S0BAUDinit         EQU     SPiclk+207  ;(16MHz/(8*9600))-1
S0CTRLinit         EQU     SPcts+SPmod1

; Timer
TIME_UNIT          EQU     2500        ;(16MHz/4)*10ms/16
INT_TM0_VEC        EQU     20h
TM0_UNIT           EQU     50h         ;(50ms/10ms)*16
T0CTRLinit         EQU     TmrINH+TmrCONT+TmrINT+TmrP
T1CTRLinit         EQU     TmrINH+TmrINT+TmrP
T2CTRLinit         EQU     TmrINH+TmrCONT

; Interrupt Control
INT_MASK           EQU     8           ;mask bit in control register
INT_LVL            EQU     10h         ;level trigger
SP0_INTinit        EQU     0           ;highest priority
TGT_INTinit        EQU     1+INT_LVL   ;
SP1_INTinit        EQU     2+INT_LVL   ;
TMR_INTinit        EQU     3           ;lowest priority
