
// ----- 10/8/1996 4:24 log file opened -----
//******** MICEpack 68328 Test Data 8_bit mode************// 
//******** Include File : Mp328_8.inc         ************// 
//******** Target :  Null Target              ************// 
//******** Log file : samp2.txt               ************// 
 
//* signal dtack_ext disable ; 
map 0 fffff ram ; 
// Mapped block #0: 0x000000 0x0FFFFF RAM UP UD SP SD
res  ; 
// 000400  2E7C 0000 16EA  MOVEA.L     #000016EA,A7
halt ; 
// 000400  2E7C 0000 16EA  MOVEA.L     #000016EA,A7
 
//***** Selftest *****// 
selftest; 
//   Test MCE16B -- Good
//   Test emulation memory bank1 -- Good
//   Test emulation memory bank2 -- Good
//   Test emulation memory bank3 -- Good
//   Test emulation memory bank4 -- Good
//   Test trace module -- Good
 
 
//***** Register Modify test *****// 
reg pc 0x00000402; 
reg d0 0x11111111; 
reg d1 0x22222222;	 
reg d2 0x33333333; 
reg d3 0x44444444; 
reg d4 0x55555555; 
reg d5 0x66666666; 
reg d6 0x77777777; 
reg d7 0x88888888; 
reg a0 0x99999999; 
reg a1 0xaaaaaaaa; 
reg a2 0xbbbbbbbb;	 
reg a3 0xcccccccc; 
reg a4 0xdddddddd; 
reg a5 0xeeeeeeee; 
reg a6 0xffffffff; 
reg ssp 0x12345678; 
reg usp 0xabcdef12; 
reg sr 0xffff; 
reg; 
//     PC =   0x000402
//     A7 = 0x12345678
//     A6 = 0xFFFFFFFF
//     D0 = 0x11111111
//     D1 = 0x22222222
//     D2 = 0x33333333
//     D3 = 0x44444444
//     D4 = 0x55555555
//     D5 = 0x66666666
//     D6 = 0x77777777
//     D7 = 0x88888888
//     A0 = 0x99999999
//     A1 = 0xAAAAAAAA
//     A2 = 0xBBBBBBBB
//     A3 = 0xCCCCCCCC
//     A4 = 0xDDDDDDDD
//     A5 = 0xEEEEEEEE
//     SR =     0xFFFF
//        = TS7XNZVC
//    SSP = 0x12345678
//    USP = 0xABCDEF12
res; 
// 000400  1038 0001       MOVE.B      000001,D0
 
//***** Map setting & Memory Test *****// 
 
map clear; 
// All memory mapped to target
map 0 fffff ram sp sd up ud ; 
// Mapped block #0: 0x000000 0x0FFFFF RAM UP UD SP SD
ramtst 0x400 0xfffff; 
// RAM Test OK.
map clear ; 
// All memory mapped to target
map e00000 efffff ram; 
// Mapped block #0: 0xE00000 0xEFFFFF RAM UP UD SP SD
ramtst e00000 efffff ; 
// RAM Test OK.
map clear; 
// All memory mapped to target
map 0 0x1ffff none sp sd up ud ; 
// Mapped block #0: 0x000000 0x01FFFF NONE UP UD SP SD
fill 0 ff 0xabcd word; 
// Memory verification failed (address: 0x000000 SD , expected: 0xABCD, actual: 0xFFFF).
map clear; 
// All memory mapped to target
ramtst 1000 1fff ; 
// RAM Test failure at: 0x1000  sd
// Test operation aborted prior to completion.
map 0 ffff ram; 
// Mapped block #0: 0x000000 0x00FFFF RAM UP UD SP SD
 
 
//***** Load file test & software brkpnt *****// 
map; 
// Mapped block #0: 0x000000 0x00FFFF RAM UP UD SP SD
load "c:\mp68k\samp68k\demo.abs" reload;  
// 4233 bytes code loaded.
// 2 module(s) loaded.
// Load complete.
reset; 
// 000400  2E7C 0000 16EA  MOVEA.L     #000016EA,A7
bkpt 0x406; 
bkpt 0x414; 
bkpt 0x430; 
bkpt #main; 
go;go;go;go; 
// Emulation started
// 000406  DFFC 0000 0080  ADDA.L      #00000080,A7
// 000406  DFFC 0000 0080  ADDA.L      #00000080,A7
// Emulation started
// 000414  23C8 0000 16E6  MOVE.L      A0,_HEAP
// 000414  23C8 0000 16E6  MOVE.L      A0,_HEAP
// Emulation started
// 000430  4EB9 0000 1190  JSR         memset
// 000430  4EB9 0000 1190  JSR         memset
// Emulation started
// 000452  4E56 0000       LINK.W      A6,#0000
// 000452  4E56 0000       LINK.W      A6,#0000
bkpt temporary 0x46a; 
go; 
// Emulation started
// 00046A  4EB9 0000 04EC  JSR         insert
// 00046A  4EB9 0000 04EC  JSR         insert
step into; 
// 0004EC  2F0A            MOVE.L      A2,-(A7)
gointo return; 
// 000470  4EB9 0000 0546  JSR         printall
step over; 
// 000476  4878 0003       PEA.L       000003
gointo call; 
// 00051E  202F 0004       MOVE.L      (0004,A7),D0
gountil return; 
// 00053A  2091            MOVE.L      (A1),(A0)
gointo return; 
// 000484  4EB9 0000 0546  JSR         printall
// 000484  4EB9 0000 0546  JSR         printall
step over 3; 
// 000496  4EB9 0000 05AE  JSR         cosineFunc
step into 2; 
// 0005B2  48E7 3000       MOVEM.L     D3-D2,-(A7)
bkptclear all; 
res; 
 
 
 
//***** Trace test *****// 
include "c:\MP68K\328\trg.inc"; 
 
 
eventrestore "c:\MP68K\328\328test.evt"; 
_trgopen default; 
//**level 0**// 
_trglevel 0; 
// 0
_trgmode post; 
// POST
_trgevent ev0; 
// EV0
_trgname t1; 
// t1
_trgenable true; 
// TRUE
_trgaction seq inc0; 
// SEQ|INC0
_trgevent ev1; 
// EV1
_trgname t4; 
// t4
_trgenable true; 
// TRUE
_trgaction seq inc1; 
// SEQ|INC1
_trgcntrfunc counter; 
// COUNTERS
_trgevent tc1; 
// TC1
_trgcntrval 1# 4; 
// 4
_trgenable true; 
// TRUE
_trgaction brk; 
// BRK
//**level 1**// 
_trglevel 1; 
// 1
_trgevent ev0; 
// EV0
_trgname t2; 
// t2
_trgenable true; 
// TRUE
_trgaction seq inc1; 
// SEQ|INC1
_trgevent ev1; 
// EV1
_trgname t5; 
// t5
_trgenable true; 
// TRUE
_trgaction inc1; 
// INC1
_trgevent tc1; 
// TC1
_trgenable true; 
// TRUE
_trgaction brk; 
// BRK
 
//**level 2**// 
_trglevel 2; 
// 2
_trgevent ev0; 
// EV0
_trgname t3; 
// t3
_trgenable true; 
// TRUE
_trgaction seq inc0 ; 
// SEQ|INC0
//**level 3**// 
_trglevel 3; 
// 3
_trgevent tc0; 
// TC0
_trgcntrval 0# 2; 
// 2
_trgenable true; 
// TRUE
_trgaction reset inc1; 
// RESET|INC1
_evevent t3; 
// t3
_evclear; 
_evfield address; 
// address
_evstart 42a; 
// 42a
_evend 42a: 
// res; 
REG PC 400 ; 
// 42a
go; 
// Emulation started
// 000470  4EB9 0000 0546  JSR         printall
// 000470  4EB9 0000 0546  JSR         printall
nameof pc; 
// #dm_main#75#1 (function main+0x1E [30])
_trgclrtrig; 
_evdelall; 
 
//***** Hardware breakpoint test *****// 
map clear; 
// All memory mapped to target
bkptclear all; 
bkpt 406; 
bkpt 40e; 
bkpt 416; 
// The number of hardware breakpoints exceeds capability.
bkptclear all; 
 
logging off; 

// ----- 10/8/1996 4:28 log file closed -----
