#ifndef _PERERRST_
#include "pererrst.h"
#endif

#ifndef _PERIMENU_
#include "perimenu.h"
#endif

#ifndef _PERIRCID
#include "perircid.h"
#endif

#ifndef _MUSCROLL_
#include "muscroll.h"
#endif

#ifdef IDHELP
#undef IDHELP
#define IDHELP 8
#endif

peri_menu MENU 
BEGIN
	POPUP "&File"
	BEGIN
		MENUITEM "E&xit", CM_FEXIT
	END

	POPUP "&Edit"
	BEGIN
		MENUITEM "Re&gister...", CM_EREG
		MENUITEM "Go To &Peripheral...", CM_EGO2PERI
		MENUITEM "Go To &Register...", CM_EGO2REG
		MENUITEM "Go To &Address...", CM_EGO2ADR
	END

	POPUP "&View"
	BEGIN
		MENUITEM "&Expand All", CM_VEXALL
		MENUITEM "&Compress All", CM_VCMALL
		MENUITEM SEPARATOR
		MENUITEM "Re&fresh Display", CM_VREF
	END

	POPUP "&Windows"
	BEGIN
		MENUITEM "&Breakpoint", CM_WINBKP
		MENUITEM "&CPU", CM_WINCPU
/*                MENUITEM "&Event", CM_WINEVT <JUDY 10/11/1996> */
		MENUITEM "&Memory", CM_WINMEM
		MENUITEM "&Peripheral", CM_WINPERI
		MENUITEM "S&hell", CM_WINSHL
		MENUITEM "&Source", CM_WINSRC
		MENUITEM "S&tack", CM_WINSTK
		MENUITEM "Stat&us", CM_WINSTAT
		MENUITEM "T&oolBar", CM_WINTB
		MENUITEM "Tr&ace", CM_WINTRC
		MENUITEM "Tri&gger", CM_WINTRG
		MENUITEM "&Variable", CM_WINVAR
                MENUITEM "SPA(&z)",   CM_WINSPA   /* <judy 10/11/1996> */
	END

	POPUP "&Help"
	BEGIN
		MENUITEM "Help &Index", CM_HLPIN
		MENUITEM "&Help With Help", CM_HLPHLP
		MENUITEM SEPARATOR
		MENUITEM "Help With &Peripheral", CM_HLPPERI
	END

END

DIA_GO2PER DIALOG 39, 40, 115, 57
STYLE DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU
CAPTION "Generic Dialog"
BEGIN
	CONTROL "Static_Text:", STATIC_ID, "STATIC", SS_LEFT | WS_CHILD | WS_VISIBLE, 7, 9, 102, 8
	CONTROL "", ER_VALUE_ID, "EDIT", ES_LEFT | WS_CHILD | WS_VISIBLE | WS_BORDER | WS_GROUP | WS_TABSTOP, 12, 21, 90, 13
	CONTROL "&OK", IDOK, "BUTTON", BS_DEFPUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 6, 41, 30, 14
	CONTROL "&Cancel", IDCANCEL, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 43, 41, 30, 14
	CONTROL "&Help", IDHELP, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 78, 41, 30, 14
END


DIA_EDITREG DIALOG 14, -30, 248, 161
STYLE DS_MODALFRAME | WS_POPUP | WS_VISIBLE | WS_CAPTION | WS_SYSMENU
CAPTION " "
BEGIN
	CONTROL "&Register Value:", -1, "STATIC", SS_LEFT | WS_CHILD | WS_VISIBLE, 8, 9, 53, 10
	CONTROL "", ER_VALUE_ID, "EDIT", ES_LEFT | ES_WANTRETURN | WS_CHILD | WS_VISIBLE | WS_BORDER | WS_GROUP | WS_TABSTOP, 65, 7, 62, 14
	LTEXT "", ER_WRITE_ONLY_ID, 138, 8, 102, 8
	LTEXT "&Fields:", -1, 8, 24, 43, 8, WS_CHILD | WS_VISIBLE | WS_GROUP
	CONTROL "", ER_LISTBOX_ID, "LISTBOX", LBS_NOTIFY | LBS_USETABSTOPS | WS_CHILD | WS_VISIBLE | WS_BORDER | WS_VSCROLL | WS_HSCROLL | WS_GROUP | WS_TABSTOP, 8, 34, 233, 64
	LTEXT "Field &Value:", -1, 9, 102, 42, 7, WS_CHILD | WS_VISIBLE | WS_GROUP
	CONTROL "", ER_FVALUE_ID, "EDIT", ES_LEFT | WS_CHILD | WS_VISIBLE | WS_BORDER | WS_GROUP | WS_TABSTOP, 8, 111, 44, 14
	CONTROL "", ER_SPIN_ID, "MicroScroll", WS_CHILD | WS_VISIBLE | MSS_VERTICAL, 52, 111, 6, 14
	CONTROL " ", ER_FLDINFO_ID, "EDIT", ES_LEFT | ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | WS_CHILD | WS_VISIBLE | WS_DISABLED | WS_GROUP, 66, 101, 175, 39
	CONTROL "&Write", ER_WRITE_ID, "BUTTON", BS_DEFPUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 5, 144, 44, 14
	CONTROL "&Close", ER_CLOSE_ID, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 53, 144, 45, 14
	CONTROL "<< &Prev", ER_PREV_ID, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 105, 144, 44, 14
	CONTROL "&Next >>", ER_NEXT_ID, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 152, 144, 44, 14
	CONTROL "&Help", IDHELP, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 203, 144, 40, 14
END


DIA_GO2ADDR DIALOG 37, 37, 160, 60
STYLE DS_MODALFRAME | WS_OVERLAPPED | WS_VISIBLE | WS_CAPTION | WS_SYSMENU
CAPTION "Go To Address"
FONT 10, "System"
BEGIN
	CONTROL "&Address:", -1, "STATIC", SS_LEFT | WS_CHILD | WS_VISIBLE, 8, 13, 36, 8
	CONTROL "", G2A_EDIT_ID, "EDIT", ES_LEFT | ES_AUTOHSCROLL | WS_CHILD | WS_VISIBLE | WS_BORDER | WS_GROUP | WS_TABSTOP, 8, 24, 142, 12
	CONTROL "&OK", IDOK, "BUTTON", BS_DEFPUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 11, 43, 36, 14
	CONTROL "&Cancel", IDCANCEL, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 63, 43, 36, 14
	CONTROL "&Help", IDHELP, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 112, 43, 36, 14
END

DIA_EDITBUF DIALOG 18, 18, 182, 92
STYLE DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU
CAPTION "Buffer Name"
BEGIN
	LTEXT "Buffer Base", -1, 100, 7, 41, 8
	LTEXT "Address:", -1, 100, 15, 30, 8
	LTEXT "0xFFFC0E", EB_BASEADDRESS_ID, 131, 15, 46, 8, WS_CHILD | WS_VISIBLE | WS_GROUP
	LTEXT "Address:", -1, 100, 33, 30, 8, WS_CHILD | WS_VISIBLE | WS_GROUP
	LTEXT "0xFFFC0E", EB_ADDRESS_ID, 131, 33, 46, 8, WS_CHILD | WS_VISIBLE | WS_GROUP
	CONTROL "", EB_LISTBOX_ID, "LISTBOX", LBS_NOTIFY | LBS_USETABSTOPS | WS_CHILD | WS_VISIBLE | WS_BORDER | WS_VSCROLL | WS_TABSTOP, 6, 6, 84, 61
	CONTROL "0xFFFF", EB_EDIT_ID, "EDIT", ES_LEFT | ES_NOHIDESEL | WS_CHILD | WS_VISIBLE | WS_BORDER | WS_TABSTOP, 108, 46, 48, 12
	CONTROL "&OK", IDOK, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 31, 75, 33, 14
	CONTROL "&Cancel", IDCANCEL, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 74, 75, 33, 14
	CONTROL "&Help", IDHELP, "BUTTON", BS_PUSHBUTTON | WS_CHILD | WS_VISIBLE | WS_GROUP | WS_TABSTOP, 117, 75, 33, 14
END


STRINGTABLE LOADONCALL MOVEABLE PURE DISCARDABLE 
{     
;new CLI registration
  0,  "peripheral"
  1,  "peri.dll"
  2,  "0"

 99, "Peripheral Server"
PP_NULL_STR, ""


;peripheral description and informational strings
200, "Module Configuration Register"
201, "MCR controls the SIM configuration"
202, "CLKOUT driven from internal source"
203, "CLKOUT in high impedance state"
204, "SW watchdog and counters enabled"
205, "SW watchdog and counters disabled"
206, "Bus monitor enabled"
207, "Bus monitor disabled"
208, "Slave mode disabled"
209, "Slave mode enabled"
210, "Show cycles disabled, arbitration enabled"
211, "Show cycles enabled, arbitration disabled"
212, "Show cycles enabled, arbitration enabled"
213, " "
214, "Show cycles enabled, arbitration enabled, bus grant"
215, "Register access unrestricted"
216, "Register access restricted to supervisor"
217, "Modules addressed 7FF000 - 7FFFFF"
218, "Modules addressed FFF000 - FFFFFF"
219, "Reset value, interrupts are discarded"
220, "Interrupt value from F(highest priority) to 1(lowest priority"
221, "Module Test Register"
222, "SIMTR is reserved for factory testing"
223, "Part revision number"
224, "Internal scan in"
225, "External scan in"
226, "Periodic interrupt zero detect"
227, "Modulo counter clock output"
228, "Off"
229, "Reserved"
230, "Show internal IRQ"
231, "Show internal bus signals"
232, "SW watchdog bypass"
233, "SW watchdog reset"
234, "Loss of clock reset"
235, "Narrow bandwidth"
236, "Wide bandwidth"
237, "Disable filter"
238, "Module Test Register E Clock"
239, "SIMTRE is reserved for factory testing"
240, "Reset Status Register"
241, "RSR indicates the last type of reset that occurred"
242, "Last reset from external signal"
243, "Last reset from power-up reset"
244, "Last reset from SW watchdog"
245, "Last reset from system protection submodule"
246, "Last reset from loss of frequency reference to clock submodule"
247, "Last reset from CPU reset"
248, "Last reset from test submodule"
249, "Clock Synthesizer Control Register"
250, "SYNCR controls and reports the status of the processor clock"
251, "Prescaler tap inactive, VCO speed unmodified"
252, "Prescaler tap active, VCO speed increased x4"
253, "Divide by two prescaler inactive, clock speed unmodified"
254, "Divide by two prescaler active, clock speed doubled"
255, "E-Clock divide rate: system clock divided by 8"
256, "E-Clock divide rate: system clock divided by 16"
257, "External crystal frequency is VCO reference"
258, "External crystal frequency lost.  VCO is one half maximum speed."
259, "VCO is enabled, but has not locked yet."
260, "VCO is locked on the desired frequency."
261, "Loss of clock causes processor to run at nominal speed."
262, "Loss of clock causes processor to reset."
263, "LPSTOP causes SIM clock to be driven by crystal oscillator."
264, "LPSTOP causes SIM clock to be driven by VCO."
265, "LPSTOP causes CLKOUT to be driven low."
266, "LPSTOP causes CLKOUT to be driven by SIM clock."
267, "Port E/F Data Register"
268, "Port E/F Data holds the current state of the programable I/O pins."
269, "Port E/F Data Direction Register"
270, "DDRE/DDRF programs the Port E/F pins to be inputs and/or outputs."
271, "Port E/F Pin Assignment Register"
272, "PEPAR/PFPAR assigns the function of each Port E/F pin."
273, "System Protection Control Register"
274, "SYPCR controls the SW watchdog clock, and bus monitor timing."
275, "SW watchdog disabled."
276, "SW watchdog enabled."
277, "SW watchdog is not prescaled."
278, "SW watchdog is prescaled by 512."
279, "SW watchdog timeout period is  2^^9/EXTAL.  (2^^18 if SWP = 1)"
280, "SW watchdog timeout period is 2^^11/EXTAL.  (2^^20 if SWP = 1)"
281, "SW watchdog timeout period is 2^^13/EXTAL.  (2^^22 if SWP = 1)"
282, "SW watchdog timeout period is 2^^15/EXTAL.  (2^^24 if SWP = 1)"
283, "Halt monitor is disabled."
284, "Halt monitor is enabled."
285, "Bus monitor external disabled. (Internal to external cycle)"
286, "Bus monitor external enabled. (Internal to external cycle)"
287, "Bus monitor timeout period is 64 system clocks."
288, "Bus monitor timeout period is 32 system clocks."
289, "Bus monitor timeout period is 16 system clocks."
290, "Bus monitor timeout period is  8 system clocks."
291, "Periodic Interrupt Control Register"
292, "Sets up the interrupt level and vector for the periodic timer."
293, "Periodic interrupts disabled."
294, "Periodic interrupt request level 1."
295, "Periodic interrupt request level 2."
296, "Periodic interrupt request level 3."
297, "Periodic interrupt request level 4."
298, "Periodic interrupt request level 5."
299, "Periodic interrupt request level 6."
300, "Periodic interrupt request level 7."
301, "Interrupt vector."
302, "Periodic Timer Interrupt Register"
303, "PITR defines the amount of time between periodic interrupts."
304, "Periodic timer clock not prescaled."
305, "Periodic timer clock prescaled by 512."
306, "Periodic timer timer modulus value."
307, "Software Service Register"
308, "SWSR is used to service the SW watchdog timer."
309, "Master Shift Register A"
310, "Master Shift Register B"
311, "Shift Count Register A"
312, "Shift Count Register B"
313, "Test Repetition Counter"
314, "Test Submodule Control Register"
315, "Configures the test submodule"
316, "Test submodule is not busy"
317, "Test submodule is busy"
318, "TSTME pin negated, test mode disabled"
319, "TSTME pin asserted, test mode enabled"
320, "Shift register B contains incorrect answer"
321, "Shift register B contains correct answer"
322, "Internal interconnect lines are in normal operation mode"
323, "Internal interconnect lines are in test mode"
324, "Scan lines disconnected from the CPU test register"
325, "Scan lines connected to the CPU test register"
326, "The internal freeze status is available on FREEZE/QUOT pin"
327, "LSB of Shift Register B available on FREEZE/QUOT pin"
328, "Shift in source for the MSRB is the internal test line"
329, "Shift in source for the MSRB is the external interrupt pin"
330, "Stay in normal mode"
331, "Stop continuous operation"
332, "Start continuous operation"
333, "Start shifting operation"
334, "Start an automatic testing operation"
335, "Enter test mode"
336, "Distributed Register"
337, "Configures the master shift registers"
338, "Programs the wait between test sequences"
339, "MSB of Shift Register A"
340, "Master Shift Register A Configuration"
341, "MSB of Shift Register B"
342, "Master Shift Register B Configuration"
343, "Chip Select Pin Data Register"
344, "Controls the state of CS pins programmed as discreet outputs."
345, "Chip Select Pin Assignment Register 0"
346, "Assigns the function of chip select pins CS1-CS5"
347, "CS5 is a discrete output"
348, "CS5 uses the default function"
349, "CS5 is an 8 bit chip select"
350, "CS5 is a 16 bit chip select"
351, "CS4 is a discrete output"
352, "CS4 uses the default function"
353, "CS4 is an 8 bit chip select"
354, "CS4 is a 16 bit chip select"
355, "CS3 is a discrete output"
356, "CS3 uses the default function"
357, "CS3 is an 8 bit chip select"
358, "CS3 is a 16 bit chip select"
359, "CS2 is a discrete output"
360, "CS2 uses the default function"
361, "CS2 is an 8 bit chip select"
362, "CS2 is a 16 bit chip select"
363, "CS1 is a discrete output"
364, "CS1 uses the default function"
365, "CS1 is an 8 bit chip select"
366, "CS1 is a 16 bit chip select"
367, "SWSR1 is a discrete output"
368, "SWSR1 uses the default function"
369, "SWSR1 is an 8 bit chip select"
370, "SWSR1 is a 16 bit chip select"
371, "SWSR0 is a discrete output"
372, "SWSR0 uses the default function"
373, "SWSR0 is an 8 bit chip select"
374, "SWSR0 is a 16 bit chip select"
375, "Chip Select Pin Assignment Register 1"
376, "Assigns the function of chip select pins CS6-CS10"
377, "CS10 is a discrete output"
378, "CS10 uses the default function"
379, "CS10 is an 8 bit chip select"
380, "CS10 is a 16 bit chip select"
381, "CS9 is a discrete output"
382, "CS9 uses the default function"
383, "CS9 is an 8 bit chip select"
384, "CS9 is a 16 bit chip select"
385, "CS8 is a discrete output"
386, "CS8 uses the default function"
387, "CS8 is an 8 bit chip select"
388, "CS8 is a 16 bit chip select"
389, "CS7 is a discrete output"
390, "CS7 uses the default function"
391, "CS7 is an 8 bit chip select"
392, "CS7 is a 16 bit chip select"
393, "CS6 is a discrete output"
394, "CS6 uses the default function"
395, "CS6 is an 8 bit chip select"
396, "CS6 is a 16 bit chip select"
397, "Chip Select Boot Base Address Register"
398, "Defines the base address and block size for the chip select"
399, "Chip Select base address"
400, "2 KB block"
401, "8 KB block"
402, "16 KB block"
403, "64 KB block"
404, "128 KB block"
405, "256 KB block"
406, "512 KB block"
407, "1 MB block"
408, "Chip Select Boot Option Register"
409, "Configures the chip selects operation"
410, "Asynchronous"
411, "Synchronous"
412, "Off"
413, "Lower"
414, "Upper"
415, "Both bytes"
416, "Read"
417, "Write"
418, "Read/Write"
419, "AS"
420, "DS"
421, "0 wait state"
422, "1 wait state"
423, "2 wait state"
424, "3 wait state"
425, "4 wait state"
426, "5 wait state"
427, "6 wait state"
428, "7 wait state"
429, "8 wait state"
430, "9 wait state"
431, "10 wait state"
432, "11 wait state"
433, "12 wait state"
434, "13 wait state"
435, "Fast Termination"
436, "External DSACK"
437, "CPU space"
438, "User space"
439, "Supervisor space"
440, "Supervisor/User space"
441, "All IPL"
442, "Level 1 IPL"
443, "Level 2 IPL"
444, "Level 3 IPL"
445, "Level 4 IPL"
446, "Level 5 IPL"
447, "Level 6 IPL"
448, "Level 7 IPL"
449, "Autovectoring off"
450, "Autovectoring on"
451, "Chip Select 0 Base Address Register"
452, "Chip Select 0 Option Register"
453, "Chip Select 1 Base Address Register"
454, "Chip Select 1 Option Register"
455, "Chip Select 2 Base Address Register"
456, "Chip Select 2 Option Register"
457, "Chip Select 3 Base Address Register"
458, "Chip Select 3 Option Register"
459, "Chip Select 4 Base Address Register"
460, "Chip Select 4 Option Register"
461, "Chip Select 5 Base Address Register"
462, "Chip Select 5 Option Register"
463, "Chip Select 6 Base Address Register"
464, "Chip Select 6 Option Register"
465, "Chip Select 7 Base Address Register"
466, "Chip Select 7 Option Register"
467, "Chip Select 8 Base Address Register"
468, "Chip Select 8 Option Register"
469, "Chip Select 9 Base Address Register"
470, "Chip Select 9 Option Register"
471, "Chip Select 10 Base Address Register"
472, "Chip Select 10 Option Register"
473, "QSM Module Configuration Register"
474, "MCR controls the QSM configuration"
475, "Normal QSM clock operation"
476, "QSM clock operation stopped"
477, "QSM Test Register"
478, "Used for testing the QSM"
479, "SPI scan path baud clock enabled"
480, "SCK scan path delay enabled"
481, "SCI source signal activated"
482, "SCI source signal disabled"
483, "Scan path disabled"
484, "Scan paths enabled"
485, "QSM responds to QSM memory addresses"
486, "QSM responds to test memory addresses"
487, "QSM Interrupt Level Register"
488, "Configures the interrupt level generated by the SCI and QSPI"
489, "QSM Interrupt Vector Register"
490, "Sets the interrupt vector generated by the SCI and QSPI."
491, "SCI Control Register 0"
492, "Configures the SCI baud rate"
493, "Encoded baud rate"
494, "SCI Control Register 1"
495, "Configures the SCI"
496, "SCI test/looping/feedback disabled"
497, "SCI test/looping/feedback enabled"
498, "TXD is a normal CMOS output"
499, "TXD is open-drain"
500, "Short idle-line detect"
501, "Long idle-line detect"
502, "Even parity"
503, "Odd parity"
504, "SCI parity disabled"
505, "SCI parity enabled"
506, "SCI frame: 1 start, 8 data, 1 stop"
507, "SCI frame: 1 start, 9 data, 1 stop"
508, "SCI receiver awakened by idle-line detection"
509, "SCI receiver awakened by address mark bit"
510, "SCI TDRE interrupts disabled"
511, "SCI TDRE interrupts enabled"
512, "SCI TC interrupts disabled"
513, "SCI TC interrupts enabled"
514, "SCI RDRF interrupts disabled"
515, "SCI RDRF interrupts enabled"
516, "SCI IDLE interrupts disabled"                   
517, "SCI IDLE interrupts enabled"
518, "SCI transmitter disabled"
519, "SCI transmitter enabled"
520, "SCI receiver disabled"
521, "SCI receiver enabled"
522, "Normal receiver operation"
523, "Wakeup mode enabled"
524, "Normal operation"
525, "Break frames enabled"
526, "SCI Status Register"
527, "Contains SCI status flags."
528, "TDR still contains data"
529, "TDR will accept a new character"
530, "SCI transmitter is busy"
531, "SCI transmitter is idle"
532, "RDR is empty"
533, "RDR contains new data"
534, "SCI receiver is idle"
535, "SCI receiver is busy"
536, "SCI receiver: idle-line not detected"
537, "SCI receiver: idle-line detected"
538, "RDRF cleared before new data arrives"
539, "RDRF is not cleared before new data arrives"
540, "No noise detected on received data"
541, "Noise detected on received data"
542, "No framing error on received data"
543, "Framing error/break on received data"
544, "No parity error on received data"
545, "Parity error on received data"
546, "SCI Data Register"
547, "Holds data received/transmitted"
548, "QSM Port Data Register"
549, "Holds data if QSM pins are general I/O"
550, "QSM Pin Assignment Register"
551, "Assigns the function of QSM pins"
552, "General Purpose I/O"
553, "QSPI module pin"
554, "QSM Data Direction Register"
555, "Configures the QSM pins as input or output"
556, "Input pin"
557, "Output pin"
558, "QSPI Control Register 0"
559, "Configures the QSPI"
560, "QSPI in slave mode"
561, "QSPI in master mode"
562, "QSPI pins are CMOS outputs"
563, "QSPI pins are open-drain"
564, "16 bits/transfer"
565, "8 bits/transfer"
566, "9 bits/transfer"
567, "10 bits/transfer"
568, "11 bits/transfer"
569, "12 bits/transfer"
570, "13 bits/transfer"
571, "14 bits/transfer"
572, "15 bits/transfer"
573, "SCK inactive state is LOW"
574, "SCK inactive state is HIGH"
575, "Data captured on leading edge of SCK"
576, "Data changed on leading edge of SCK"
577, "QSPI SCK clock frequency"
578, "QSPI Control Register 1"
579, "Configures the QSPI"
580, "QSPI disabled"
581, "QSPI enabled"
582, "PCSx delay to SCK transition time"
583, "QSPI delay after transmission time"
584, "QSPI Control Register 2"
585, "Configures the QSPI"
586, "QSPI interrupts disabled"
587, "QSPI interrupts enabled"
588, "Wraparound mode disabled"
589, "Wraparound mode enabled"
590, "Execution wraps to 0"
591, "Execution wraps to (NEWQP)"
592, "Last address in queue to be completed"
593, "First queue entry to be transfered first"
594, "QSPI Control Register 3"
595, "Configures the QSPI"
596, "Feedback path disabled"
597, "Feedback path enabled"
598, "HALTA/MODF interrupts disabled"
599, "HALTA/MODF interrupts enabled"
600, "HALT disabled"
601, "HALT enabled"
602, "QSPI Status Register"
603, "Contains QSPI status information"
604, "QSPI not finished"
605, "QSPI finished"
606, "Mode fault occured"
607, "QSPI not halted"
608, "QSPI halted"
609, "Pointer value to last completed command"
610, "Receive Data Ram"
611, "Holds data received by the QSPI from other peripherals."
612, "Transmit Data Ram"
613, "Holds data to be transmitted by the QSPI."
614, "Command Ram"
615, "Holds commands for the QSPI when in master mode."
616, "RAM Module Configuration Register"
617, "RAMMCR controls the Standby Ram configuration"
618, "Ram Test Register"
619, "Provides access to built in functional tests"
620, "Value selects the ram array test to be performed"
621, "RAMBAR may only be written once"
622, "RAMBAR may be written as desired"
623, "Ram Base Address and Status Register"
624, "Defines ram arrays base address and enable/disable status"
625, "Ram array base address"
626, "Ram array is enabled"
627, "Ram array is disabled"
628, "TPU Module Configuration Register"
629, "MCR controls the TPU configuration"
630, "Internal clocks running"
631, "Internal clocks shut down"
632, "Clock divisor is 1"
633, "Clock divisor is 2"
634, "Clock divisor is 4"
635, "Clock divisor is 8"
636, "TPU/RAM not in emulation mode"
637, "TPU/RAM in emulation mode"
638, "TCR2 pin is clock source for TCR2"
639, "TCR2 pin gates DIV8 source for TCR2"
640, "TPU running"
641, "TPU stopped"
642, "System clock/32 sources TCR1 prescaler"
643, "System clock/4 sources TCR1 prescaler"
644, "TPU Test Configuration Register"
645, "Configures/controls TPU built-in tests"
646, "uPC increments"
647, "TCR1 clocked externally via TCR2"
648, "No response"
649, "Run one TPU cycle"
650, "Assert scheduler end of time slot"
651, "No scan path"
652, "uPC scan path"
653, "Microinstruction scan path"
654, "Branch PLA scan path"
655, "uPC Breakpoint scan path"
656, "Scheduler PLA scan path"
657, "Channel breakpoint scan path"
658, "Normal memory map"
659, "Module at alternate location"
660, "Development Support Control Register"
661, "Development Support Control Register"
662, "Exit wait on T4 state"
663, "Enter wait on T4 state"
664, "Don't latch conditions"
665, "Latch conditions"
666, "Don't stop TCR's"
667, "Stop TCR's during halt"
668, "Ignore FREEZE"
669, "Freeze at end of current microcycle"
670, "Freeze at next time-slot boundary"
671, "Only latch pin state"
672, "Pin state, MRL, TDL latched"
673, "Break on uPC disabled"
674, "Break on uPC enabled"
675, "Break on CHAN disabled"
676, "Break on CHAN enabled"
677, "Break on host service latch disabled"
678, "Break on host service latch enabled"
679, "Break on link service latch disabled"
680, "Break on link service latch enabled"
681, "Break on MRL disabled"
682, "Break on MRL enabled"
683, "Break on TDL disabled"
684, "Break on TDL enabled"
685, "Development Support Status Register"
686, "Indicates if/why the TPU is stopped"
687, "Breakpoint not asserted"
688, "Breakpoint asserted"
689, "uPC breakpoint not asserted"
690, "uPC breakpoint asserted"
691, "CHAN breakpoint not asserted"
692, "CHAN breakpoint asserted"
693, "Service request breakpoint not asserted"
694, "Service request breakpoint asserted"
695, "TPU not frozen"
696, "TPU frozen"
697, "TPU Interrupt Configuration Register"
698, "Configures interrupt request level and vector base"
699, "TPU interrupt base vector value"
700, "Channel Interrupt Enable Register"
701, "Enables/disables channel interrupts"
702, "Channel 15 disabled"
703, "Channel 15 disabled"
704, "Channel 14 disabled"
705, "Channel 14 enabled"
706, "Channel 13 disabled"
707, "Channel 13 enabled"
708, "Channel 12 disabled"
709, "Channel 12 enabled"
710, "Channel 11 disabled"
711, "Channel 11 enabled"
712, "Channel 10 disabled"
713, "Channel 10 enabled"
714, "Channel 9 disabled"
715, "Channel 9 enabled"
716, "Channel 8 disabled"
717, "Channel 8 enabled"
718, "Channel 7 disabled"
719, "Channel 7 enabled"
720, "Channel 6 disabled"
721, "Channel 6 enabled"
722, "Channel 5 disabled"
723, "Channel 5 enabled"
724, "Channel 4 disabled"
725, "Channel 4 enabled"
726, "Channel 3 disabled"
727, "Channel 3 enabled"
728, "Channel 2 disabled"
729, "Channel 2 enabled"
730, "Channel 1 disabled"
731, "Channel 1 enabled"
732, "Channel 0 disabled"
733, "Channel 0 enabled"
734, "Channel Function Select Register 0"
735, "Controls the time function of four TPU channels"
736, "Encoded time function value"
737, "Channel Function Select Register 1"
738, "Channel Function Select Register 2"
739, "Channel Function Select Register 3"
740, "Host Sequence Register 0 (Channels 15-8)"
741, "Allows a bus master to select a mode of operation"
742, "Encoded host sequence value"
743, "Host Sequence Register 1 (Channels 7-0)"
744, "Host Service Request Register 0 (Channels 15-8)"
745, "Defines the type host interaction by channel"
746, "No host service"
747, "Type 1 host service"
748, "Type 2 host service"
749, "Type 3 host service"
750, "Host Service Request Register 1 (Channels 7-0)"
751, "Channel Priority Register 0 (Channels 15-8)"
752, "Assigns a priority level to channels"
753, "Channel disabled"
754, "Low priority"
755, "Middle priority"
756, "High priority"
757, "Channel Priority Register 1 (Channels 7-0)"
758, "Channel Interrupt Status Register"
759, "Provides interrupt status, one flag/channel"
760, "Interrupt not asserted"
761, "Interrupt asserted"
762, "Link Register"
763, "Used in generating link service requests"
764, "Link not asserted"
765, "Link asserted"
766, "Service Grant Latch Register"
767, "Ensures of same priority are serviced equally"
768, "Service not granted"
769, "Service granted"
770, "Decoded Channel Number Register"
771, "Indicates the channedl currently being serviced"
772, "Channel being serviced"
773, "Freeze GPT when FREEZE asserted"
774, "Stop the prescaler and pulse accumulator from incrementing"
775, "Increment the prescaler and clock synchronizers once when STOPP asserted"
776, "GPT Interrupt Configuration Register"
777, "Controls the interrupt operation of the GPT"
778, "Value specifies the highest priority interrupt"
779, "GPT interrupt base vector address"
780, "Parallel Data Direction Register"
781, "Controls the data direction for the Input Capture/Output Compare pins"
782, "Parallel Data Register"
783, "Holds the current state of the IC/OC pins."
784, "OC1 Action Mask Register"
785, "Mask value applied to an OC1 compare"
786, "Bit is not affected by OC1 compare"
787, "Bit is affected by OC1 compare"
788, "OC1 Action Data Register"
789, "Specifies data to be transferred to OC1M defined pins"
790, "Transfer 0 to OC1 pin if OC1M bit is set"
791, "Transfer 1 to OC1 pin if OC1M bit is set"
792, "Timer Counter"
793, "Free running timer value"
794, "Pulse Accumulator Control Register"
795, "Configures the pulse accumulator"
796, "PAI pin state"
797, "Pulse accumulator disabled"
798, "Pulse accumulator enabled"
799, "External event counting"
800, "Gated time accumulation"
801, "PAI falling edge increments counter/(PAI=0 inhibits counter) PAMOD=0(1)"
802, "PAI rising edge increments counter/(PAI=1 inhibits counter) PAMOD=0(1)"
803, "PCLK pin state"
804, "OC5 function enabled"
805, "IC4 function enabled"
806, "System clock divided by 512"
807, "Accumualtor clocked by clock used for TCNT"
808, "Accumualtor clocked by TOF flag from TCNT"
809, "Accumualtor clocked by external clock PCLK"
810, "Pulse Accumulator Counter"
811, "Holds count of external events or gated time accumulation"
812, "Input Capture Register 1"
813, "Latched value of TCNT"
814, "Input Capture Register 2"
815, "Input Capture Register 3"
816, "Output Compare Register 1"
817, "Holds an output compare value (or general storage)"
818, "Output Compare Register 2"
819, "Output Compare Register 3"
820, "Output Compare Register 4"
821, "Input Capture Register 4/Output Compare Register 5"
822, "IC4 holds the latched value of TCNT/OC5 provides an output compare value"
823, "Timer Control Register 1"
824, "Configures the automatic actions for OC2-4"
825, "Output compare value"
826, "Output action value"
827, "Timer Control Register 2"
828, "Configures input capture mode"
829, "Capture disabled"
830, "Capture on rising edge"
831, "Capture on falling edge"
832, "Capture on rising and falling edge"
}
