/* System Configuration Register Bit Definitions */

#define S3C2510_SYSCFG_CPLLREN          0x80000000          /* CPLLCON Register Enable */
#define S3C2510_SYSCFG_SPLLREN          0x40000000          /* SPLLCON Register Enable */
#define S3C2510_SYSCFG_UPLLREN          0x20000000          /* UPLLCON Register Enable */
#define S3C2510_SYSCFG_PPLLREN          0x10000000          /* PPLLCON Register Enable */
#define S3C2510_SYSCFG_CPLLCE           0x08000000          /* CPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_SPLLCE           0x04000000          /* SPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_UPLLCE           0x02000000          /* UPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_PPLLCE           0x01000000          /* PPLL Clock Enable during Configuration */
#define S3C2510_SYSCFG_BIG              0x00010000          /* Big Endian */
#define S3C2510_SYSCFG_REMAP            0x00000100          /* Remap Enable */
#define S3C2510_SYSCFG_HCLKODIS         0x00000010          /* HCLKO Output Disable */
#define S3C2510_SYSCFG_ARBR             0x00000002          /* Round-Robin Priority */
#define S3C2510_SYSCFG_ARBF             0x00000001          /* Fixed Priority */
#define S3C2510_SYSCFG_ARBC             0x00000000          /* Conventional Round-Robin Priority.*/

#define SYSCFG  (0xF0000000+0x0000)
#define S3C2510_CLKCON   (0xF0000000+0x00000008)
#define S3C2510_PCLKDIS  (0xF0000000+0x0000000C)
#define S3C2510_INTINTMASK   (0xF0000000+0x00140008) 
#define S3C2510_EXTINTMASK   (0xF0000000+0x0014000C)
#define S3C2510_MUXBCON   (0xF0000000+0x00010020) 
#define S3C2510_WAITCON   (0xF0000000+0x00010024)
#define S3C2510_SDRAMCFG1 (0xF0000000+0x00020004)
#define S3C2510_SDRAMCFG2 (0xF0000000+0x00020008) 
#define S3C2510_INT_MASK_INTERNAL       0xFFFFFFFF
#define S3C2510_INT_MASK_EXTERNAL       0x8000003F
#define S3C2510_MUXBCON_VAL 0x006DB6DB
#define S3C2510_WAITCON_VAL 0x00FF0000
#define S3C2510_SDRAMCFG1_INIT_PALL     0x00000001    
#define S3C2510_SDRAMCFG1_INIT_MRS      0x00000002
#define S3C2510_SDRAMCFG1_INIT_NORMAL   0x00000000      /* Normal Operation */

#define rSYSCFG   (S3C2510_SYSCFG_CPLLREN |S3C2510_SYSCFG_SPLLREN |S3C2510_SYSCFG_UPLLREN |S3C2510_SYSCFG_ARBF)

/* SDRAM Configuration Register 1 Bit Definitions */

#define S3C2510_SDRAMCFG0_VAL           0x00058AAC          /* Init Value for SDRAM */

#define SDRAM_INIT_BASE                 (0xF0000000+0x00020000)

#define S3C2510_B0CON                   (0xF0000000+0x00010000)  /* Bank 0 Control Register */
#define S3C2510_B1CON                   (0xF0000000+0x00010004)  /* Bank 1 Control Register */

#define S3C2510_B0CON_VAL 		0x850A1111
#define S3C2510_B1CON_VAL 		0x8514E488



        .align
        .text
        .global _init_ram,hardware_init_hook
hardware_init_hook:
_init_ram:              
  	ldr   	r0, =0xF0000000
  	ldr   	r1, =rSYSCFG
  	str   	r1, [r0]

  /* Initialize Clock Control Register. */
        LDR     r2, =S3C2510_CLKCON
        MOV     r1, #0x0
        STR     r1, [r2]
        
  /* Disable peripherals. */
        LDR     r2, =S3C2510_PCLKDIS
        MOV     r1, #0x0                                        
        STR     r1, [r2] 
  
  /* Disable individual interrupts in the interrupt controller. */
        LDR     r2, =S3C2510_INTINTMASK
        LDR     r1, =S3C2510_INT_MASK_INTERNAL
        STR     r1, [r2]                                /* disable all internal interrupt */
        LDR     r2, =S3C2510_EXTINTMASK
        LDR     r1, =S3C2510_INT_MASK_EXTERNAL
        STR     r1, [r2]                                /* disable all external interrupt */      

 /* set reset memory map */
  	LDR     r0, =SDRAM_INIT_BASE
      	LDR     r1, =S3C2510_SDRAMCFG0_VAL
  	STR     r1, [r0]                  
  	
 /* MRS command to the SDRAM. */
        LDR     r2, =S3C2510_SDRAMCFG1
        MOV     r1, #S3C2510_SDRAMCFG1_INIT_MRS
        STR     r1, [r2]
        
 /* Controller enters the normal mode. */
        LDR     r2, =S3C2510_SDRAMCFG1
        MOV     r1, #S3C2510_SDRAMCFG1_INIT_NORMAL
        STR     r1, [r2]   
  
  /* Initialize Muxed Bus Control Register. */
        LDR     r2, =S3C2510_MUXBCON
        LDR     r1, =S3C2510_MUXBCON_VAL                     
        STR     r1, [r2]
        
  /* Initialize Wait Control Register. */
        LDR     r2, =S3C2510_WAITCON
        LDR     r1, =S3C2510_WAITCON_VAL                     
        STR     r1, [r2]
        
  /* Drain write-buffer. */
        LDR     r1, =0x0000000                          
        MCR     p15, 0, r1, c7, c10, 2                   /* drain write-buffer */
  
  /* Flush (invalidate) both caches. */
        MOV     r1, #0                                   /* data SBZ */
        MCR     p15, 0, r1, c7, c5, 0                    /* Flush (invalidate) all I-cache */
        MCR     p15, 0, r1, c7, c6, 0                    /* Flush (invalidate) all D-cache */
 
  /* Initialize Bank Control Register. */
        
  /* Bank 0 - Flash (Application Flash) */
  	LDR     r2, =S3C2510_B0CON
  	LDR     r1, =S3C2510_B0CON_VAL                     
  	STR     r1, [r2]
        
  /* Bank 1 - ROM (Boot ROM) */
        LDR     r2, =S3C2510_B1CON
        LDR     r1, =S3C2510_B1CON_VAL                     
        STR     r1, [r2]
  	mov     pc,lr                     /*  return to caller */
 
