<?xml version="1.0" standalone="no" ?>
<!--  ARM Register Configuration File -->
<CPU type="ZAC2MMU" family="ARM" immr="true" description="this is the ZAC2MMU cp15 register configration file">
    <Group name="CP15" description="Gerneral CP15 Registers list" id="0" modemask="0x8f0000">
        <Register name="CPUID" memorymap="false" id="0x8f0000" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="Main ID Register" signed="false" />
        <Register name="CACHECFG" memorymap="false" id="0x8f0040" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="Cache Type Register" signed="false" />
        <Register name="CONTROL" memorymap="false" id="0x8f0001" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Cache and TLBs Control Register" signed="false" />
        <Register name="TLBASE" memorymap="false" id="0x8f0002" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="TLB Page Directory Base Address Register" signed="false" />
        <Register name="DAC" memorymap="false" id="0x8f0003" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="TLB Domain Access Control Register" signed="false" />
        <Register name="DASTAT" memorymap="false" id="0x8f0005" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Data Abort Status Register" signed="false" />
        <Register name="IASTAT" memorymap="false" id="0x8f0045" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Instruction Abort Status Register" signed="false" />
        <Register name="DAADDR" memorymap="false" id="0x8f0006" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Data Abort Address Register" signed="false" />
        <Register name="DCACHELOCK" memorymap="false" id="0x8f0009" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Data Cache Lock Register" signed="false" />
        <Register name="ICACHELOCK" memorymap="false" id="0x8f0049" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Instruction Cache Lock Register" signed="false" />
        <Register name="DTLBLOCK" memorymap="false" id="0x8f000a" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Data TLB lock Register" signed="false" />
        <Register name="ITLBLOCK" memorymap="false" id="0x8f004a" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Instruction TLB lock Register" signed="false" />
        <Register name="REMAP" memorymap="false" id="0x8f000d" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="First 32MByte Range Re-map Register" signed="false" />
        <Register name="SFCR" memorymap="false" id="0x8f000f" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="Special Features Control Register" signed="false" />
    </Group>
</CPU>
