
#setMMRBaseAddr 0xFF400000
writereg	MBAR	0xFF400000

# change internal MMR base from 0xff400000 (reset value) to 0xe0000000
writemem.l 0xff400000 0xe0000000 # IMMRBAR = 0xe0000000

#setMMRBaseAddr 0xe0000000
writereg	MBAR	0xe0000000


##############################################
# System Configuration - Local Access Windows 
##############################################

# Local Bus Local Access Windows
#################################
# WINDOW 0 - FLASH
writemem.l 0xe0000020 0xff000000 # LBLAWBAR0  - begining at 0xff000000 
writemem.l 0xe0000024 0x80000017 # LBLAWAR0   - enable, size = 16MB 

# WINDOW 1 - board BCSRs
writemem.l 0xe0000028 0xf8000000 # LBLAWBAR1  - begining at 0xf8000000
writemem.l 0xe000002c 0x8000000e # LBLAWAR1   - enable, size = 32MB 

# WINDOW 3 - PIBs
writemem.l 0xe0000038 0xf8008000 # LBLAWBAR3  - begining at 0xf8008000
writemem.l 0xe000003c 0x8000000f # LBLAWAR3   - enable, size = 64KB

# PCI Local Access Windows
#################################
# WINDOW 0
writemem.l 0xe0000060 0x80000000 # PCILAWBAR0 - begining at 0x80000000
writemem.l 0xe0000064 0x8000001c # PCILAWAR0  - enable, size = 512MB

# DDR Local Access Windows
#################################
# WINDOW 0 - 1st DDR SODIMM
writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000
writemem.l 0xe00000a4 0x8000001a # DDRLAWAR0  - enable, size = 128MB

##############################################
# DDR Controller Configuration
##############################################

#CLK_CNTL
# bit 0 = 1 - SS_EN address and command sent to the DDR source synchronously
# bit 5-7 = 2 - CLK_ADJST
writemem.l 0xE0002130 0x02000000

# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002000 0x00000007 ; 0x00000000 - 0x07FFFFFF # first 128MB

# CS0_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 21 - 23 = 0 - ROW_BITS_CS_0 13 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 10 columns
writemem.l 0xe0002080 0x80840102

# TIMING_CFG_3
# bit 13 - 15 = 0 - EXT_REFREC 0 Clocks
writemem.l 0xe0002100 0x00000000

# TIMING_CONFIG_1
# bit 1-3 = 2 - PRETOACT precharge activate interval 2 clock cycles
# bit 4-7 = 6 - ACTTOPRE activate to precharge interval 6 clock cycles
# bit 9-11 = 2 = ACTTORW activate to r/w interval 2 clock cycles 
# bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles
# bit 16 - 19 = 6 - REFREC refresh recovery time 14 clock cycles 
# bit 21 - 23 = 2 - WRREC data to precharge interval 2 clock cycles 
# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
# bit 29 - 31 = 2 - WRTORD write data to read command interval 2 clock cycles
writemem.l 0xe0002108 0x26256222

# TIMING_CONFIG_2
# bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay
writemem.l 0xe000210C 0x0f9028c7

# TIMING_CFG_0
# bit 9-11 = 2 - ACT_PD_EXIT Active powerdown exit timing 2 Clocks
# bit 13-15 = 2 - PRE_PD_EXIT Precharge powerdown exit timing 2 Clocks
# bit 20-32 = 2 - ODT_PD_EXIT ODT powerdown exit timing 8 Clocks
# bit 28-31 = 2 -  MRS_CYC Mode register set cycle time 2 Clocks
writemem.l 0xE0002104 0x00220802

# temporary disable the memory interface for reconfiguration
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 3 - SDRAM_TYPE DDR2 SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l 0xe0002110 0x43080000

# DDR_SDRAM_CFG_2
# bit 0 = 0 - FRC_SR normal self refresh 
# bit 4-5 = 0 - DQS_CFG Only true DQS signals are used
# bit 9-10 = 2 - ODT_CFG Assert ODT to internal IOs only during reads to DRAM
# bit 16-19 = 1 - NUM_PR 1 refresh will be issued at a time
# bit 0 = 0 - D_INIT no data initialization in progress
writemem.l 0xE0002114 0x00401000

# DDR_SDRAM_MODE
# bit 0 - 15 = 0x2000  - ESDMODE
# bit 16 - 31 = 0x0162 - SDMODE 
writemem.l 0xe0002118 0x44400232

# DDR_SDRAM_MODE_2
# bit 0 - 15 = 0x8000  - ESDMODE2
# bit 16 - 31 = 0xc000 - ESDMODE3
writemem.l 0xE000211C 0x8000c000
		

# DDR_SDRAM_INTERVAL
# bit 2 - 15 = 0x45b0 - REFINT 800 Clocks
# bit 18 - 31 = 0x0100  - BSTOPRE 100 Clocks
writemem.l 0xe0002124 0x03200064


#delay before enable
sleep 300

# enable the DDR memory controller
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic enabled
writemem.l 0xe0002110 0xc3080000


##############################################
# Local Bus Interface (LBIU) Configuration
##############################################

#LCRR
writemem.l 0xE00050d4 0x00010002

# CS0 - 16MB FLASH 
writemem.l 0xe0005000 0xff001001 # BR0 base address at 0xFF000000, port size 16 bit, GPCM, valid
writemem.l 0xe0005004 0xff006ff7 # OR0 16MB flash size, 15 w.s., timing relaxed

# CS1 - board BCSRs
writemem.l 0xe0005008 0xf8000801 # BR1 base address at 0xF8000000, port size 8 bit, GPCM, valid
writemem.l 0xe000500c 0xffffe9f7 # OR1 32KB size, 15 w.s., timing relaxed

# CS2 - 32KB PIB
writemem.l 0xe0005014 0xFFFFE9f7 # OR2 32KB size
writemem.l 0xe0005010 0xF8008801 # BR2 base address at 0xF8008000, port size 8 bit, GPCM, valid

# CS3 - 32KB PIB
writemem.l 0xe000501c 0xFFFFE9f7 # OR3 32KB size
writemem.l 0xe0005018 0xF8010801 # BR2 base address at 0xF0010000, port size 8 bit, GPCM, valid

# LBCR - local bus enable
writemem.l 0xe00050d0 0x00000000

# LCRR
# bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles 
# bit 28 - 31 = 0x0010  - CLKDIV - system clock:memory bus clock = 2
writemem.l 0xe00050d4 0x00030002

# MRTPR - refresh timer prescaler
writemem.l 0xe0005084 0x20000000 

# System configuration registers

writemem.l 0xe0000114 0x00000000 # SICRL

ANDmem.l 0xe0000118 0x00000003 # SICRH

#DDRCDR
writemem.l 0xE0000128 0x73000002

writereg MSR 0x3000 # machine check enable, exception vectors at 0x0000_0000


ANDMem.l 0xE0000800 0x00300000 # ACR - Enable Core

#unlock flash in BCSR9 - bit 4 FLASHPRT
ANDmem.l 0xf8000008 0xFFF7FFFF
