<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<CPU type="PPCE500" family="PPCE500" immr="false" description="this is the PPC register configration file">
    <Group name="Instruction-Accessible Regs" description="Instruction-Accessible Registers, User-level" >
        <Register name="CTR" memorymap="False" id="0x0000009" bytes="4" width="32" reservalue="0x0000" unused="0xFFFFFFFF" bitable="False" rdable="true" wrable="true" description="CTR" signed="False" />
        <Register name="LR" memorymap="False" id="0x0000008" bytes="4" width="32" reservalue="0x0000" unused="0xFFFFFFFF" bitable="False" rdable="true" wrable="true" description="LR" signed="False" />
        <Register name="XER" memorymap="False" id="0x0000001" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="XER" signed="False">
            <Field name="SO" size="1" location="0" bitable="false" minval="0" maxval="1" description="Summary Overflow (SO) - The summary overflow bit is set whenever an instruction sets the overflow bit (OV) to indicate overflow and remains set until software clears it. It is not altered by compare instructions or other instructions that cannot overflow." />
            <Field name="OV" size="1" location="1" bitable="false" minval="0" maxval="1" description="Overflow (OV) - The overflow bit is set to indicate that an overflow has occurred during execution of an instruction. Integer and subtract instructions have OE=1 set OV if the carry out of bit 0 is not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by compare instructions or other instructions that cannot overflow." />
            <Field name="CA" size="1" location="2" bitable="false" minval="0" maxval="1" description="Carry (CA) - In general, the carry bit is set to indicate that a carry out of bit 0 occurred during execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract from extended instructions set CA to one if there is a carry out of bit 0, and clear it otherwise. The CA bit is not altered by compare instructions or other instructions that cannot carry, except that shift right algebraic instructions set the CA bit to indicate whether any &apos;1&apos; bits have been shifted out of a negative quantity." />
            <Field name="BYTES" size="7" location="25" bitable="false" minval="0" maxval="1" description="This field specifies the number of bytes to be transferred by a load string word indexed (lswx) or store string word indexed (stswx) instruction." />
        </Register>
        <Register name="SPEFSCR" memorymap="false" id="0x0000200" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="SPEFSCR" signed="false">
            <Field name="SOVH" size="1" location="0" bitable="false" minval="0" maxval="1" description="Summary integer overflow high. Set whenever an instruction (except mtspr) sets OVH. SOVH remains set until it is cleared by an mtspr[SPEFSCR]." />
            <Field name="OVH" size="1" location="1" bitable="false" minval="0" maxval="1" description="Integer overflow high. An overflow occurred in the upper half of the register while executing a SPE integer instruction" />
            <Field name="FGH" size="1" location="2" bitable="false" minval="0" maxval="1" description="Embedded floating-point guard bit high. Floating-point guard bit from the upper half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow." />
            <Field name="FXH" size="1" location="3" bitable="false" minval="0" maxval="1" description="Embedded floating-point sticky bit high. Floating bit from the upper half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow or floating-point underflow." />
            <Field name="FINVH" size="1" location="4" bitable="false" minval="0" maxval="1" description="Embedded floating-point invalid operation error high. Set when an input value on the high side is a NaN, Inf, or Denorm. Also set on a divide if both the dividend and divisor are zero." />
            <Field name="FDBZH" size="1" location="5" bitable="false" minval="0" maxval="1" description="Embedded floating-point divide by zero error high. Set if the dividend is non-zero and the divisor is zero." />
            <Field name="FUNFH" size="1" location="6" bitable="false" minval="0" maxval="1" description="Embedded floating-point underflow error high" />
            <Field name="FOVFH" size="1" location="7" bitable="false" minval="0" maxval="1" description="Embedded floating-point overflow error high" />
            <Field name="FINXS" size="1" location="10" bitable="false" minval="0" maxval="1" description="Embedded floating-point inexact sticky. FINXS = FINXS | FGH | FXH | FG | FX" />
            <Field name="FINVS" size="1" location="11" bitable="false" minval="0" maxval="1" description="Embedded floating-point invalid operation sticky. Location for software to use when implementing true IEEE floating point." />
            <Field name="FDBZS" size="1" location="12" bitable="false" minval="0" maxval="1" description="Embedded floating-point divide by zero sticky. FDBZS = FDBZS | FDBZH | FDBZ" />
            <Field name="FUNFS" size="1" location="13" bitable="false" minval="0" maxval="1" description="Embedded floating-point underflow sticky. Storage location for software to use when implementing true IEEE floating point." />
            <Field name="FOVFS" size="1" location="14" bitable="false" minval="0" maxval="1" description="Embedded floating-point overflow sticky. Storage location for software to use when implementing true IEEE floating point." />
            <Field name="MODE" size="1" location="15" bitable="false" minval="0" maxval="1" description="Embedded floating-point mode (read-only on e500)" />
            <Field name="SOV" size="1" location="16" bitable="false" minval="0" maxval="1" description="Integer summary overflow. Set whenever an SPE instruction (except mtspr) sets OV. SOV remains set until it is cleared by mtspr[SPEFSCR]." />
            <Field name="OV" size="1" location="17" bitable="false" minval="0" maxval="1" description="Integer overflow. An overflow occurred in the lower half of the register while a SPE integer instruction is being executed." />
            <Field name="FG" size="1" location="18" bitable="false" minval="0" maxval="1" description="Embedded floating-point guard bit. Floating-point guard bit from the lower half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow." />
            <Field name="FX" size="1" location="19" bitable="false" minval="0" maxval="1" description="Embedded floating-point sticky bit. Floating bit from the lower half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow or floating-point underflow." />
            <Field name="FINV" size="1" location="20" bitable="false" minval="0" maxval="1" description="Embedded floating-point invalid operation error. Set when an input value on the high side is a NaN, Inf, or Denorm. Also set on a divide if both the dividend and divisor are zero." />
            <Field name="FDBZ" size="1" location="21" bitable="false" minval="0" maxval="1" description="Embedded floating-point divide by zero error. Set of the dividend is non-zero and the divisor is zero." />
            <Field name="FUNF" size="1" location="22" bitable="false" minval="0" maxval="1" description="Embedded floating-point underflow error" />
            <Field name="FOVF" size="1" location="23" bitable="false" minval="0" maxval="1" description="Embedded floating-point overflow error" />
            <Field name="FINXE" size="1" location="25" bitable="false" minval="0" maxval="1" description="Embedded floating-point inexact enable" />
            <Field name="FINVE" size="1" location="26" bitable="false" minval="0" maxval="1" description="Embedded floating-point invalid operation/input error exception enable" />
            <Field name="FDBZE" size="1" location="27" bitable="false" minval="0" maxval="1" description="Embedded floating-point divide-by-zero exception enable" />
            <Field name="FUNFE" size="1" location="28" bitable="false" minval="0" maxval="1" description="Embedded floating-point underflow exception enable" />
            <Field name="FOVFE" size="1" location="29" bitable="false" minval="0" maxval="1" description="Embedded floating-point overflow exception enable" />
            <Field name="FRMC" size="2" location="30" bitable="false" minval="0" maxval="1" description="Embedded floating-point rounding mode control" />
        </Register>
    </Group>
    <Group name="User General SPR" description="User General SPR, User level" >
    	<Register name="USPRG0" alias="vrsave" memorymap="false" id="0x0000100" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="USPRG0" signed="false" />
        <Register name="USPRG3" memorymap="false" id="0x0000103" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="USPRG0" signed="false" />
        <Register name="USPRG4" memorymap="false" id="0x0000104" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="USPRG4" signed="false" />
        <Register name="USPRG5" memorymap="false" id="0x0000105" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="USPRG5" signed="false" />
        <Register name="USPRG6" memorymap="false" id="0x0000106" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="USPRG6" signed="false" />
        <Register name="USPRG7" memorymap="false" id="0x0000107" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="USPRG7" signed="false" />
    </Group>
    <Group name="Time-Base Registers" description="Time-Base Registers, User level" >
    	<Register name="TBL" memorymap="false" id="0x000010c" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="TBL" signed="false" />
        <Register name="TBU" memorymap="false" id="0x000010d" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="TBU" signed="false" />
    </Group>
    <Group name="Configuration Registers" description="Configuration Registers, Supervisor level" >
	<Register name="EPIR" alias="svrzeppo" memorymap="false" id="0x000011E" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="PVR" signed="false" />
        <Register name="PVR" memorymap="false" id="0x000011F" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="PVR" signed="false">
            <Field name="VERSION" size="16" location="0" bitable="false" minval="0" maxval="1" description="A 16-bit number that identifies the version of the processor and of the PowerPC architecture." />
            <Field name="REVISION" size="16" location="16" bitable="false" minval="0" maxval="1" description="A 16-bit number that distinguishes between various releases of a particular version." />
        </Register>
        <Register name="NPIDR" memorymap="false" id="0x0000205" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="Nexus processor ID register" signed="false" />	
    </Group>
    <Group name="Interrupt Registers" description="Interrupt Registers, Supervisor level" >
    	<Register name="IVPR" memorymap="false" id="0x000003F" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVPR" signed="false">
            <Field name="Interrupt vector offset" size="16" location="0" bitable="false" minval="0" maxval="1" description="-" />
        </Register>
        <Register name="SRR0" memorymap="false" id="0x000001A" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SRR0" signed="false" />
        <Register name="SRR1" memorymap="false" id="0x000001B" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SRR1" signed="false" />
        <Register name="CSRR0" memorymap="false" id="0x000003A" bytes="4" width="32" reservalue="58" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CSRR0" signed="false" />
        <Register name="CSRR1" memorymap="false" id="0x000003B" bytes="4" width="32" reservalue="58" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CSRR1" signed="false" />
        <Register name="MCSRR0" memorymap="false" id="0x000023A" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="MCSRR0" signed="false" />
        <Register name="MCSRR1" memorymap="false" id="0x000023B" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="MCSRR1" signed="false" />
    `	<Register name="ESR" memorymap="false" id="0x000003E" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="ESR" signed="false">
            <Field name="PIL" size="1" location="4" bitable="false" minval="0" maxval="1" description="Illegal instruction exception" />
            <Field name="PPR" size="1" location="5" bitable="false" minval="0" maxval="1" description="Privileged instruction exception" />
            <Field name="PTR" size="1" location="6" bitable="false" minval="0" maxval="1" description="Trap exception" />
            <Field name="ST" size="1" location="8" bitable="false" minval="0" maxval="1" description="Store operation" />
            <Field name="DLK0" size="1" location="10" bitable="false" minval="0" maxval="1" description="Cache locking. Settings are implementation-dependent." />
            <Field name="ILK" size="1" location="11" bitable="false" minval="0" maxval="1" description="Set when a DSI occurs because icbtl or icblc is executed in user mode&#x0A;(MSR[PR] = 1) and MSR[UCLE] = 0." />
            <Field name="AP" size="2" location="12" bitable="false" minval="0" maxval="1" description="Reserved" />
            <Field name="BO" size="1" location="14" bitable="false" minval="0" maxval="1" description="Byte-ordering exception" />
            <Field name="SPE" size="1" location="24" bitable="false" minval="0" maxval="1" description="SPE exception bit (e500-specific)." />
        </Register>
        <Register name="MCSR" memorymap="false" id="0x000023C" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MCSR" signed="false">
            <Field name="MCP" size="1" location="0" bitable="false" minval="0" maxval="1" description="Machine check input pin" />
            <Field name="ICPERR" size="1" location="1" bitable="false" minval="0" maxval="1" description="Instruction cache parity error" />
            <Field name="DCP_PERR" size="1" location="2" bitable="false" minval="0" maxval="1" description="Data cache push parity error" />
            <Field name="DCPERR" size="1" location="3" bitable="false" minval="0" maxval="1" description="Data cache parity error" />
            <Field name="GL_CI" size="1" location="15" bitable="false" minval="0" maxval="1" description="Set when a guarded load or cache-inhibited stwcx.&#x0A;provokes a parity error in the cache (ICPERR or DCPERR). In this case, the address saved in MCSRR0 is the address&#x0A;after the instruction that caused the error." />
            <Field name="ABIST_IC" size="1" location="16" bitable="false" minval="0" maxval="1" description="Abist instruction cache error" />
            <Field name="ABIST_DC" size="1" location="17" bitable="false" minval="0" maxval="1" description="Abist data cache error" />
            <Field name="ABIST_ITLB" size="1" location="18" bitable="false" minval="0" maxval="1" description="Abist instruction TLB error" />
            <Field name="ABIST_DTLB" size="1" location="19" bitable="false" minval="0" maxval="1" description="Abist data TLB error" />
            <Field name="ABIST_L2TLB" size="1" location="20" bitable="false" minval="0" maxval="1" description="Abist L2 TLB error" />
            <Field name="ABIST_TLB1" size="1" location="21" bitable="false" minval="0" maxval="1" description="Abist TLB1 error" />
            <Field name="ABIST_BTB" size="1" location="22" bitable="false" minval="0" maxval="1" description="Abist BTB error" />
            <Field name="BUS_IAERR" size="1" location="24" bitable="false" minval="0" maxval="1" description="Bus. Instruction address error" />
            <Field name="BUS_RAERR" size="1" location="25" bitable="false" minval="0" maxval="1" description="Bus. Read address error" />
            <Field name="BUS_WAERR" size="1" location="26" bitable="false" minval="0" maxval="1" description="Bus. Write address error" />
            <Field name="BUS_IBERR" size="1" location="27" bitable="false" minval="0" maxval="1" description="Bus. Instruction data bus error" />
            <Field name="BUS_RBERR" size="1" location="28" bitable="false" minval="0" maxval="1" description="Bus. Read data bus error" />
            <Field name="BUS_WBERR" size="1" location="29" bitable="false" minval="0" maxval="1" description="Bus. Write bus error" />
            <Field name="BUS_IPERR" size="1" location="30" bitable="false" minval="0" maxval="1" description="Bus - instruction parity error" />
            <Field name="BUS_RPERR" size="1" location="31" bitable="false" minval="0" maxval="1" description="Bus - read parity error" />
        </Register>
        <Register name="MCAR" memorymap="false" id="0x000023D" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="MCAR" signed="false" />
        <Register name="DEAR" memorymap="false" id="0x000003D" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="DEAR" signed="false" />
    	<Register name="IVOR0" memorymap="false" id="0x0000190" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR0" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Critical input" />
        </Register>
        <Register name="IVOR1" memorymap="false" id="0x0000191" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR1" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Machine check" />
        </Register>
        <Register name="IVOR2" memorymap="false" id="0x0000192" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR2" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Data storage" />
        </Register>
        <Register name="IVOR3" memorymap="false" id="0x0000193" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR3" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Instruction storage" />
        </Register>
        <Register name="IVOR4" memorymap="false" id="0x0000194" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR4" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : External input" />
        </Register>
        <Register name="IVOR5" memorymap="false" id="0x0000195" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR5" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Alignment" />
        </Register>
        <Register name="IVOR6" memorymap="false" id="0x0000196" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR6" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Program" />
        </Register>
        <Register name="IVOR7" memorymap="false" id="0x0000197" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR7" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Floating-point unavailable (not supported on the e500)" />
        </Register>
        <Register name="IVOR8" memorymap="false" id="0x0000198" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR8" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : System call" />
        </Register>
        <Register name="IVOR9" memorymap="false" id="0x0000199" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR9" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type :Auxiliary processor unavailable (not supported on the e500)" />
        </Register>
        <Register name="IVOR10" memorymap="false" id="0x000019A" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR10" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type :Decrementer" />
        </Register>
        <Register name="IVOR11" memorymap="false" id="0x000019B" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR11" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Fixed-interval timer interrupt" />
        </Register>
        <Register name="IVOR12" memorymap="false" id="0x000019C" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR12" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Watchdog timer interrupt" />
        </Register>
        <Register name="IVOR13" memorymap="false" id="0x000019D" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR13" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Data TLB error" />
        </Register>
        <Register name="IVOR14" memorymap="false" id="0x000019E" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR14" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Instruction TLB error" />
        </Register>
        <Register name="IVOR15" memorymap="false" id="0x000019F" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR15" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type : Debug" />
        </Register>
        <Register name="IVOR32" alias="mi_gra" memorymap="false" id="0x0000210" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR32" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type :(e500-specific) SPE APU unavailable" />
        </Register>
        <Register name="IVOR33" alias="eibadr" memorymap="false" id="0x0000211" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR33" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type :(e500-specific) SPE floating-point data exception" />
        </Register>
        <Register name="IVOR34" memorymap="false" id="0x0000212" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR34" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type :(e500-specific) SPE floating-point round exception" />
        </Register>
        <Register name="IVOR35" memorymap="false" id="0x0000213" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IVOR35" signed="false">
            <Field name="Interrupt vector offset" size="14" location="16" bitable="false" minval="0" maxval="1" description="Interrupt type :(e500-specific) Performance monitor" />
        </Register>
    </Group>
    <Group name="MMU Control and Status" description="MMU Control and Status, Supervisor level" >
    	<Register name="MMUCSR0" memorymap="false" id="0x00003F4" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MMUCSR0" signed="false">
            <Field name="IL1MMU_FI" size="1" location="27" bitable="false" minval="0" maxval="1" description="Instruction L1 MMU (TLB) flash invalidate (write to 1 to invalidate)" />
            <Field name="DL1MMU_FI" size="1" location="28" bitable="false" minval="0" maxval="1" description="Data L1 MMU (TLB) flash invalidate (write to 1 to invalidate)" />
            <Field name="L2TLB0_FI" size="1" location="29" bitable="false" minval="0" maxval="1" description="TLB0 flash invalidate (write to 1 to invalidate)" />
            <Field name="L2TLB1_FI" size="1" location="30" bitable="false" minval="0" maxval="1" description="TLB1 flash invalidate (write to 1 to invalidate)0No flash invalidate. Writing a 0 to this bit during an invalidation operation is ignored." />
        </Register>
    	<Register name="MAS0" memorymap="false" id="0x0000270" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MAS0" signed="false">
            <Field name="TLBSEL" size="1" location="3" bitable="false" minval="0" maxval="1" description="Selects TLB for access." />
            <Field name="ESEL" size="4" location="12" bitable="false" minval="0" maxval="1" description="For the e500, ESEL serves as the way select for the corresponding TLB as follows: When TLBSEL = 00 (TLB0 selected), only bit 47 is used (and bits 44-46 should be cleared). This bit selects between way 0 and way 1 of TLB0. EA bits 45-51 are used to index into the TLB to further select the entry for the operation.&#x0A;When TLBSEL = 01 (TLB1 selected), all four bits are used to select one of 16 entries in the array." />
            <Field name="NV" size="1" location="31" bitable="false" minval="0" maxval="1" description="For the e500 implementation, this bit is the next victim bit value to be written to TLB0[NV] on execution of tlbwe. NV is also updated on TLB error exceptions (misses), tlbsx hit and miss cases,&#x0A;and on execution of tlbre. NV is updated with the calculated next victim bit for TLB0, based on the round-robin replacement&#x0A;algorithm. Note that this field is not defined for operations that specify TLB1 (when TLBSEL = 01)." />
        </Register>
        <Register name="MAS1" memorymap="false" id="0x0000271" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MAS1" signed="false">
            <Field name="V" size="1" location="0" bitable="false" minval="0" maxval="1" description="TLB valid bit." />
            <Field name="IPROT" size="1" location="1" bitable="false" minval="0" maxval="1" description="Invalidate protect. Set to protect this TLB entry from invalidate operations due the execution of tlbivax (TLB1 only). Note that not all TLB arrays are necessarily protected from invalidation with IPROT. Arrays that support invalidate protection are denoted as such in the TLB configuration registers." />
            <Field name="TID" size="8" location="8" bitable="false" minval="0" maxval="1" description="For the e500, 8-bit field that defines the process ID for this TLB entry. TID is compared with the current process IDs of the three effective address to be translated. A TID value of 0 defines an entry as global and matches with all process IDs." />
            <Field name="TS" size="1" location="19" bitable="false" minval="0" maxval="1" description="Translation space. This bit is compared with the IS or DS fields of the MSR (depending on the type of access) to determine if this TLB entry may be used for translation." />
            <Field name="TSIZE" size="4" location="20" bitable="false" minval="0" maxval="1" description="Translation size. This 4-bit field defines the page size of the TLB entry. For TLB arrays that contain fixed-size TLB entries, this field is ignored. For variable page size TLB arrays, the page size is 4^TSIZE Kbytes. Note that the Motorola Book E standard supports all 16 page sizes defined in Book E." />
        </Register>
        <Register name="MAS2" memorymap="false" id="0x0000272" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MAS2" signed="false">
            <Field name="EPN" size="20" location="0" bitable="false" minval="0" maxval="1" description="Effective page number. Depending on page size, only the bits associated with a page boundary are valid. Bits that represent offsets within a page are ignored and should be zero." />
            <Field name="SHAREN" size="1" location="22" bitable="false" minval="0" maxval="1" description="For e500 implementation, enables cache fills to use shared cache state." />
            <Field name="X0" size="1" location="25" bitable="false" minval="0" maxval="1" description="Implementation-dependent page attribute" />
            <Field name="X1" size="1" location="26" bitable="false" minval="0" maxval="1" description="Implementation-dependent page attribute" />
            <Field name="W" size="1" location="27" bitable="false" minval="0" maxval="1" description="Write-through" />
            <Field name="I" size="1" location="28" bitable="false" minval="0" maxval="1" description="Caching-inhibited" />
            <Field name="M" size="1" location="29" bitable="false" minval="0" maxval="1" description="Memory coherence required" />
            <Field name="G" size="1" location="30" bitable="false" minval="0" maxval="1" description="Guarded" />
            <Field name="E" size="1" location="31" bitable="false" minval="0" maxval="1" description="Endianness. Determines endianness for the corresponding page. Little-endian operation is true little endian, which differs from the modified little-endian byte ordering model optionally available in previous devices that implement the PowerPC architecture." />
        </Register>
        <Register name="MAS3" memorymap="false" id="0x0000273" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MAS3" signed="false">
            <Field name="RPN" size="20" location="0" bitable="false" minval="0" maxval="1" description="Real page number. Depending on page size, only the bits associated with a page boundary are valid. Bits that represent offsets within a page are ignored and should be zero." />
            <Field name="U0" size="1" location="22" bitable="false" minval="0" maxval="1" description="User bits. These bits are associated with a TLB entry and can be used by system software. For example, these bits may be used to hold information useful to a page scanning algorithm or be used&#x0A;to mark more abstract page attributes." />
            <Field name="U1" size="1" location="23" bitable="false" minval="0" maxval="1" description="User bits. These bits are associated with a TLB entry and can be used by system software. For example, these bits may be used to hold information useful to a page scanning algorithm or be used&#x0A;to mark more abstract page attributes." />
            <Field name="U2" size="1" location="24" bitable="false" minval="0" maxval="1" description="User bits. These bits are associated with a TLB entry and can be used by system software. For example, these bits may be used to hold information useful to a page scanning algorithm or be used&#x0A;to mark more abstract page attributes." />
            <Field name="U3" size="1" location="25" bitable="false" minval="0" maxval="1" description="User bits. These bits are associated with a TLB entry and can be used by system software. For example, these bits may be used to hold information useful to a page scanning algorithm or be used&#x0A;to mark more abstract page attributes." />
            <Field name="PERMIS" size="6" location="26" bitable="false" minval="0" maxval="1" description="Permission bits (UX, SX, UW, SW, UR, SR). User and supervisor read, write, and execute permission bits." />
        </Register>
        <Register name="MAS4" memorymap="false" id="0x0000274" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MAS4" signed="false">
            <Field name="TLBSELD" size="2" location="2" bitable="false" minval="0" maxval="1" description="TLBSEL default value. 2-bit field that specifies the default value to be loaded in MAS0[TLBSEL] on a TLB miss exception." />
            <Field name="TIDSELD" size="2" location="14" bitable="false" minval="0" maxval="1" description="-" />
            <Field name="SHAREND" size="1" location="19" bitable="false" minval="0" maxval="1" description="On the e500 implementation this fields is defined as the default SHAREN value." />
            <Field name="TSIZED" size="4" location="20" bitable="false" minval="0" maxval="1" description="Default TSIZE value. Specifies the default value to be loaded into MAS1[TSIZE] on a TLB miss exception." />
            <Field name="X0D" size="1" location="25" bitable="false" minval="0" maxval="1" description="Default X0 value. Specifies the default value to be loaded into MAS2[X0] on a TLB miss exception." />
            <Field name="X1D" size="1" location="26" bitable="false" minval="0" maxval="1" description="Default X1 value. Specifies the default value to be loaded into MAS2[X1] on a TLB miss exception." />
            <Field name="WD" size="1" location="27" bitable="false" minval="0" maxval="1" description="Default W value. Specifies the default value to be loaded into MAS2[W] on a TLB miss exception." />
            <Field name="ID" size="1" location="28" bitable="false" minval="0" maxval="1" description="Default I value. Specifies the default value to be loaded into MAS2[I] on a TLB miss exception." />
            <Field name="MD" size="1" location="29" bitable="false" minval="0" maxval="1" description="Default M value. Specifies the default value to be loaded into MAS2[M] on a TLB miss exception." />
            <Field name="GD" size="1" location="30" bitable="false" minval="0" maxval="1" description="Default G value. Specifies the default value to be loaded into MAS2[G] on a TLB miss exception." />
            <Field name="ED" size="1" location="31" bitable="false" minval="0" maxval="1" description="Default E value. Specifies the default value to be loaded into MAS2[E] on a TLB miss exception." />
        </Register>
        <Register name="MAS6" memorymap="false" id="0x0000276" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="MAS6" signed="false">
            <Field name="SPID0" size="8" location="8" bitable="false" minval="0" maxval="1" description="For the e500 implementation, this field contains the 8-bit search PID0 value. Specifies the value of PID0 used when searching the TLB during execution of tlbsx." />
            <Field name="SAS" size="1" location="31" bitable="false" minval="0" maxval="1" description="Address space (AS) value for searches. Specifies the value of AS used when searching the TLB during execution of tlbsx." />
        </Register>
        <Register name="PID0" memorymap="False" id="0x0000030" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="PID0" signed="False">
            <Field name="Process ID" size="10" location="22" bitable="false" minval="0" maxval="1" description="-" />
        </Register>
        <Register name="PID1" memorymap="false" id="0x0000279" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="PID1" signed="false">
            <Field name="Process ID" size="10" location="22" bitable="false" minval="0" maxval="1" description="-" />
        </Register>
        <Register name="PID2" memorymap="false" id="0x000027A" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="PID2" signed="false">
            <Field name="Process ID" size="10" location="22" bitable="false" minval="0" maxval="1" description="-" />
        </Register>
        <Register name="MMUCFG" alias="msssr0" memorymap="false" id="0x00003F7" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="MMUCFG" signed="false">
            <Field name="NPIDS" size="4" location="17" bitable="false" minval="0" maxval="1" description="Number of PID registers, a 4-bit field that indicates the number of PID registers provided by the processor. The e500 implements three PIDs." />
            <Field name="PIDSIZE" size="5" location="21" bitable="false" minval="0" maxval="1" description="PID register size. The 5-bit value of PIDSIZE is one less than the number of bits in each of the PID registers implemented by the processor. The processor implements only the least significant PIDSIZE+1 bits in the PID registers. 00111: indicates 8-bit registers. This is the value presented by the e500" />
            <Field name="NTLBS" size="2" location="28" bitable="false" minval="0" maxval="1" description="Number of TLBs. The value of NTLBS is one less than the number of software-accessible TLB structures that are implemented by the processor. NTLBS is set to one less than the number of TLB structures so that its value matches the maximum value of MAS0[TLBSEL].)" />
            <Field name="MAVN" size="2" location="30" bitable="false" minval="0" maxval="1" description="MMU architecture version number. Indicates the version number of the architecture of the MMU implemented by the processor. 0b00 indicates version 1.0." />
        </Register>
        <Register name="TLB0CFG" memorymap="false" id="0x00002B0" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="TLB0CFG" signed="false">
            <Field name="ASSOC" size="8" location="0" bitable="false" minval="0" maxval="1" description="Associativity of TLB0; 0x02: indicates associativity is 2-way set associative" />
            <Field name="MINSIZE" size="4" location="8" bitable="false" minval="0" maxval="1" description="Minimum page size of TLB0; 0x1: indicates smallest page size is 4K" />
            <Field name="MAXSIZE" size="4" location="12" bitable="false" minval="0" maxval="1" description="Maximum page size of TLB0; 0x1: indicates maximum page size is 4k" />
            <Field name="IPROT" size="1" location="16" bitable="false" minval="0" maxval="1" description="Invalidate protect capability of TLB0;0 Indicates invalidate protection capability not supported" />
            <Field name="AVAIL" size="1" location="17" bitable="false" minval="0" maxval="1" description="Page size availability of TLB0; 0 No variable-sized pages available (MINSIZE = MAXSIZE)" />
            <Field name="NENTRY" size="12" location="20" bitable="false" minval="0" maxval="1" description="Number of entries in TLB0; 0x100: TLB0 contains 256 entries" />
        </Register>
        <Register name="TLB1CFG" memorymap="false" id="0x00002B1" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="TLB1CFG" signed="false">
            <Field name="ASSOC" size="8" location="0" bitable="false" minval="0" maxval="1" description="Associativity of TLB1; 0x10: indicates associativity is 16" />
            <Field name="MINSIZE" size="4" location="8" bitable="false" minval="0" maxval="1" description="Minimum page size of TLB1; 0x1: indicates smallest page size is 4K" />
            <Field name="MAXSIZE" size="4" location="12" bitable="false" minval="0" maxval="1" description="Maximum page size of TLB1; 0x9: indicates maximum page size is 256 Mbyte" />
            <Field name="IPROT" size="1" location="16" bitable="false" minval="0" maxval="1" description="Invalidate protect capability of TLB1; 1 Indicates that TLB1 supports invalidate protection capability" />
            <Field name="AVAIL" size="1" location="17" bitable="false" minval="0" maxval="1" description="Page size availability of TLB1; 1 Indicates all page sizes between MINSIZE and MAXSIZE supported" />
            <Field name="NENTRY" size="12" location="20" bitable="false" minval="0" maxval="1" description="Number of entries in TLB1; 0x010: TLB1 contains 16 entries" />
        </Register>
    </Group>
    <Group name="Debug Registers" description="Debug Registers, Supervisor level" >
    	<Register name="DBCR0" memorymap="false" id="0x0000134" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="DBCR0" signed="false">
            <Field name="IDM" size="1" location="1" bitable="false" minval="0" maxval="1" description="Internal debug mode." />
            <Field name="RST" size="2" location="2" bitable="false" minval="0" maxval="1" description="Reset. Book E defines this field such that 00 is always no action and all other settings are implementation specific." />
            <Field name="ICMP" size="1" location="4" bitable="false" minval="0" maxval="1" description="Instruction completion debug event enable" />
            <Field name="BRT" size="1" location="5" bitable="false" minval="0" maxval="1" description="Branch taken debug event enable" />
            <Field name="IRPT" size="1" location="6" bitable="false" minval="0" maxval="1" description="Interrupt taken debug event enable. This bit affects only noncritical interrupts." />
            <Field name="TRAP" size="1" location="7" bitable="false" minval="0" maxval="1" description="Trap debug event enable" />
            <Field name="IAC1" size="1" location="8" bitable="false" minval="0" maxval="1" description="Instruction address compare 1 debug event enable" />
            <Field name="IAC2" size="1" location="9" bitable="false" minval="0" maxval="1" description="Instruction address compare 2 debug event enable." />
            <Field name="DAC1" size="2" location="12" bitable="false" minval="0" maxval="1" description="Data address compare 1 debug event enable" />
            <Field name="DAC2" size="2" location="14" bitable="false" minval="0" maxval="1" description="Data address compare 2 debug event enable" />
            <Field name="RET" size="1" location="16" bitable="false" minval="0" maxval="1" description="Return debug event enable" />
            <Field name="FT" size="1" location="31" bitable="false" minval="0" maxval="1" description="Freeze timers on debug event" />
        </Register>
        <Register name="DBCR1" alias="ibcrzeppo" memorymap="false" id="0x0000135" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="DBCR1" signed="false">
            <Field name="IAC1US" size="2" location="0" bitable="false" minval="0" maxval="1" description="Instruction address compare 1 user/supervisor mode" />
            <Field name="IAC1ER" size="2" location="2" bitable="false" minval="0" maxval="1" description="Instruction address compare 1 effective/real mode" />
            <Field name="IAC2US" size="2" location="4" bitable="false" minval="0" maxval="1" description="Instruction address compare 2 user/supervisor mode" />
            <Field name="IAC2ER" size="2" location="6" bitable="false" minval="0" maxval="1" description="Instruction address compare 2 effective/real mode" />
            <Field name="IAC12M" size="2" location="8" bitable="false" minval="0" maxval="1" description="Instruction address compare 1/2 mode" />
        </Register>
        <Register name="DBCR2" alias="dbcrzeppo" memorymap="false" id="0x0000136" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="DBCR2" signed="false">
            <Field name="DAC1US" size="2" location="0" bitable="false" minval="0" maxval="1" description="Data address compare 1 user/supervisor mode" />
            <Field name="DAC1ER" size="2" location="2" bitable="false" minval="0" maxval="1" description="Data address compare 1 effective/real mode" />
            <Field name="DAC2US" size="2" location="4" bitable="false" minval="0" maxval="1" description="Data address compare 2 user/supervisor mode" />
            <Field name="DAC2ER" size="2" location="6" bitable="false" minval="0" maxval="1" description="Data address compare 2 effective/real mode" />
            <Field name="DAC12M" size="2" location="8" bitable="false" minval="0" maxval="1" description="Data address compare 1/2 mode" />
        </Register>
        <Register name="DBSR" memorymap="false" id="0x0000130" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="DBSR" signed="false">
            <Field name="IDE" size="1" location="0" bitable="false" minval="0" maxval="1" description="Imprecise debug event. Set if MSR[DE] = 0 and a debug event causes its respective DBSR bit to be set." />
            <Field name="UDE" size="1" location="1" bitable="false" minval="0" maxval="1" description="Unconditional debug event. Set if an unconditional debug event occurred." />
            <Field name="MRR" size="2" location="2" bitable="false" minval="0" maxval="1" description="Most recent reset. Set of three values when a reset occurs. Undefined at power-up." />
            <Field name="ICMP" size="1" location="4" bitable="false" minval="0" maxval="1" description="Instruction complete debug event. Set if an instruction completion debug event occurred and DBCR0[ICMP] = 1." />
            <Field name="BRT" size="1" location="5" bitable="false" minval="0" maxval="1" description="Branch taken debug event. Set if a branch taken debug event occurred (DBCR0[BRT]=1)." />
            <Field name="IRPT" size="1" location="6" bitable="false" minval="0" maxval="1" description="Interrupt taken debug event. Set if an interrupt taken debug event occurred (DBCR0[IRPT]=1)." />
            <Field name="TRAP" size="1" location="7" bitable="false" minval="0" maxval="1" description="Trap instruction debug event. Set if a trap Instruction debug event occurred (DBCR0[TRAP]=1)." />
            <Field name="IAC1" size="1" location="8" bitable="false" minval="0" maxval="1" description="Instruction address compare 1 debug event. Set if an IAC1 debug event occurred (DBCR0[IAC1]=1)." />
            <Field name="IAC2" size="1" location="9" bitable="false" minval="0" maxval="1" description="Instruction address compare 2 debug event. Set if an IAC2 debug event occurred (DBCR0[IAC2]=1)." />
            <Field name="DAC1R" size="1" location="12" bitable="false" minval="0" maxval="1" description="Data address compare 1 read debug event. Set if a read-type DAC1 debug event occurred (DBCR0[DAC1]=10 or 11)." />
            <Field name="DAC1W" size="1" location="13" bitable="false" minval="0" maxval="1" description="Data address compare 1 write debug event. Set if a write-type DAC1 debug event occurred (DBCR0[DAC1]=01 or 11)." />
            <Field name="DAC2R" size="1" location="14" bitable="false" minval="0" maxval="1" description="Data address compare 2 read debug event.Set if a read-type DAC2 debug event occurred (DBCR0[DAC2]=10 or 11)." />
            <Field name="DAC2W" size="1" location="15" bitable="false" minval="0" maxval="1" description="Data address compare 2 write debug event. Set if a write-type DAC2 debug event occurred (DBCR0[DAC2] =01 or 11)." />
            <Field name="RET" size="1" location="16" bitable="false" minval="0" maxval="1" description="Return debug event. Set if a return debug event occurred (DBCR0[RET]=1)." />
        </Register>        
        <Register name="IAC1" memorymap="false" id="0x0000138" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IAC1" signed="false">
            <Field name="Instruction address" size="30" location="0" bitable="false" minval="0" maxval="1" description="-" />
        </Register>
        <Register name="IAC2" memorymap="false" id="0x0000139" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="IAC2" signed="false">
            <Field name="Instruction address" size="30" location="0" bitable="false" minval="0" maxval="1" description="-" />
        </Register>
        <Register name="DAC1" memorymap="false" id="0x000013C" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="DAC1" signed="false" />
        <Register name="DAC2" alias="dabr2zeppo" memorymap="false" id="0x000013D" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="DAC2" signed="false" />
    </Group>
    <Group name="Timer Decrementer Registers" description="Timer Decrementer Registers, Supervisor level" >
    	<Register name="DEC" memorymap="false" id="0x000016" bytes="4" width="32" reservalue="0x0000" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="DEC" signed="false" />
    	<Register name="DECAR" memorymap="False" id="0x0000036" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="False" rdable="false" wrable="true" description="DECAR" signed="false" />
    	<Register name="TBLW" memorymap="false" id="00000x11C" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="false" wrable="true" description="TBLW" signed="false" />
        <Register name="TBUW" memorymap="false" id="0x000011d" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="false" wrable="true" description="TBUW" signed="false" />
        <Register name="TCR" memorymap="false" id="0x0000154" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="TCR" signed="false">
            <Field name="WP" size="2" location="0" bitable="false" minval="0" maxval="1" description="Watchdog timer period. When concatenated with WPEXT, specifies one of 64-bit locations of the time base used to signal a watchdog timer exception on a transition from 0 to 1. WPEXT[0-3],WP[0-1] = 0b00_0000 selects TBU[0] ; WPEXT[0-3],WP[0-1] = 0b111111 selects TBL[63]" />
            <Field name="WRC" size="2" location="2" bitable="false" minval="0" maxval="1" description="Watchdog timer reset control. This value is written into TSR[WRS] when a watchdog event occurs. WRC may be set by software but cannot be cleared by software, except by a software-induced reset. Once written to a non-zero value, WRC may no longer be altered by software." />
            <Field name="WIE" size="1" location="4" bitable="false" minval="0" maxval="1" description="Watchdog timer interrupt enable" />
            <Field name="DIE" size="1" location="5" bitable="false" minval="0" maxval="1" description="Decrementer interrupt enable" />
            <Field name="FP" size="2" location="6" bitable="false" minval="0" maxval="1" description="Fixed interval timer period. When concatenated with FPEXT, FP specifies one of 64 bit locations of the time base used to signal a fixed-interval timer exception on a transition from 0 to 1.FPEXT[0-3],FP[0-1] = 0b00_0000 selects TBU[0];FPEXT[0-3],FP[0-1] = 0b11_1111 selects TBL[63]" />
            <Field name="FIE" size="1" location="8" bitable="false" minval="0" maxval="1" description="Fixed interval interrupt enable" />
            <Field name="ARE" size="1" location="9" bitable="false" minval="0" maxval="1" description="Auto-reload enable. Controls whether the value in DECAR is reloaded into the DEC when the DEC value reaches 0000_0001." />
            <Field name="WPEXT" size="4" location="11" bitable="false" minval="0" maxval="1" description="Watchdog timer period extension (see above description for WP)." />
            <Field name="FPEXT" size="4" location="15" bitable="false" minval="0" maxval="1" description="Fixed-interval timer period extension (see above description for FP)" />
        </Register>
        <Register name="TSR" memorymap="false" id="0x0000150" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="TSR" signed="false">
            <Field name="ENW" size="1" location="0" bitable="false" minval="0" maxval="1" description="Enable next watchdog time." />
            <Field name="WIS" size="1" location="1" bitable="false" minval="0" maxval="1" description="Watchdog timer interrupt status." />
            <Field name="WRS" size="2" location="2" bitable="false" minval="0" maxval="1" description="Watchdog timer reset status. Defined at reset (value = 00). Set to TCR[WRC] when a reset is caused by the watchdog timer." />
            <Field name="DIS" size="1" location="4" bitable="false" minval="0" maxval="1" description="Decrementer interrupt status." />
            <Field name="FIS" size="1" location="5" bitable="false" minval="0" maxval="1" description="Fixed-interval timer interrupt status." />
        </Register>
    </Group>
    <Group name="L1 Cache Registers" description="L1 Cache Registers, User/Supervisor level" >
    	<Register name="L1CSR0" memorymap="false" id="0x00003F2" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="L1CSR0" signed="false">
            <Field name="CPE" size="1" location="15" bitable="false" minval="0" maxval="1" description="Cache parity enable" />
            <Field name="PEIE" size="1" location="16" bitable="false" minval="0" maxval="1" description="Parity error injection enable" />
            <Field name="CSLC" size="1" location="20" bitable="false" minval="0" maxval="1" description="Cache snoop lock clear. Sticky bit set by hardware if a dcbi snoop (either internally or externally generated) invalidated a locked cache line. Note that the lock bit for that line is cleared whenever the line is invalidated. This bit can be cleared only by software." />
            <Field name="CUL" size="1" location="21" bitable="false" minval="0" maxval="1" description="Cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location." />
            <Field name="CLO" size="1" location="22" bitable="false" minval="0" maxval="1" description="Cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location." />
            <Field name="CLFC" size="1" location="23" bitable="false" minval="0" maxval="1" description="Cache lock bits flash clear When written to a 1, hardware initiates a cache lock bits flash clear operation. Once the operation is complete, this bit is cleared. Writing a 1 during a flash clear operation causes an undefined operation. Writing a 0 during a flash clear operation is ignored. Clearing occurs regardless of the enable (CE) value." />
            <Field name="CABT" size="1" location="29" bitable="false" minval="0" maxval="1" description="Cache operation aborted." />
            <Field name="CFI" size="1" location="30" bitable="false" minval="0" maxval="1" description="Cache flash invalidate. Cache invalidate" />
            <Field name="CE" size="1" location="31" bitable="false" minval="0" maxval="1" description="Cache enable" />
        </Register>
        <Register name="L1CSR1" alias="HID2" memorymap="false" id="0x00003F3" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="L1CSR1" signed="false">
            <Field name="ICPE" size="1" location="15" bitable="false" minval="0" maxval="1" description="Instruction cache parity enable" />
            <Field name="IPEIE" size="1" location="16" bitable="false" minval="0" maxval="1" description="Instruction parity error injection enable" />
            <Field name="ICSLC" size="1" location="20" bitable="false" minval="0" maxval="1" description="Instruction cache snoop lock clear. Sticky bit set by hardware if an icbi snoop (either internally or externally generated) invalidated a locked line in the instruction cache. Note that the lock bit for that line is cleared whenever the line is invalidated. This bit can only be cleared by software." />
            <Field name="ICUL" size="1" location="21" bitable="false" minval="0" maxval="1" description="Instruction cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location." />
            <Field name="ICLO" size="1" location="22" bitable="false" minval="0" maxval="1" description="Instruction cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location." />
            <Field name="ICLFC" size="1" location="23" bitable="false" minval="0" maxval="1" description="Instruction cache lock bits flash clear. Written to 0 and then 1 to flash clear the lock bit of all entries in the instruction cache; clearing occurs independently from the value of the enable bit (ICE). ICLFC is always always read as 0." />
            <Field name="ICFI" size="1" location="30" bitable="false" minval="0" maxval="1" description="Instruction cache flash invalidate. Written to 0 and then 1 to flash clear the valid bit of all entries in the instruction cache; operates independently from the value of the enable bit (ICE). ICI is always always read as 0." />
            <Field name="ICE" size="1" location="31" bitable="false" minval="0" maxval="1" description="Instruction cache enable" />
        </Register>
    	<Register name="L1CFG0" memorymap="false" id="0x0000203" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="L1CFG0" signed="false">
            <Field name="CARCH" size="2" location="0" bitable="false" minval="0" maxval="1" description="Cache architecture" />
            <Field name="CWPA" size="1" location="2" bitable="false" minval="0" maxval="1" description="Cache way partitioning available" />
            <Field name="CFAHA" size="1" location="3" bitable="false" minval="0" maxval="1" description="Cache flush all by hardware available" />
            <Field name="CFISWA" size="1" location="4" bitable="false" minval="0" maxval="1" description="Cache flush/inval by set and way available" />
            <Field name="CBSIZE" size="2" location="7" bitable="false" minval="0" maxval="1" description="Cache line size" />
            <Field name="CREPL" size="2" location="9" bitable="false" minval="0" maxval="1" description="Cache replacement policy" />
            <Field name="CLA" size="1" location="11" bitable="false" minval="0" maxval="1" description="Cache locking APU available" />
            <Field name="CPA" size="1" location="12" bitable="false" minval="0" maxval="1" description="Cache parity available" />
            <Field name="CNWAY" size="8" location="13" bitable="false" minval="0" maxval="1" description="Cache number of ways. 111Indicates 8 ways." />
            <Field name="CSIZE" size="11" location="21" bitable="false" minval="0" maxval="1" description="Cache size. 0x20: indicates 32 Kbytes" />
        </Register>
        <Register name="L1CFG1" memorymap="false" id="0x0000204" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="L1CFG1" signed="false">
            <Field name="ICBSIZ" size="2" location="7" bitable="false" minval="0" maxval="1" description="Instruction cache block size. 00 Indicates block size of 32 bytes" />
            <Field name="ICREPL" size="2" location="9" bitable="false" minval="0" maxval="1" description="Instruction cache replacement policy. 01Indicates pseudo-LRU policy" />
            <Field name="ICLA" size="1" location="11" bitable="false" minval="0" maxval="1" description="Instruction cache locking available. 1 indicates available." />
            <Field name="ICPA" size="1" location="12" bitable="false" minval="0" maxval="1" description="Instruction cache parity available. 1 indicates available." />
            <Field name="ICNWAY" size="8" location="13" bitable="false" minval="0" maxval="1" description="Instruction cache number of ways. 111 Indicates eight ways." />
            <Field name="ICSIZE" size="11" location="21" bitable="false" minval="0" maxval="1" description="Instruction cache size. 0x20 indicates 32 Kbytes" />
        </Register>
    </Group>
    <Group name="Miscellaneous Registers" description="Miscellaneous Registers, User/Supervisor level" >
		<Register name="BBEAR" memorymap="false" id="0x0000201" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="BBEAR" signed="false">
            <Field name="Branch buffer entry address" size="30" location="0" bitable="false" minval="0" maxval="1" description="Branch buffer entry address bits 0-29" />
            <Field name="IAB[0-1]" size="2" location="30" bitable="false" minval="0" maxval="1" description="Instruction after branch (with BBTAR[62]). 3-bit pointer that points to the instruction in the cache line after the branch." />
        </Register>
        <Register name="BBTAR" memorymap="false" id="0x0000202" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="BBTAR" signed="false">
            <Field name="Branch buffer target address" size="30" location="0" bitable="false" minval="0" maxval="1" description="Branch buffer target address bits 0-29" />
            <Field name="IAB2" size="1" location="30" bitable="false" minval="0" maxval="1" description="Instruction after branch bit 2 (with BBEAR[30-31]). IAB is a 3-bit pointer that points to the instruction in the cache line after the branch." />
            <Field name="BDIRPR" size="1" location="31" bitable="false" minval="0" maxval="1" description="Branch direction prediction. The user can pick the direction of the predicted branch." />
        </Register>
		<Register name="BUCSR" alias="dabr" memorymap="false" id="0x00003F5" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="BUCSR" signed="false">
            <Field name="BBFI" size="1" location="22" bitable="false" minval="0" maxval="1" description="Branch buffer flash invalidate. Clearing and then setting BBFI flash clears the valid bit of all entries in the branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBFI is always read as 0." />
            <Field name="BBLO" size="1" location="23" bitable="false" minval="0" maxval="1" description="Branch buffer lock overflow status" />
            <Field name="BBUL" size="1" location="24" bitable="false" minval="0" maxval="1" description="Branch buffer unable to lock" />
            <Field name="BBLFC" size="1" location="25" bitable="false" minval="0" maxval="1" description="Branch buffer lock bits flash clear. Clearing and then setting BBLFC flash clears the lock bit of all entries in the branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBLFC is always read as 0." />
            <Field name="BPEN" size="1" location="31" bitable="false" minval="0" maxval="1" description="Branch prediction enable" />
        </Register>
		<Register name="HID0" memorymap="false" id="0x00003F0" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="HID0" signed="false">
            <Field name="EMCP" size="1" location="0" bitable="false" minval="0" maxval="1" description="Enable machine check pin, MCP. Used to mask out further machine check exceptions caused by assertion of MCP." />
            <Field name="DOZE" size="1" location="8" bitable="false" minval="0" maxval="1" description="Doze power management mode. If MSR[WE] is set, this bit controls DOZE mode." />
            <Field name="NAP" size="1" location="9" bitable="false" minval="0" maxval="1" description="Nap power management mode. If MSR[WE] is set, this bit controls NAP mode." />
            <Field name="SLEEP" size="1" location="10" bitable="false" minval="0" maxval="1" description="Configure for sleep power management mode. Controls SLEEP mode if MSR[WE] is set." />
            <Field name="TBEN" size="1" location="17" bitable="false" minval="0" maxval="1" description="Time base enable" />
            <Field name="SEL_TBCLK" size="1" location="18" bitable="false" minval="0" maxval="1" description="Select time base clock" />
            <Field name="NOPTI" size="1" location="31" bitable="false" minval="0" maxval="1" description="No-op the data and instruction cache touch instructions." />
        </Register>
        <Register name="HID1" memorymap="false" id="0x00003F1" bytes="4" width="32" reservalue="0x00" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="HID1" signed="false">
            <Field name="PLL_MODE" size="2" location="0" bitable="false" minval="0" maxval="1" description="Read-only for integrated devices. 01 fixed value for MPC8560." />
            <Field name="PLL_CFG" size="6" location="2" bitable="false" minval="0" maxval="1" description="Reflected directly from configuration input pins (read-only).lf; &#x0A;    PLL_CFG[0-4] corresponds to the integer divide ratio and PLL_CFG5 is the half-mode bit.lf;&#x0A;    MPC8560 supports the following:lf;&#x0A;    00010 0 2:1lf;&#x0A;    00010 1 5:2 (2.5:1)lf;&#x0A;    00011 0 3:1lf;&#x0A;    00011 1 7:2 (3.5:1)lf;&#x0A;    Note that this value is also reflected to PORPLLSR[e500_Ratio].lf; &#x0A;    See Section 17.4.1.1, POR PLL Status Register (PORPLLSR)." />
            <Field name="RFXE" size="1" location="14" bitable="false" minval="0" maxval="1" description="Read fault exception enable. Controls whether assertion of core_fault_in causes a machine check&#x0A;interrupt. The assertion of core_fault_in can result from an L2 multibit ECC error. It can also occur&#x0A;for a system error if logic on the integrated device signals a fault for nonfatal errors (read data is&#x0A;corrupt (or zero), but the bus transaction can complete without corrupting other system state,&#x0A;making it unnecessary to take a machine check (for example, a master abort of a PCI transaction).lf;&#x0A;0 Assertion of core_fault_in cannot cause a machine check. RFXE should be left clear if an&#x0A;interrupt is to be reported by the integrated device through int or c_int for this condition. If&#x0A;RFXE = 0, it is important that the integrated device generates an interrupt if core_fault_in is&#x0A;asserted.&#x0A;If core_fault_in is asserted, any data on the CCB bus is dropped, stalling the load/store&#x0A;execution unit and eventually causing the e500 pipeline to stall until an interrupt occurs (typically&#x0A;an interrupt generated by the programmable interrupt controller (PIC) as a response to the&#x0A;fault). Because core_fault_in cannot cause a machine check if RFXE is 0, it is critical that the&#x0A;system be configured to generate the appropriate interrupt.lf;&#x0A;1 A machine check can occur due to assertion of core_fault_in.&#x0A;If MSR[ME] = 1 and a fault is signaled, a machine check interrupt occurs.&#x0A;If MSR[ME] = 0 and a fault is signaled, a checkstop occurs.&#x0A;Note that if RFXE is set and another mechanism is configured to generate an interrupt in&#x0A;response to assertion of core_fault_in, the same event causes two interrupts, the machine&#x0A;check enabled by setting RFXE and the interrupt triggered by the on-chip peripheral or other&#x0A;block; therefore, RFXE should be set only if no other mechanism is configured to generate an&#x0A;interrupt for this case.&#x0A;Note that th
e L2 cache detects any assertion of core_fault_in and ensures that the L2 cache is not&#x0A;corrupted when data is dropped for this type of transaction.&#x0A;&#x09;" />
            <Field name="ASTME" size="1" location="18" bitable="false" minval="0" maxval="1" description="Address bus streaming mode enable. This bit, along with the ECM stream control bits in the&#x0A;EEBACR, enables address bus streaming on the CCB. See Section 8.2.1.1, ECM CCB Address&#x0A;Configuration Register (EEBACR)." />
            <Field name="ABE" size="1" location="19" bitable="false" minval="0" maxval="1" description="Address broadcast enable. The e500 broadcasts cache management instructions (dcbst, dcblc&#x0A;(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) based on ABE. On the&#x0A;MPC8560, ABE must be set to allow management of external L2 caches." />
        </Register>
		<Register name="SPRG0" memorymap="false" id="0x0000110" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG0" signed="false" />
        <Register name="SPRG1" memorymap="false" id="0x0000111" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG1" signed="false" />
        <Register name="SPRG2" memorymap="false" id="0x0000112" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG2" signed="false" />
        <Register name="SPRG3" memorymap="false" id="0x0000113" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG3" signed="false" />
        <Register name="SPRG4" memorymap="false" id="0x0000114" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG0" signed="false" />
        <Register name="SPRG5" memorymap="false" id="0x0000115" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG1" signed="false" />
        <Register name="SPRG6" memorymap="false" id="0x0000116" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG2" signed="false" />
        <Register name="SPRG7" memorymap="false" id="0x0000117" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="SPRG3" signed="false" />    	
    </Group>
   
    
	<Group name="Floating Register" description="Registers">
    	<Register name="fpr0" memorymap="false" id="0x0000BB8" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr1" memorymap="false" id="0x0000BB9" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr2" memorymap="false" id="0x0000BBA" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr3" memorymap="false" id="0x0000BBB" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr4" memorymap="false" id="0x0000BBC" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr5" memorymap="false" id="0x0000BBD" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr6" memorymap="false" id="0x0000BBE" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr7" memorymap="false" id="0x0000BBF" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr8" memorymap="false" id="0x0000BC0" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr9" memorymap="false" id="0x0000BC1" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr10" memorymap="false" id="0x0000BC2" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr11" memorymap="false" id="0x0000BC3" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr12" memorymap="false" id="0x0000BC4" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr13" memorymap="false" id="0x0000BC5" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr14" memorymap="false" id="0x0000BC6" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr15" memorymap="false" id="0x0000BC7" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr16" memorymap="false" id="0x0000BC8" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr17" memorymap="false" id="0x0000BC9" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr18" memorymap="false" id="0x0000BCA" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr19" memorymap="false" id="0x0000BCB" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr20" memorymap="false" id="0x0000BCC" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr21" memorymap="false" id="0x0000BCD" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr22" memorymap="false" id="0x0000BCE" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr23" memorymap="false" id="0x0000BCF" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr24" memorymap="false" id="0x0000BD0" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr25" memorymap="false" id="0x0000BD1" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr26" memorymap="false" id="0x0000BD2" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr27" memorymap="false" id="0x0000BD3" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr28" memorymap="false" id="0x0000BD4" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr29" memorymap="false" id="0x0000BD5" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr30" memorymap="false" id="0x0000BD6" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpr31" memorymap="false" id="0x0000BD7" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="fpscr" memorymap="false" id="0x0000BD8" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    </Group>
    
    <Group name="VFP Register" description="Registers">
    	<Register name="vr0" memorymap="false" id="0x0000FA0" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr1" memorymap="false" id="0x0000FA1" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr2" memorymap="false" id="0x0000FA2" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr3" memorymap="false" id="0x0000FA3" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr4" memorymap="false" id="0x0000FA4" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr5" memorymap="false" id="0x0000FA5" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr6" memorymap="false" id="0x0000FA6" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr7" memorymap="false" id="0x0000FA7" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr8" memorymap="false" id="0x0000FA8" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr9" memorymap="false" id="0x0000FA9" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr10" memorymap="false" id="0x0000FAA" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr11" memorymap="false" id="0x0000FAB" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr12" memorymap="false" id="0x0000FAC" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr13" memorymap="false" id="0x0000FAD" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr14" memorymap="false" id="0x0000FAE" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr15" memorymap="false" id="0x0000FAF" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr16" memorymap="false" id="0x0000FB0" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr17" memorymap="false" id="0x0000FB1" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr18" memorymap="false" id="0x0000FB2" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr19" memorymap="false" id="0x0000FB3" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr20" memorymap="false" id="0x0000FB4" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr21" memorymap="false" id="0x0000FB5" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr22" memorymap="false" id="0x0000FB6" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr23" memorymap="false" id="0x0000FB7" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr24" memorymap="false" id="0x0000FB8" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr25" memorymap="false" id="0x0000FB9" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr26" memorymap="false" id="0x0000FBA" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr27" memorymap="false" id="0x0000FBB" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr28" memorymap="false" id="0x0000FBC" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr29" memorymap="false" id="0x0000FBD" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr30" memorymap="false" id="0x0000FBE" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vr31" memorymap="false" id="0x0000FBF" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    	<Register name="vscr" memorymap="false" id="0x0000FC0" bytes="4" width="32" resetvalue="0x00" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="r0" signed="false" />
    </Group>
    
    <Group name="Performance Monitor Regs" description="Performance Monitor Registers">
    </Group>
</CPU>
