#######################################
#FILE
# $RCSfile: 8540EVAL_init.cfg,v $
# $Date: 2006/09/22 14:30:09 $
# $Revision: 1.3 $
#DESCRIPTION
# Debugger initialization file for
# 8540 EVAL rev.B board
# MPC8540 - silicon Rev. 1.0
#COPYRIGHT 
# (c) 2004 Freescale Semiconductor
# All rights reserved.
#HISTORY
# $Log: 8540EVAL_init.cfg,v $
# Revision 1.3  2006/09/22 14:30:09  vcambrea
# clear debug event status after all breakpoint hits
#
# Revision 1.2  2005/11/14 13:36:29  adrpopa1
# Remove comments containing "workaround" word.
#
# Revision 1.1  2004/11/15 14:13:02  c-dnegrea
# files moved from Initialization_Files/JTAG to Initialization_Files/PQ3
#
# Revision 1.4  2004/07/01 14:41:35  tmadan
# commented out setMMRBaseAddr command (it is obsolete)
#
# Revision 1.3  2004/05/29 13:47:57  C-vcambrea
# updated to 8540EVAL with rev 2 silicon
#
# Revision 1.2  2004/01/30 16:41:55  C-vcambrea
# Trap debug event enable in DBCR0.
#
# Revision 1.1  2004/01/12 12:21:20  C-vcambrea
# debugger initialization file for 8540 EVAL board
# 
########################################


# debugger does not need anymore to be informed about the 8560 memory-mapped register base CCSRBAR. 
# It will read CCSRBAR value through JTAG
#setMMRBaseAddr 0xFF700000		# CCSRBAR default value

writemem.l 0xFF705000 0x00001000 # invalidate BR0
writemem.l 0xFF720E44 0x0000000C # disable L2SRAM ECC Errors


##################################################################################
# configure internal SRAM at highest memory address to cover the default MMU page

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM disabled
# bit 4-5 = 01 		- L2BLKSZ: = 256KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0x68010000

# L2SRBAR0
# bit 0-17 = 0xFFFC0000 - BASE addr: 4GB-256KB
writemem.l	0xFF720100	0xFFFC0000

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM enable
# bit 4-5 = 01 		- L2BLKSZ: = 256KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0xA8010000

#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200

# set IVOR15 (debug) interrupt vectors in SRAM at 0xFFFFF000
writereg	IVPR 	0xFFFF0000 	# IVPR (default reset value) 
writereg	IVOR15 	0x0000F000	# IVOR15 - debug

# write at the reset address a branch to 0xFFFFF000
writemem.l  0xfffffffc  0x4BFFF004  # branch to 0xfffff000

# set hardware breakpoint at 0xFFFFF000 address
writereg	DBCR0		0x41800000
writereg	IAC1		0xFFFFF000
writemem.l	0xFFFFF000	0x60000000	# nop (or any valid opcode)

run
sleep 0x10
stop

writereg	DBCR0	0x41000000
writereg	IAC1	0x00000000

#######################################################################


##################################################################################
# MMU initialization
#
# MAS0: MMU read/write and replacement control 
# MAS1: descriptor context and configuration control
# MAS2: EPN and page attributes
# MAS3: RPN and access control
# MAS4: Hardware replacement assist configuration

###
# define 16MB TLB1 entry 0 - FLASH: 0xFF000000 - 0xFFFFFFFF
writespr	624 0x10000000	# MAS0 - select TLB1, entry 0 
writespr	625 0x80000700	# MAS1 - TLB1 valid, 16MB page-size
writespr	626 0xFF000008	# MAS2 - EPN, Caching-inhibited 
writespr	627 0xFF00003f	# MAS3 - RPN, full-control permissions

# write tlb entry
writemem.l	0xFFFFF000	0x7C0007A4	# tlbwe
writemem.l	0xFFFFF004	0x7C0004AC	# msync
writemem.l	0xFFFFF008	0x4C00012C	# isync
writemem.l	0xFFFFF00C	0x48000000	# infinite loop
writereg	PC	0xfffff000
run
stop

###
# define 1MB TLB1 entry 1 - CCSR: 0x40000000 - 0x400FFFFF
writespr	624 0x10010000	# MAS0 - select TLB1, entry 1 
writespr	625 0x80000500	# MAS1 - TLB1 valid
writespr	626 0x4000000A	# MAS2 - EPN, Caching-inhibited  
writespr	627 0x4000003f	# MAS3 - RPN, full-control permissions
# write tlb entry
writereg	PC	0xfffff000
run
stop

###
# define 256MB TLB1 entry 2 - DDR: 0x00000000 - 0x0FFFFFFF
writespr	624 0x10020000	# MAS0 - select TLB1, entry 2
writespr	625 0x80000900	# MAS1 - TLB1 valid	
writespr	626 0x00000000	# MAS2 - EPN , cacheable
writespr	627 0x0000003f	# MAS3 - RPN, full-control permissions
writespr	628 0x00000000	# MAS4 - defaults for TLB miss
# write tlb entry
writereg	PC	0xfffff000
run
stop

###
# define 256MB TLB1 entry 3 - PCI: 0xC0000000 - 0xCFFFFFFF
writespr	624 0x10030000	# MAS0 - select TLB1, entry 3 
writespr	625 0x80000900	# MAS1 - TLB1 valid
writespr	626 0xC0000008	# MAS2 - EPN, Caching-inhibited  
writespr	627 0xC000003f	# MAS3 - RPN, full-control permissions
# write tlb entry
writereg	PC	0xfffff000
run
stop

####################################################################
# DDR Controller's DLL stabilization
####################################################################

writemem.l	0xFFFFF000	0x3FC0FF7E  	#	lis      r30,0xFF7E	
writemem.l	0xFFFFF004	0x3BDE0E10  	#	addi     r30,r30,0x0E10
writemem.l	0xFFFFF008	0x83FE0000  	#	lwz      r31,0(r30)
writemem.l	0xFFFFF00c	0x57FF063E  	#	clrlwi   r31,r31,16
writemem.l	0xFFFFF010	0x57FF801E  	#	slwi     r31,r31,16
writemem.l	0xFFFFF014	0x67FF8000  	#	oris     r31,r31,0x8000
writemem.l	0xFFFFF018	0x93FE0000  	#	stw      r31,0(r30)
writemem.l	0xFFFFF01c	0x48000000	# 				/* infinite loop */

writereg	PC	0xfffff000

run
sleep 0x10
stop

##################################################################################
# disable internal 256KB SRAM (used for MMU initialization)

# L2CTL
# bit 0 = 0 		- L2E: L2 SRAM disable
writemem.l	0xFF720000	0x00000000

##################################################################################
# move CCSR at 0x40000000
# 

# CCSRBAR
# bit 12 - 23 - BASE_ADDR
writemem.l	0xFF700000	0x00040000

# debugger does not need anymore to be informed about the 8560 memory-mapped register base CCSRBAR. 
# It will read CCSRBAR value through JTAG
#setMMRBaseAddr 0x40000000


##################################################################################
# configure local access windows
# 
# window 0: DDR - 256MB
# window 1: Local Bus - 2GB

# LAWBAR0
# bit 12 - 31 = 0x0 - base addr
writemem.l	0x40000c08 	0x00000000

# LAWAR0
# bit 1 = 1 - enable window
# bit 8-11 = F - DDR
# bit 26 - 31  = 256MB - size
writemem.l	0x40000c10	0x80f0001b 

# LAWBAR1
# bit 12 - 31 = 0x80000000 - base addr
writemem.l	0x40000c28 	0x00080000

# LAWAR1
# bit 1 = 1 - enable window
# bit 8-11 = 4 - local bus
# bit 26 - 31  = 2GB - size
writemem.l	0x40000c30	0x8040001E


################################################################################
#
# DDR initalization
#

# configure the appropriate DDR controller registers

# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002000 0x00000007 ; DDR CS0 - 0x0000_0000 : 0x07FF_FFFF

# CS0_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 21 - 23 = 0 - ROW_BITS_CS_0 13 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 9 columns
writemem.l 0x40002080 0x80000101

# CS1_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002008 0x0008000f ; DDR CS1 - 0x0800_0000 : 0x0FFF_FFFF

# CS1_CONFIG
# bit 0 = 1 - CS_1_EN CS1 enable
# bit 21 - 23 = 1 - ROW_BITS_CS_1 13 rows
# bit 29 - 31 = 1 - COL_BITS_CS_1 9 columns
writemem.l 0x40002084 0x80000101

# TIMING_CONFIG_1
# bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles
# bit 5-7 = 5 - ACTTOPRE activate to precharge interval 5 clock cycles
# bit 9-11 = 5 = ACTTORW activate to r/w interval 5 clock cycles 
# bit 13 - 15 = 3 - CASLAT CAS latency 2 clock cycles
# bit 16 - 19 = 8 - REFREC refresh recovery time 12 clock cycles 
# bit 22 - 23 = 3 - WRREC data to precharge interval 3 clock cycles 
# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
# bit 30 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle
writemem.l	0x40002108 0x37534321 #0x35534321 

# TIMING_CONFIG_2
# bit 19-21  = b010  - WR_DATA_DELAY - 4/8 clock delay
writemem.l	0x4000210C 0x00000800	#0x00001000

# temporary disable the memory interface for reconfiguration
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l	0x40002110 0x02000000

# DDR_SDRAM_MODE
# bit 0 - 15 = 0x0000 
# bit 16 - 31 = 0x0022 SDMODE 
# burst length = 4
# Normal Operation
# CAS Latency = 2
# Burst Type = Sequential
writemem.l	0x40002118 0x00000022

# DDR_SDRAM_INTERVAL
# bit 2 - 15 = 0x249d - REFINT 
# bit 18 - 31 = 0  - BSTOPRE auto precharge r/w commands used
writemem.l	0x40002124 0x04d00000	#0x249d0000

sleep 300

# enable the DDR memory controller
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic enabled
writemem.l	0x40002110 0x82000000 


#################################################################################
# configure local bus memory controller

# CS0 configuration - FLASH 8MB ,0xFF800000-0xFFFFFFFF 
writemem.l 0x40005000 0xFF801001 # BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid
writemem.l 0x40005004 0xFF806FF7 # OR0 8MB flash size, 15 w.s., timing relaxed


####################################################################
# interrupt vectors initialization

###
# interrupt vectors in SDRAM
#
writereg	IVPR 0x00000000 	# IVPR (default reset value) 

# interrupt vector offset registers 
writespr	400 0x00000100	# IVOR0  - critical input
writespr	401 0x00000200	# IVOR1  - machine check
writespr	402 0x00000300	# IVOR2  - data storage
writespr	403 0x00000400	# IVOR3  - instruction storage
writespr	404 0x00000500	# IVOR4  - external input
writespr	405 0x00000600	# IVOR5  - alignment
writespr	406 0x00000700	# IVOR6  - program
writespr	408 0x00000c00	# IVOR8  - system call
writespr	410 0x00000900	# IVOR10 - decrementer
writespr	411 0x00000f00	# IVOR11 - fixed-interval timer interrupt
writespr	412 0x00000b00	# IVOR12 - watchdog timer interrupt
writespr	413 0x00001100	# IVOR13 - data TLB errror
writespr	414 0x00001000	# IVOR14 - instruction TLB error
writespr	415 0x00001500	# IVOR15 - debug
writespr	528 0x00001600	# IVOR32 - SPE-APU unavailable
writespr	529 0x00001700	# IVOR33 - SPE-floating point data exception
writespr	530 0x00001800	# IVOR34 - SPE-floating point round exception
writespr	531 0x00001900	# IVOR35 - performance monitor



#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200

############
#
# time base enable
writespr	1008	0x00004000	# HID0

######
#
# CW debugger settings
#

# Trap debug event enable
writereg	DBCR0		0x41000000

# Clear debug event status
writereg	DBSR		0x01CF0000

#  set the PC at the reset address (for debug-->connect)
writereg	PC	0xfffffffc

# put a valid opcode at 0x700
writemem.l 0x00000700 0x48000000 # program 
writemem.l 0x00001500 0x48000000 # debug

# for debugging starting at program entry point when stack is not initialized
writereg	SP	0x0000000F
