#############
# enable the second core PCR[PORT1_EN] bit (6)

writemem.l 0xf8001010 0x03000000


#############
#
# enable machine check exception and move interrupt handlers to 0x00000000
writereg	MSR 0x00001000

############
#
# time base enable
writespr	1008	0x04000000	# HID0


######
#
# CW debugger settings
#

# put a valid opcode at debug and progrm exception vector address
# (the begining of physical address space for core 2 is internally shifted with 256MB)
writemem.l 0x10000700 0x48000000

# enable breakpoints workaround for Flash Programmer
writespr	1010	0x702

#initialize SP with an invalid value to prevent stack trace memory reads
writereg SP 0x0f