writereg	MBAR	0xff400000

# change internal MMR base from 0x80000000 (reset value) to 0x80000000
writemem.l 0xff400000 0x80000000 # IMMRBAR = 0x80000000

writereg	MBAR	0x80000000

# LocalPlus Bus Local Access Windows
#####################################
# WINDOW 1 - LocalPlus Boot: 64MB NOR FLASH
writemem.l 0x80000020 0xfc00ffff #LPBAW  - begining at 0xfc000000 

# PCI Local Access Windows
#################################
# WINDOW 0
writemem.l 0x80000060 0x90000000 # PCILAWBAR0 - begining at 0x90000000
writemem.l 0x80000064 0x8000001b # PCILAWAR0  - enable, size = 256MB

# WINDOW 1
writemem.l 0x80000068 0xa0000000 # PCILAWBAR1 - begining at 0xa0000000
writemem.l 0x8000006c 0x8000001b # PCILAWAR1  - enable, size = 256MB

# WINDOW 2
writemem.l 0x80000070 0xb0000000 # PCILAWBAR2 - begining at 0xb0000000
writemem.l 0x80000074 0x8000001b # PCILAWAR2  - enable, size = 256MB

# DDR Local Access Window
#################################
writemem.l 0x800000a0 0x00000000 # DDRLAWBAR - begining at 0x00000000
writemem.l 0x800000a4 0x0000001a # DDRLAWAR  - enable, size = 128MB

# NFC memory window
####################
writemem.l 0x800000c8 0x40000000 # NFCBAR - begining at 0x40000000

#**************************************
# Configure Multi-Port D-RAM Controller
#**************************************

#Enable Clocks
##################
writemem.l 0x80000f04 0xfffffc00 # SCCR1 - enable all clocks
writemem.l 0x80000f08 0xfff80000 # SCCR2 - enable all clocks

#Enable DRAM Module
#######################
writemem.l 0x80009000 0xf0000000

#[0x8000a000] -> 0x00000009 // Setup DDR pads for mobile DDR mode
writemem.l 0x8000a000 0x00000009

#Setup PRIOMAN
##################
writemem.l 0x80009080 0x000777aa
writemem.l 0x80009084 0x00000055
writemem.l 0x80009088 0x00000000
writemem.l 0x8000908C 0x11111117
writemem.l 0x800090a0 0x7777777a
writemem.l 0x80009090 0x444eeeee
writemem.l 0x800090a4 0xeeeeeeee
writemem.l 0x80009094 0x44444444
writemem.l 0x800090a8 0x44444444
writemem.l 0x80009098 0x55555555
writemem.l 0x800090ac 0x55555558
writemem.l 0x8000909c 0x11111111
writemem.l 0x800090b0 0x1111117c
writemem.l 0x800090b4 0x33333377
writemem.l 0x800090c8 0x7777eeee
writemem.l 0x800090b8 0x11111111
writemem.l 0x800090cc 0x11111111
writemem.l 0x800090bc 0x11111111
writemem.l 0x800090d0 0x11111111
writemem.l 0x800090c0 0x11111111
writemem.l 0x800090d4 0x11111111
writemem.l 0x800090c4 0x11111111
writemem.l 0x800090d8 0x11111111

#echo Init. MDDRC for 132 MHz
############################
# DDR_SYS_CONFIG - CMDmode=1, row=4, bank=2, SelfRefEn=0, (rdly=4, 1/2=1, 1/4=0) -> CAS=2, wdly=4
writemem.l 0x80009000 0xf8608100

# DDR_TIME_CONFIG0 - refresh=0, cmd=40, bank_pre=30)
writemem.l 0x80009004 0x0000281e

# DDR_TIME_CONFIG1, rfc=21, wr1=7, wrt1=6 ,rrd=2, rc=11, ras=15
writemem.l 0x80009008 0x54ec1168

# DDR_TIME_CONFIG2, rcd=3, faw=10, rtw1=4, ccd=2, rtp=2, rp=3, rpa=4
writemem.l 0x8000900c 0x35210864

#echo Init DDR2 (Micron MT46H32M16LFCK-75)
#########################################
#Issue 1 NOP operation while waiting 200 us since clock is stable.
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000
writemem.l 0x80009010 0x01380000

#Precharge All
writemem.l 0x80009010 0x01100400

# Issue NOP operation for tRP time
writemem.l 0x80009010 0x01380000

# Issue an AUTO REFRESH
writemem.l 0x80009010 0x01080000

# Issue NOP operation for tRFC time
writemem.l 0x80009010 0x01380000

# Issue an AUTO REFRESH
writemem.l 0x80009010 0x01080000

# Issue NOP operation for tRFC time
writemem.l 0x80009010 0x01380000

# Use LOAD MODE REGISTER to load the standard mode register, CAS=2, BT=Seq, Burst=4
#writemem.l 0x80009010 0x0100002A 
writemem.l 0x80009010 0x01000022 

# Issue NOP operation for tMRD time
writemem.l 0x80009010 0x01380000

# Use LOAD MODE REGISTER to load the extended mode register, DS=Full, PASR=Full
writemem.l 0x80009010 0x01020000

# Issue NOP operation for tMRD time
writemem.l 0x80009010 0x01380000
 
sleep 1000

#echo Start MDDRC
################
# DDR_TIME_CONFIG0, refresh=500, cmd=40, bank_pre=30
writemem.l 0x80009004 0x01f4281e

# DDR_SYS_CONFIG - CMDmode=0, row=4, bank=2, SelfRefEn=0, (rdly=4, 1/2=1, 1/4=0) -> CAS=2, wdly=1
writemem.l 0x80009000 0xe8608100

##############################################
# Local Plus Controller (LPC) Configuration
##############################################

# CS0 - NOR FLASH 
writemem.l 0x80010000 0x00201000 # enable write access


writereg MSR 0x3000 # FP available, machine check, exception vectors at 0x0000_0000


# SPCR[TBEN] enable timebase
writemem.l 0x80000104 0x00400000

#invalidate SP
writereg SP 0xF
