#####################################################
#FILE
# $RCSfile: 7457_Sandpoint_init.cfg,v $
# $Date: 2007/12/18 11:25:17 $
# $Revision: 1.5 $
#DESCRIPTION
#----------------------------------------------------
# Code Warrior config file for Valis X3 with MPC7457
#----------------------------------------------------
#COPYRIGHT 
# (c) 2004 Freescale Corporation
# All rights reserved.
#HISTORY
# $Log: 7457_Sandpoint_init.cfg,v $
# Revision 1.5  2007/12/18 11:25:17  r04474
# update
#
# Revision 1.4  2005/03/19 09:03:32  milies
# changed the offsets for the ODCR, CDCR, and write the MDCR (according to Dink initialization)
#
# Revision 1.3  2004/12/22 10:57:50  milies
# set breakpoint at 0x700 - necessary for flash programmer
#
# Revision 1.2  2004/12/13 16:48:32  abadea
# Added Reset sequence. It is supposed to replace the 'Reset Target on
# Launch' option, which is not always working for 7457 Sandpoint.
#
# Revision 1.1  2004/11/15 13:56:34  c-dnegrea
# files moved from Initialization_Files/JTAG to Initialization_Files/Host
#
# Revision 1.3  2004/05/24 14:46:39  C-vcambrea
# updated Valis X3 (MPC7457) initialization file
# 
#####################################################

; This is the reset sequence required for 7457 Sandpoint.
; Please disable "Reset Target on Launch" option
; in the connection preferences. Otherwise you will
; not be able to properly reset the processor&board.
stop
sleep 0x100
reset 1

;------------------------------------------------------------------
; Note that all registers are indirectly addressed through 
; 0xFEC0_0000, and data is written through 0xFEE0_0000.  Note also
; that the MPC107 is little-endian, but the 'writemem' instruction
; is big-endian, so that all data had to be byte-swapped manually.
;------------------------------------------------------------------

; ----- MPC107 is the PCI bus master (PCICR) ----------------------
writemem.l	0xFEC00000	0x04000080	 
writemem.b	0xFEE00000	0x06	 	; Bus master, memory space

; ----- 8 Memory Banks (64MB each) ---------------------------------
writemem.l	0xFEC00000	0x80000080	; mem_starting_address_1
writemem.l	0xFEE00000	0x0080a0c0	 
writemem.l	0xFEC00000	0x84000080	; mem_starting_address_2
writemem.l	0xFEE00000	0xe0002040       
writemem.l	0xFEC00000	0x88000080	; extended_mem_starting_address_1
writemem.l	0xFEE00000	0x00000000
writemem.l	0xFEC00000	0x8c000080	; extended_mem_starting_address_2
writemem.l	0xFEE00000	0x00010101
writemem.l	0xFEC00000	0x90000080	; mem_ending_address_1
writemem.l	0xFEE00000	0x7f9fbfdf       
writemem.l	0xFEC00000	0x98000080	; extended_mem_ending_address_1
writemem.l	0xFEE00000	0x00000000
writemem.l	0xFEC00000	0x94000080	; mem_ending_address_2
writemem.l	0xFEE00000	0xff1f3f5f       
writemem.l	0xFEC00000	0x9c000080	; extended_mem_ending_address_2
writemem.l	0xFEE00000	0x00010101

; ----- Enable Bank 0 , Disable page mode ---------------
writemem.l	0xFEC00000	0xa0000080	; mem_bank_enable, page_mode
writemem.b	0xFEE00000	0x01

; ----- map B, flash write, processor parked on the data bus ------
writemem.l	0xFEC00000	0xa8000080 	; picr_1
writemem.l	0xFEE00000	0x981a04ff

; ----- ROM/Flash remapping enabled -------------------------------
writemem.l	0xFEC00000	0xac000080	; picr_2
writemem.l	0xFEE00000	0x00000004

; ----- Embedded Utilities Base Address Register -----------------
writemem.l	0xFEC00000	0x78000080	;select EUMBBAR
writemem.l	0xFEE00000	0x000000FC	;Embedded utility memory block at 0xFC000000

; ----- Clear ECC Single-Bit Error Counter ------------------------
writemem.l	0xFEC00000	0xb8000080	; ecc_single_bit_error_ctr
writemem.b	0xFEE00000	0x00

; ----- taken from DINK startup -----------------------------------
writemem.l	0xFEC00000	0xf4000080	; mccr2
writemem.l	0xFEE00000	0x2c184004
writemem.l	0xFEC00000	0xf8000080	; mccr3
writemem.l	0xFEE00000	0x00003078
writemem.l	0xFEC00000	0xfc000080	; mccr4
writemem.l	0xFEE00000	0x39223235

; ----- Enable memory, 8-bit data path for ROM back 0, enable refresh
; ----- during sleep, RAM type = SDRAM, 11 or 12 row bits
writemem.l	0xFEC00000	0xf0000080	; mccr1
writemem.l	0xFEE00000	0x0000e875

writemem.l	0xFEC00000	0x72000080	; PMCR2 
writemem.b	0xFEE00000	0xa0

writemem.l	0xFEC00000	0x73000080	; ODCR 
writemem.b	0xFEE00003	0xd1


writemem.l	0xFEC00000	0x74000080	; CDCR
writemem.w	0xFEE00002	0x00fd	

writemem.l	0xFEC00000	0x76000080	; MDCR
writemem.b	0xFEE00002	0x40

writemem.l	0xFEC00000	0xa3000080	; PGMAX
writemem.b	0xFEE00003	0x32
	

writereg MSR 0x02003902

;valid opcode at program exception
writemem.l	0x700	0x48000000

# for flash programmer:
# eable breakpoint at program exception
writereg IABR	0x702	
