#######################################
#FILE
# $RCSfile: 8250_AM_Rattler_init.cfg,v $
# $Date: 2007/12/18 11:39:39 $
# $Revision: 1.2 $
#DESCRIPTION
#
# Debug Version initialization file for 
# Analogue & Micro RATTLER PCI MPC8250 
# Boot-Low Configuration(factory default)
# CPU = MPC8250AVR; 
# PVR = 0x80811014
#
#COPYRIGHT 
# (c) 2003 Freescale Corporation
# All rights reserved.
#HISTORY
# $Log: 8250_AM_Rattler_init.cfg,v $
# Revision 1.2  2007/12/18 11:39:39  r04474
# update
#
# Revision 1.1  2004/11/15 14:02:11  c-dnegrea
# files moved from Initialization_Files/JTAG to Initialization_Files/PQ2
#
# Revision 1.3  2004/03/31 12:17:41  C-vcambrea
# corrected typo ( 8MB of flash )
#
# Revision 1.2  2003/11/19 16:21:47  C-vcambrea
# debugger init files for AM8250 PCI (boot-low and boot-high)
# 
########################################
 

# Set the IMMR so the debugger plugin knows where it is since
# the IMMR itself is a memory mapped register. This does not
# actually write anything to the target, it is simply to inform
# the debugger plugin where the IMMR is

setMMRBaseAddr 0xFF000000

writemmr IMMR  0x04700000	# relocate internal memory space

setMMRBaseAddr 0x04700000

#Turn on LEDs
writemmr PDIRA 0xE0000000
writemmr PDATA 0x00000000

#Main System Clock Configuration Registers 

writereg 	MSR	0x1002	   # Machine Mode Register

writemmr	SYPCR	0xFFFFFFC3 # SYPCR: turn off watchdog timer

writemmr	SCCR	0x00000000 #  Force baud rate clock divisor = 4

writemmr 	SIUMCR	0x0E040000 # Set configuration bits

writemmr 	SWSR	0x0000

writemmr	BCR		0x00000000               
writemmr	PPC_ACR 	0x02                     
writemmr	PPC_ALRH        0x01234567               
writemmr	PPC_ALRL        0x89ABCDEF               
writemmr	LCL_ACR         0x02                     
writemmr	LCL_ALRH        0x01234567               
writemmr	LCL_ALRL        0x89ABCDEF               
writemmr	TESCR1          0x00000000               
writemmr	TESCR2          0x00000000               
writemmr	L_TESCR1        0x00000000               
writemmr	L_TESCR2        0x00000000               
writemmr	PDTEA           0x00000000               
writemmr	PDTEM           0x00                     
writemmr	LDTEA           0x00000000               
writemmr	LDTEM           0x00        

writemmr	RMR		0x0001	   # generate reset when core enters checkstop state.

# Setup the chip selects

# CS0 - 8MB flash
writemmr	BR0		0xFF801001
writemmr	OR0		0xFF800E76

# CS1 - 16MB DRAM
writemmr	OR1		0xFF003080
writemmr	BR1		0x00000041

# CS4 - 1MB external
writemmr	OR4		0xFFF00000
writemmr	BR4		0x80001801


writemmr	MPTPR		0x2000	# MPTPR: Set the Memory Periodic Timer Prescaler
writemmr	PSRT		0x1F	# set 60x Bus assigned SDRAM Refresh Timer (PSRT) ~ 15.6us

#SDRAM controller
writemmr	PSDMR		0xEA69A452 #Precharge all banks.
writemem.b	0x00000000	0xFF
writemmr	PSDMR		0xCA69A452 #CBR refresh.

# perform 8 accesses
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF

writemmr	PSDMR		0xDA69A452 #Mode Register write.
writemem.b	0x00000000	0xFF
writemmr	PSDMR		0xC269A452 #Normal operation.

# Registers programmed, starting up DRAM
writemmr	PDATA	0xA0000000
sleep 100
writemmr	PDATA	0x80000000

#Turn OFF LEDs
#writemmr PDATA 0xFFFFFFFF