
#setMMRBaseAddr 0xFF400000
writereg	MBAR		0xFF400000

# change internal MMR base from 0xff400000 (reset value) to 0xe0000000
writemem.l	0xFF400000	0xE0000000 # IMMRBAR = 0xE0000000

#setMMRBaseAddr 0xE0000000
writereg	MBAR		0xE0000000


#################################
# Local Bus Local Access Windows
#################################

#
# Window 0 - NAND Flash memory
#
writemem.l	0xE0000020	0xFE000000 # LBLAWBAR0  - begining at 0xFE000000
writemem.l	0xE0000024	0x80000018 # LBLAWAR0   - enable, size = 32MB

#
# Window 1 - BCSR
#
writemem.l	0xE0000028	0xF8000000 # LBLAWBAR1  - begining at 0xF8000000
writemem.l	0xE000002C	0x8000000E # LBLAWAR1   - enable, size = 32KB

#
# Window 2 - NOR Flash memory
#
writemem.l	0xE0000030	0xD0000000 # LBLAWBAR2  - begining at 0xD0000000 
writemem.l	0xE0000034	0x80000017 # LBLAWAR2   - enable, size = 16MB 

#################################
# DDR Local Access Windows
#################################

#
# WINDOW 0 - DDR SODIMM
#
writemem.l	0xE00000a0	0x00000000 # DDRLAWBAR0 - begining at 0x00000000
writemem.l	0xE00000a4	0x8000001A # DDRLAWAR0  - enable, size = 128MB


##############################################
# DDR Controller Configuration
##############################################

#CLK_CNTL
writemem.l	0xE0002130	0x02000000

# CS0_BNDS
writemem.l	0xE0002000	0x00000007 ; 0x00000000 - 0x07FFFFFF # first 128MB

# CS0_CONFIG
writemem.l	0xE0002080	0x80840102

# TIMING_CFG_3
writemem.l	0xE0002100	0x00000000

# TIMING_CONFIG_1
writemem.l	0xE0002108	0x3935D322

# TIMING_CONFIG_2
writemem.l	0xE000210C	0x0F9048CA

# TIMING_CFG_0
writemem.l	0xE0002104	0x00220802

# temporary disable the memory interface for reconfiguration
writemem.l	0xE0002110	0x43080000

# DDR_SDRAM_CFG_2
writemem.l	0xE0002114	0x00401000

# DDR_SDRAM_MODE
writemem.l	0xE0002118	0x44400232

# DDR_SDRAM_MODE_2
writemem.l	0xE000211C	0x8000C000
		

# DDR_SDRAM_INTERVAL
writemem.l	0xE0002124	0x03200064


#delay before enable
sleep 300

# enable the DDR memory controller
writemem.l	0xE0002110	0xC3080000

##############################################
# Local Bus Interface (LBIU) Configuration
##############################################

#LCRR
writemem.l	0xE00050d4	0x00010002

#
# Local bus CS0 - NAND Flash settings
# 
writemem.l	0xE0005000	0xFE000C21 # BR2 base address at 0xFE000000, port size 8 bit, FCM, valid
writemem.l	0xE0005004	0xFFFF83CC # OR2 32KB flash size, small page

#
# Local bus CS1 - BCSR settings
# 
writemem.l	0xE0005008	0xF8000801
writemem.l	0xE000500C	0xFFFFE9F7

#
# Local bus CS2 - NOR Flash settings
# 
writemem.l	0xE0005010	0xD0001001 # BR0 base address at 0xD0000000, port size 16 bit, GPCM, valid
writemem.l	0xE0005014	0xFE006FF7 # OR0 16MB flash size, 15 w.s., timing relaxed

# LBCR - local bus enable
writemem.l	0xE00050D0	0x00000000

# LCRR
writemem.l	0xE00050d4	0x00030002

# MRTPR - refresh timer prescaler
writemem.l	0xE0005084	0x20000000 

# System configuration registers
writemem.l	0xE0000114	0x00000000 # SICRL
ANDmem.l	0xE0000118	0x00000003 # SICRH

#DDRCDR
writemem.l	0xE0000128	0x73000002

#
# NAND Flash settings
#
writemem.l	0xE00050E0	0x0000E800 # FMR
writemem.b	0xF800000C	0xD9       # BCSR12 - On CS0 NOR Flash and on CS2 NAND Flash

writemem.b	0xF8000009	0x73       # BCSR9 - NOR Flash is Read/Write

#
# Enable time base register for flash programmer
#
writemem.l	0xE0000110	0x00400000

writereg	MSR			0x3002     # machine check enable, exception vectors at 0x0000_0000

ANDMem.l	0xE0000800	0x00300000 # ACR - Enable Core

