addreg idcode 
addreg cpuscr 
addreg noreg 
addreg ocr 
addreg osr 
addreg ocmd 
addreg iac1 
addreg iac2 
addreg iac3 
addreg iac4 
addreg dac1 
addreg dac2 
addreg dbcnt 
addreg pcfifo 
addreg dbsr 
addreg dbcr0 
addreg dbcr1 
addreg dbcr2 
addreg dbcr3 
addreg nexus3 
addreg lsrl_sel 
addreg once_en 
addreg bypass 
addreg wbbrl
addreg wbbrh
addreg msr
addreg pc
addreg ir
addreg ctl
addreg ctl_current
addreg csc
addreg dc1
addreg dc2
addreg ds
addreg rwcs
addreg rwa
addreg rwd
addreg wt
addreg dtc
addreg dtsa1
addreg dtsa2
addreg dtea1
addreg dtea2
addreg r0
addreg r1
addreg r2
addreg r3
addreg r4
addreg r5
addreg r6
addreg r7
addreg r8
addreg r9
addreg r10
addreg r11
addreg r12
addreg r13
addreg r14
addreg r15
addreg r16
addreg r17
addreg r18
addreg r19
addreg r20
addreg r21
addreg r22
addreg r23
addreg r24
addreg r25
addreg r26
addreg r27
addreg r28
addreg r29
addreg r30
addreg r31
addreg cr
addreg ctr
addreg lr
addreg xer
addreg pvr
addreg pir
addreg svr
addreg hid0
addreg hid1
addreg ctxcr
addreg altctxcr
addreg sprg0
addreg sprg1
addreg sprg2
addreg sprg3
addreg sprg4
addreg sprg5
addreg sprg6
addreg sprg7
addreg usprg0
addreg srr0
addreg srr1
addreg csrr0
addreg csrr1
addreg dsrr0
addreg dsrr1
addreg esr
addreg dear
addreg ivpr
addreg ivor0
addreg ivor1
addreg ivor2
addreg ivor3
addreg ivor4
addreg ivor5
addreg ivor6
addreg ivor7
addreg ivor8
addreg ivor9
addreg ivor10
addreg ivor11
addreg ivor12
addreg ivor13
addreg ivor14
addreg ivor15
addreg ivor32
addreg ivor33
addreg ivor34
addreg tbl
addreg tbu
addreg tcr
addreg tsr
addreg dec
addreg decar
addreg spefscr
addreg mas0
addreg mas1
addreg mas2
addreg mas3
addreg mas4
addreg mas6
addreg pid0
addreg mmucsr0
addreg mmucfg
addreg tlbcfg0
addreg tlbcfg1
addreg l1cfg0
addreg l1csr0
addreg l1finv0
addreg mcsr
addreg r0_high
addreg r0_low
addreg r1_high
addreg r1_low
addreg r2_high
addreg r2_low
addreg r3_high
addreg r3_low
addreg r4_high
addreg r4_low
addreg r5_high
addreg r5_low
addreg r6_high
addreg r6_low
addreg r7_high
addreg r7_low
addreg r8_high
addreg r8_low
addreg r9_high
addreg r9_low
addreg r10_high
addreg r10_low
addreg r11_high
addreg r11_low
addreg r12_high
addreg r12_low
addreg r13_high
addreg r13_low
addreg r14_high
addreg r14_low
addreg r15_high
addreg r15_low
addreg r16_high
addreg r16_low
addreg r17_high
addreg r17_low
addreg r18_high
addreg r18_low
addreg r19_high
addreg r19_low
addreg r20_high
addreg r20_low
addreg r21_high
addreg r21_low
addreg r22_high
addreg r22_low
addreg r23_high
addreg r23_low
addreg r24_high
addreg r24_low
addreg r25_high
addreg r25_low
addreg r26_high
addreg r26_low
addreg r27_high
addreg r27_low
addreg r28_high
addreg r28_low
addreg r29_high
addreg r29_low
addreg r30_high
addreg r30_low
addreg r31_high
addreg r31_low

set Stat(inst) 4
set Stat(icnt) 6
set Stat(vname) zen
set Stat(core) "PowerPC Zen"
set Stat(reg) {r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 pc}
set Stat(size) {8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8}
set Stat(fmt) {r0  $fmt(r0)\t r1  $fmt(r1)\t r2  $fmt(r2)\t r3  $fmt(r3)\n}
append Stat(fmt) {r4  $fmt(r4)\t r5  $fmt(r5)\t r6  $fmt(r6)\t r7  $fmt(r7)\n}
append Stat(fmt) {r8  $fmt(r8)\t r9  $fmt(r9)\t r10 $fmt(r10)\t r11 $fmt(r11)\n}
append Stat(fmt) {r12 $fmt(r12)\t r13 $fmt(r13)\t r14 $fmt(r14)\t r15 $fmt(r15)\n}
append Stat(fmt) {r16 $fmt(r16)\t r17 $fmt(r17)\t r18 $fmt(r18)\t r19 $fmt(r19)\n}
append Stat(fmt) {r20 $fmt(r20)\t r21 $fmt(r21)\t r22 $fmt(r22)\t r23 $fmt(r23)\n}
append Stat(fmt) {r24 $fmt(r24)\t r25 $fmt(r25)\t r26 $fmt(r26)\t r27 $fmt(r27)\n}
append Stat(fmt) {r28 $fmt(r28)\t r29 $fmt(r29)\t r30 $fmt(r30)\t r31 $fmt(r31)\n}
append Stat(fmt) {pc $fmt(pc)}

