#reset 0		# reset & run
#sleep 0x100
#stop

# set interrupt vectors
writereg	IVPR 	0xFFFF0000 	# IVPR (compatible to the Flash) 
writereg	IVOR15	0x0000F000	# debug (a valid instruction should exist to be fetched)
writereg	IVOR6	0x0000F700	# program

#######################################################################
# Set a breakpoint at the reset address 
writereg	IAC1		0xfffffffc
writereg	DBCR0		0x40800000
writereg	DBCR1		0x00000000
writereg	MSR		0x02000200

run
sleep 0x10
stop

writereg	DBCR0	0x41000000
writereg	IAC1	0x00000000

#######################################################################

# activate debug interrupt
writereg	MSR 0x00000200

# invalidate BR0
writemem.l 0xFF705000 0x00001000 

# ABIST off
writemem.l	0xFF720E44 0x0000000C	# L2ERRDIS[MBECCDIS]=1 L2ERRDIR[SBECCDIS]=1

####################################################################################
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200

##################################################################################
#	
#	Memory Map - LAW(Local Access Window) configuration
#
#	0x00000000	0x0fffffff	TLB1_8	DDR	 512M
#	0x10000000	0x1fffffff	TLB1_9	DDR	 512M
#	0x80000000	0xbfffffff	TLB1_1	PEX	 1GB
#	0xc0000000	0xcfffffff	TLB1_2	PCI	 256MB
#	0xd0000000	0xdfffffff	TLB1_3	PCI	 256M
#	0xf0000000 	0xf3ffffff	TLB1_5	LBC	 64M
#	0xf8000000 	0xfbffffff	TLB1_6	LBC	 64M
#	0xfc000000 	0xffffffff	TLB1_0	LBC	 64M
#
##################################################################################
# MMU initialization
#
###
# define 64MB TLB1 entry 0: 0xFC0000000 - 0xFFFFFFFF
writereg128		L2MMU_CAM0  0x80001FCA 0xFC080000 0xFC000000 0xFC000001

###
# define 1GB TLB1 entry 1: 0x80000000 - 0xBFFFFFFF
writereg128		L2MMU_CAM1  0xA0007FCA 0xFC080000 0x80000000 0x80000001

###
# define 256MB TLB1 entry 2: 0xC0000000 - 0xCFFFFFFF
writereg128		L2MMU_CAM2  0x90003FCA 0xFC080000 0xC0000000 0xC0000001

###
# define 256MB TLB1 entry 3: 0xD0000000 - 0xDFFFFFFF
writereg128		L2MMU_CAM3 0x90003FCA 0xFC080000 0xD0000000 0xD0000001

###
# define 64MB TLB1 entry 4: 0xE0000000 - 0xE3FFFFFF
writereg128		L2MMU_CAM4 0x80003FCA 0xFC080000 0xE0000000 0xE0000001

###
# define 64MB TLB entry 5: 0xF0000000 - 0xF3FFFFFF
writereg128		L2MMU_CAM5 0x80001FCA 0xFC080000 0xF0000000 0xF0000001

###
# define 64MB TLB1 entry 6: 0xF8000000 - 0xFBFFFFFF
writereg128		L2MMU_CAM6 0x80001FCA 0xFC080000 0xF8000000 0xF8000001

# define 4MB TLB1 entry 7: 0x40000000 - 0x400FFFFF
writereg128		L2MMU_CAM7  0x600003C8 0xFC000000 0x40000000 0x40000001

###
# define 256MB TLB1 entry 8: 0x00000000 - 0x0FFFFFFF
writereg128		L2MMU_CAM8 0x90003FC0 0xFC080000 0x00000000 0x00000001

###
# define 256MB TLB1 entry 9: 0x10000000 - 0x1FFFFFFF
#writereg128		L2MMU_CAM9 0x90003FC0 0xFC080000 0x10000000 0x10000001

##################################################################################
# move CCSR at 0x40000000

# CCSRBAR
# bit 12 - 23 - BASE_ADDR
writemem.l	0xFF700000	0x00040000

##################################################################################
# config BPTR register (Boot Page Translation Register)
# remove the 4k boot page from 0xFFFFF000 address
writemem.l  0x40000020  0x00000000 

# Invalidate again BR0 to prevent flash data damage in case 
# the boot sequencer re-enables CS0 access
writemem.l 0x40005000 0x00001000 

#####################################################################
#	Memory Windows
####################################################################

# LAWBAR1
# bit 12 - 31 = 0x00000000 - base addr
writemem.l	0x40000c28 	0x00000000

# LAWAR1
# bit 1 = 1 - enable window
# bit 8-11 = F - DDR
# bit 26 - 31  = 512MB - size
writemem.l	0x40000c30	0x80f0001c

# LAWBAR2
# bit 12 - 31 = 0xc0000000 - base addr
writemem.l	0x40000c48 	0x000c0000

# LAWAR2
# bit 1 = 1 - enable window
# bit 8-11 = 0 - PCI
# bit 26 - 31  = 512MB - size
writemem.l	0x40000c50	0x8000001C

# LAWBAR4
# bit 12 - 31 = 0xF0000000 - base addr
writemem.l	0x40000c88 	0x000F0000

# LAWAR4
# bit 1 = 1 - enable window
# bit 8-11 = 0 - LBC
# bit 26 - 31  = 256M - size
writemem.l	0x40000c90	0x8040001B

# LAWBAR5
# bit 12 - 31 = 0x80000000 - base addr
writemem.l	0x40000ca8 	0x00080000

# LAWAR5
# bit 1 = 1 - enable window
# bit 8-11 = 0 - PEX 1: ULI M1575
# bit 26 - 31  = 512M - size
writemem.l	0x40000cb0	0x8020001C

# LAWBAR6
# bit 12 - 31 = 0xA0000000 - base addr
writemem.l	0x40000cc8 	0x000A0000

# LAWAR6
# bit 1 = 1 - enable window
# bit 8-11 = 0 - PEX 2: PEX Slot
# bit 26 - 31  = 512M - size
writemem.l	0x40000cd0	0x8010001C

####################################################################
#
# DDR initalization
#
#####################################################

# DDR_SDRAM_CFG
writemem.l	0x40002110 0x42000000

# configure the appropriate DDR controller registers

# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002000 0x0000001f ; DDR CS0

# CS0_CONFIG
writemem.l 0x40002080 0x80010202

# TIMING_CFG_0
writemem.l	0x40002104 0x00260802

# TIMING_CFG_1
writemem.l	0x40002108 0x3935D322

# TIMING_CFG_2
writemem.l	0x4000210C 0x14904CC8

# DDR_SDRAM_MODE
writemem.l	0x40002118 0x00480432

# DDR_SDRAM_INTERVAL
writemem.l	0x40002124 0x06180100

# DDR_SDRAM_CFG2
writemem.l	0x40002114 0x04400000

# DDR_SDRAM_CLK_CNTL
writemem.l	0x40002130 0x03800000

sleep 200

# enable the memory interface
# DDR_SDRAM_CFG
# enable the memory interface
writemem.l	0x40002110 0xc3008000

##################################################################################
# configure local bus memory controller 

# CS0 - Flash Bank
writemem.l 0x40005000 0xFF801001 # BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid
writemem.l 0x40005004 0xFF806FF7 # OR0 8MB flash size

# CS1 - PromJet
writemem.l 0x40005008 0xFE801001 # BR1 base address at 0xFE800000, port size 16 bit, GPCM, valid
writemem.l 0x4000500C 0xFF806FF7 # OR1 8MB flash size

# CS3 - PIXIS
writemem.l 0x40005018 0xF8100801 # BR3 base address at 0xF8100000, port size 8 bit, GPCM, valid
writemem.l 0x4000501C 0xFFF00FF7 # OR3 1 MB

####################################################################
# interrupt vectors initialization

###
# interrupt vectors in DDR
#
writereg	IVPR 0x00000000 	# IVPR (default reset value) 

# interrupt vector offset registers 
writespr	400 0x00000100	# IVOR0 - critical input
writespr	401 0x00000200	# IVOR1 - machine check
writespr	402 0x00000300	# IVOR2 - data storage
writespr	403 0x00000400	# IVOR3 - instruction storage
writespr	404 0x00000500	# IVOR4 - external input
writespr	405 0x00000600	# IVOR5 - alignment
writespr	406 0x00000700	# IVOR6 - program
writespr	408 0x00000c00	# IVOR8 - system call
writespr	410 0x00000900	# IVOR10 - decrementer
writespr	411 0x00000f00	# IVOR11 - fixed-interval timer interrupt
writespr	412 0x00000b00	# IVOR12 - watchdog timer interrupt
writespr	413 0x00001100	# IVOR13 - data TLB errror
writespr	414 0x00001000	# IVOR14 - instruction TLB error
writespr	415 0x00001500	# IVOR15 - debug
writespr	528 0x00001600	# IVOR32 - SPE-APU unavailable
writespr	529 0x00001700	# IVOR33 - SPE-floating point data exception
writespr	530 0x00001800	# IVOR34 - SPE-floating point round exception
writespr	531 0x00001900	# IVOR35 - performance monitor

# put a valid opcode at debug and progrm exception vector address
writemem.l 0x00000700 0x48000000
writemem.l 0x00001500 0x48000000

#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200

############
#
# time base enable
writespr	1008	0x00004000	# HID0

############
#
# Workaround for Errata CPU1: 
# A core hang possible while executing a msync instruction and a snoopable transaction 
# from an I/O master tagged to make quick forward progress is present.
ORmem.l 0x40001010 0x00010000

######
#
# CW debugger settings
#

#Trap debug event enable
writereg	DBCR0		0x41000000

# Clear debug event status
writereg	DBSR		0x01CF0000

#  set the PC at the reset address (for debug-->connect)
writereg	PC	0xfffffffc
# for debugging starting at program entry point when stack is not initialized
writereg	SP	0x0000000F

