#!<cw>

change	MBAR	0xFF400000

# change internal MMR base from 0xff400000 (reset value) to 0xe0000000
change IMMRBAR  0xe0000000 

# update MBAR accordingly to IMMRBAR
change	MBAR	0xe0000000


##############################################
# System Configuration - Local Access Windows 
##############################################

# Local Bus Local Access Windows
#################################
# WINDOW 0 - NOR FLASH

# LBLAWBAR0  - begining at 0xfe000000 
change LBLAWBAR0  0xfe000000 

# LBLAWAR0   - enable, size = 32MB 
change LBLAWAR0   0x80000018 

# WINDOW 1 - NAND Flash

# LBLAWBAR1  - begining at 0xf8000000
change LBLAWBAR1  0xf8000000 

# LBLAWAR1   - enable, size = 32MB 
change LBLAWAR1   0x80000018 

# WINDOW 2 - VSC7385

# LBLAWBAR2  - begining at 0xfc100000
change LBLAWBAR2  0xf0000000 

# LBLAWAR2   - enable, size = 128kB
change LBLAWAR2   0x80000010 

# WINDOW 3 - Read Write Buffer

# LBLAWBAR3  - begining at 0xfa000000
change LBLAWBAR3  0xfa000000 

# LBLAWAR3   - enable, size = 32kB
change LBLAWAR3   0x8000000e 

# PCI Local Access Windows
#################################

# WINDOW 0

# PCILAWBAR0 - begining at 0x80000000
change PCILAWBAR0 0x80000000 

# PCILAWAR0  - enable, size = 512MB
change PCILAWAR0  0x8000001c 

# WINDOW 1

# PCILAWBAR1 - begining at 0xa0000000
change PCILAWBAR1 0xa0000000 

# PCILAWBAR1 - begining at 0xa000000
change PCILAWBAR1 0x8000001c 

# DDR Local Access Windows
#################################

# WINDOW 0 - 1st DDR SODIMM

# DDRLAWBAR0 - begining at 0x00000000
change DDRLAWBAR0 0x00000000 

# DDRLAWAR0  - enable, size = 128MB
change DDRLAWAR0  0x8000001a 

	#*********************************
	# DDR2 Controller Registers
	#*********************************

	#DDRCDR
	change DDRCDR 0x73000002

	# DDR_SDRAM_CLK_CNTL
	# CLK_ADJST = b'010' ; 2 Clocks
        change DDR_SDRAM_CLK_CNTL 0x02000000

	# CS0_BNDS
	# SA0 = b'000000000000'
	# EA0 = b'000000000111'
	# 128MB	
	change CS0_BNDS 0x00000007 
	
	# CS0_CONFIG
	# CS_0_EN = b'1'
	# AP_0_EN = b'1'
	# ODT_RD_CFG = b'0'
	# ODT_WR_CFG = b'1'
	# BA_BITS_CS_0 = b'00'
	# ROW_BITS_CS_0 = b'001' ; 13 row bits
	# COL_BITS_CS_0 = b'010' ; 10 columns bits
	change CS0_CONFIG 0x80840102

	# TIMING_CFG_3
	# EXT_REFREC = b'000' ; 0 Clocks
	change TIMING_CFG_3 0x00000000
	

	# TIMING_CONFIG_1
	# bit 1-3 = 2 - PRETOACT precharge activate interval 2 clock cycles
	# bit 4-7 = 6 - ACTTOPRE activate to precharge interval 6 clock cycles
	# bit 9-11 = 2 = ACTTORW activate to r/w interval 2 clock cycles 
	# bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles
	# bit 16 - 19 = 6 - REFREC refresh recovery time 14 clock cycles 
	# bit 21 - 23 = 2 - WRREC data to precharge interval 2 clock cycles 
	# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
	# bit 29 - 31 = 2 - WRTORD write data to read command interval 2 clock cycles
	change TIMING_CFG_1 0x26256222

	# TIMING_CONFIG_2
	# bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay
	change TIMING_CFG_2 0x0f9028c7


	
	# TIMING_CFG_0
	# RWT = b'00' ; 0 Clocks
	# WRT = b'00' ; 0 Clocks
	# RRT = b'00' ; 0 Clocks
	# WWT = b'00' ; 0 Clocks
	# ACT_PD_EXIT = b'010' ; 2 Clocks
	# PRE_PD_EXIT = b'010' ; 2 Clocks
	# ODT_PD_EXIT = b'1000' ; 8 Clocks
	# MRS_CYC = b'0010' ; 2 Clocks
	change TIMING_CFG_0 0x00220802

	# DDR_SDRAM_CFG
	# MEM_EN = b'0'
	# SREN = b'1'
	# RD_EN = b'0'
	# SDRAM_TYPE = b'011'
	# DYN_PWR = b'0'
	# 32_BE = b'1'
	# 8_BE = b'0'
	# NCAP = b'0'
	# 2T_EN = b'0'
	# x32_EN = b'0'
	# PCHB8 = b'0'
	# HSE = b'0'
	# MEM_HALT = b'0'
	# BI = b'0'
	change DDR_SDRAM_CFG 0x43080000
	
	# DDR_SDRAM_CFG_2
	# FRC_SR = b'0'
	# DQS_CFG = b'00'
	# ODT_CFG = b'10'
	# NUM_PR = b'0001'
	# D_INIT = b'0'
	change DDR_SDRAM_CFG_2 0x00401000

	# DDR_SDRAM_MODE
	# Extended Mode Register: Outputs=0 or 1?
	# Mode Register
	change DDR_SDRAM_MODE 0x44400232
	
	# DDR_SDRAM_MODE_2
	# Extended Mode Register 2
	# Extended Mode Register 3
	change DDR_SDRAM_MODE_2 0x8000c000
		
	# DDR_SDRAM_INTERVAL
	# REFINT = 800 Clocks
	# BSTOPRE = 100 Clocks
	change DDR_SDRAM_INTERVAL 0x03200064
	
	#delay before enable
	wait 300
	#Enable: DDR_SDRAM_CFG
	change DDR_SDRAM_CFG 0xc3080000


##############################################
# Local Bus Interface (LBIU) Configuration
##############################################

# CS0 - 8MB NOR FLASH 

# BR0 base address at 0xFE000000, port size 16 bit, GPCM, valid
change BR0 0xfe001001 

# OR0 8MB flash size, 15 w.s., timing relaxed
change OR0 0xfe006ff7 

# CS1 - NAND FLASH      

# BR1 base address at 0xF8000000, port size 8 bit, FCM, valid
change	BR1 0xF8000C21 

# OR1 32KB flash size, small page
change	OR1 0xFFFF93CC 

# CS2 - VSC7385

# BR2 base address at 0xF0000000, port size 8 bit, GPCM, valid
change BR2 0xf0000801 

# OR2 128KB
change OR2 0xFFFE09FF 

# CS3 - Read Write Buffer

# BR3 base address at 0xfa000000, port size 8 bit, GPCM, valid
change BR3 0xfa000801 

# OR3 32KB
change OR3 0xFFFF8FF7 

# LBCR - local bus enable
change LBCR  0x00000000

# LCRR
# bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles 
# bit 28 - 31 = 0x0010  - CLKDIV - system clock:memory bus clock = 2
change LCRR 0x00030002


# FP available, machine check disable, exception vectors at 0x0000_0000
change MSR 0x2000 

# ACR - Enable Core
change ACR 0x00000000 


# write board LEDs
change 0xfa000000 0x00000000 

#
# NAND Flash settings
#

change	FMR 0x0000E000


# MRTPR - refresh timer prescaler
change MRTPR 0x20000000 



change SP 0xf