#######################################
#FILE
#	$RCSfile: 8560ADS_init.cfg,v $
#	$Date: 2004/03/01 15:42:33 $
#	$Revision: 1.19 $
#DESCRIPTION
#   Initialization file for
#   PQIII-8560ADS board
#COPYRIGHT	
#	(c) 2003 Metrowerks Corporation
#	All rights reserved.
#HISTORY
#   $Log: 8560ADS_init.cfg,v $
#   Revision 1.19  2004/03/01 15:42:33  milies
#   added workaround for pq3 rev 2.0.1
#
#   Revision 1.18  2004/02/19 18:17:42  tmadan
#   add a loop at Debug interrupt handler. This will make HW breaks to work
#
#   Revision 1.17  2004/02/17 13:19:28  milies
#   - added  two 64MB TLB1 entries for DDR instead of one 256MB entry;
#   - modified LAW1 size to 1GB starting from 0xC0000000
#
#   Revision 1.16  2004/01/30 16:41:56  C-vcambrea
#   Trap debug event enable in DBCR0.
#
#   Revision 1.15  2003/12/19 15:28:39  milies
#   added ZBT SRAM initialization and workaround for Local Bus DLL lock
#   
########################################


# inform the debugger about the 8560 memory-mapped register base CCSRBAR 
#setMMRBaseAddr 0xFF700000		# CCSR default

writemem.l 0xFF705000 0x00001000 # invalidate BR0
writemem.l 0xFF7e0e10 0x81000000 # DDRDLLCR = 0x81000000 for DDR DDL bypass mode
sleep 0x20

##################################################################################
# Workaround for ABIST off
writemem.l	0xFF720E44 0x0000000C	# L2ERRDIS[MBECCDIS]=1 L2ERRDIR[SBECCDIS]=1


##################################################################################
# configure internal SRAM at highest memory address to cover the default MMU page

# L2CTL
# bit 0 = 0 		- L2E: L2 SRAM disabled
# bit 4-5 = 01 		- L2BLKSZ: = 128KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0x64010000

# L2SRBAR0
# bit 0-17 = 0xFFFE0000 - BASE addr: 4GB-128KB
writemem.l	0xFF720100	0xFFFE0000

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM enable
# bit 4-5 = 01 		- L2BLKSZ: = 128KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0xA4010000


#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200


#######################################################################
# workaround for PQ3 rev 2.0.1 

# set IVOR15 (debug) interrupt vectors in SRAM at 0xFFFFF000
writereg	IVPR 	0xFFFF0000 	# IVPR (default reset value) 
writereg	IVOR15 	0x0000F000	# IVOR15 - debug

# write at the reset address a branch to 0xFFFFF000
writemem.l  0xfffffffc  0x4BFFF004  # branch to 0xfffff000

# set hardware breakpoint at 0xFFFFF000 address
writereg	DBCR0		0x41800000
writereg	IAC1		0xFFFFF000
writemem.l	0xFFFFF000	0x60000000	# nop (or any valid opcode)

run
sleep 0x10
stop

writereg	DBCR0	0x41000000
writereg	IAC1	0x00000000

# end of the workaround
#######################################################################


###################################################################################
# Invalidate cache
###################################################################################
writemem.l	0xFFFFF008	0x7C12FAA6	#	mfspr	r0,L1CSR0	/* invalidate d-cache */
writemem.l	0xFFFFF00C	0x60000002	#	ori	r0,r0,0x0002
writemem.l	0xFFFFF010	0x7C0004AC	#	msync		
writemem.l	0xFFFFF014	0x4C00012C	#	isync		
writemem.l	0xFFFFF018	0x7C12FBA6	#	mtspr	L1CSR0,r0
writemem.l	0xFFFFF01C	0x4C00012C	#	isync		
writemem.l	0xFFFFF020	0x7C12FAA6	#	mfspr	r0,L1CSR0	/* disable d-cache */
writemem.l	0xFFFFF024	0x3C20FFFF	#	lis	rsp,-1
writemem.l	0xFFFFF028	0x6021FFFE	#	ori	rsp,rsp,0xfffe
writemem.l	0xFFFFF02C	0x7C000838	#	and	r0,r0,rsp
writemem.l	0xFFFFF030	0x7C0004AC	#	msync		
writemem.l	0xFFFFF034	0x4C00012C	#	isync		
writemem.l	0xFFFFF038	0x7C12FBA6	#	mtspr	L1CSR0,r0
writemem.l	0xFFFFF03C	0x4C00012C	#	isync		
writemem.l	0xFFFFF040	0x7C13FAA6	#	mfspr	r0,L1CSR1	/* invalidate i-cache */
writemem.l	0xFFFFF044	0x60000002	#	ori	r0,r0,0x0002
writemem.l	0xFFFFF048	0x7C13FBA6	#	mtspr	L1CSR1,r0
writemem.l	0xFFFFF04C	0x4C00012C	#	isync		
writemem.l	0xFFFFF050	0x7C13FAA6	#	mfspr	r0,L1CSR1	/* disable i-cache */
writemem.l	0xFFFFF054	0x3C20FFFF	#	lis	rsp,-1
writemem.l	0xFFFFF058	0x6021FFFE	#	ori	rsp,rsp,0xfffe
writemem.l	0xFFFFF05C	0x7C000838	#	and	r0,r0,rsp
writemem.l	0xFFFFF060	0x7C13FBA6	#	mtspr	L1CSR1,r0
writemem.l	0xFFFFF064	0x4C00012C	#	isync		
writemem.l	0xFFFFF068	0x7C0004AC	#	msync		
writemem.l	0xFFFFF06c	0x48000000	# 	 			/* infinite loop */

writereg	PC	0xfffff008

run
sleep 0x10
stop



##################################################################################
# MMU initialization
#
# MAS0: MMU read/write and replacement control 
# MAS1: descriptor context and configuration control
# MAS2: EPN and page attributes
# MAS3: RPN and access control
# MAS4: Hardware replacement assist configuration


###
# define 1MB TLB1 entry 1 - CCSR: 0x40000000 - 0x400FFFFF
writespr	624 0x10010000	# MAS0 
writespr	625 0x80000500	# MAS1 
writespr	626 0x40000008	# MAS2 
writespr	627 0x4000003f	# MAS3 
writespr	628 0x00000000	# MAS4

writemem.l	0xFFFFF000	0x7C0007A4	# tlbwe
writemem.l	0xFFFFF004	0x4C00012C	# isync
writemem.l	0xFFFFF008	0x7C0004AC	# msync
writemem.l	0xFFFFF00c	0x48000000	# infinite loop
# write tlb entry
writereg	PC	0xfffff000
run
stop

###
# define 64MB TLB1 entry 2 - SDRAM: 0xC0000000 - 0xC3FFFFFF
writespr	624 0x10020000	# MAS0 
writespr	625 0x80000800	# MAS1 
writespr	626 0xC0000008	# MAS2 
writespr	627 0xC000003f	# MAS3 
# write tlb entry
writereg	PC	0xfffff000
run
stop

###
# define 64MB TLB1 entry 3 - DDR: 0x00000000 - 0x03FFFFFF
writespr	624 0x10030000	# MAS0 
writespr	625 0x80000800	# MAS1 
writespr	626 0x00000000	# MAS2 
writespr	627 0x0000003f	# MAS3 
# write tlb entry
writereg	PC	0xfffff000
run
stop

###
# define 64MB TLB1 entry 4 - DDR: 0x04000000 - 0x07FFFFFF
writespr	624 0x10040000	# MAS0 
writespr	625 0x80000800	# MAS1 
writespr	626 0x04000000	# MAS2 
writespr	627 0x0400003f	# MAS3 
# write tlb entry
writereg	PC	0xfffff000
run
stop


###
# define 16MB TLB entry 5 - FLASH: 0xFF000000 - 0xFFFFFFFF
writespr	624 0x10050000	# MAS0 
writespr	625 0x80000700	# MAS1 
writespr	626 0xFF000008	# MAS2 
writespr	627 0xFF00003f	# MAS3 

# write tlb entry
writereg	PC	0xfffff000
run
stop


###
# define 16MB TLB entry 6 - 0xF0000000 - 0xF0FFFFFF
writespr	624 0x10060000	# MAS0 
writespr	625 0x80000700	# MAS1 
writespr	626 0xF0000008	# MAS2 
writespr	627 0xF000003f	# MAS3 
# write tlb entry
writereg	PC	0xfffff000
run
stop

###
# define 2MB TLB1 entry 6: 0xF2000000 - 0xF23FFFFF
# for ZBT SRAM

writespr	624 0x10060000	# MAS0 
writespr	625 0x80000600	# MAS1 
writespr	626 0xF2000008	# MAS2
writespr	627 0xF200003f	# MAS3 

# write tlb entry
#
writereg	PC	0xfffff000

run
stop


##################################################################################
# move CCSR at 0x40000000
# 

# CCSRBAR
# bit 12 - 23 - BASE_ADDR
writemem.l	0xFF700000	0x00040000

# inform the debugger
#setMMRBaseAddr 0x40000000


##################################################################################
# config BPTR register (Boot Page Translation Register)
# disable boot page (if enabled by boot sequencer)
writemem.l  0x40000020  0x00000000 


####################################################################
# workaround for DLL stabilization (DDR DLL Controller Register)
####################################################################

writemem.l	0xFFFFF074	0x3FC0400E  	#	lis      r30,0x400E	
writemem.l	0xFFFFF078	0x3BDE0E10  	#	addi     r30,r30,0x0E10
writemem.l	0xFFFFF07c	0x83FE0000  	#	lwz      r31,0(r30)
writemem.l	0xFFFFF080	0x57FF043E  	#	clrlwi   r31,r31,16
writemem.l	0xFFFFF084	0x57FF801E  	#	slwi     r31,r31,16
writemem.l	0xFFFFF088	0x67FF8000  	#	oris     r31,r31,0x8000
writemem.l	0xFFFFF08c	0x93FE0000  	#	stw      r31,0(r30)
writemem.l	0xFFFFF090	0x48000000	    #	/* infinite loop */

writereg	PC	0xfffff074

run
sleep 0x10
stop


####################################################################
# workaround for Local Bus DLL lock
####################################################################
writemem.l	0xFFFFF344	0x3CA00003  #lis      r5,3
writemem.l	0xFFFFF348	0x60A50002  #ori      r5,r5,0x0002	#LCRR, enable DLL
writemem.l	0xFFFFF34C	0x3C804000  #lis      r4,0x4000
writemem.l	0xFFFFF350	0x90A450D4  #stw      r5,0x50d4(r4)
writemem.l	0xFFFFF354	0x3CA00000  #lis      r5,0
writemem.l	0xFFFFF358	0x60A53000  #ori      r5,r5,0x3000	#wait
writemem.l	0xFFFFF35C	0x7CA903A6  #mtctr    r5
writemem.l	0xFFFFF360	0x42000000  #bdnz     0
writemem.l	0xFFFFF364	0x3CA0400E  #lis      r5,0x400e		#LBDLLCR
writemem.l	0xFFFFF368	0x60A50E20  #ori      r5,r5,0x0e20
writemem.l	0xFFFFF36C	0x80C50000  #lwz      r6,0(r5)
writemem.l	0xFFFFF370	0x54C6043E  #clrlwi   r6,r6,16
writemem.l	0xFFFFF374	0x54C6801E  #slwi     r6,r6,16
writemem.l	0xFFFFF378	0x64C68000  #oris     r6,r6,0x8000
writemem.l	0xFFFFF37C	0x90C50000  #stw      r6,0(r5)
writemem.l	0xFFFFF380	0x48000000

writereg	PC	0xfffff344

run
sleep 0x10
stop

##################################################################################
# disable internal SRAM (used for MMU initialization)

# L2CTL
# bit 0 = 0 		- L2E: L2 SRAM disable
# bit 4-5 = 01 		- L2BLKSZ: = 128KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0x40020000	0x20000000


##################################################################################
# configure local access windows
# 
# window 0: DDR = F
# window 1: Local Bus = 4

# LAWBAR0
# bit 12 - 31 = 0x0 - base addr
writemem.l	0x40000c08 	0x00000000

# LAWAR0
# bit 1 = 1 - enable window
# bit 8-11 = F - DDR
# bit 26 - 31  = 128MB - size
writemem.l	0x40000c10	0x80f0001a

# LAWBAR1
# bit 12 - 31 = 0xc0000000 - base addr
writemem.l	0x40000c28 	0x000c0000

# LAWAR1
# bit 1 = 1 - enable window
# bit 8-11 = 4 - local bus
# bit 26 - 31  = 1GB - size
writemem.l	0x40000c30	0x8040001D



####################################################################
#
# DDR initalization
#

# configure the appropriate DDR controller registers

# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002000 0x00000007 ; DDR CS0

# CS0_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 8 = 0 - AP_0_EN auto precharge for w/r disable
# bit 21 - 23 = 0 - ROW_BITS_CS_0 12 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 10 columns
writemem.l 0x40002080 0x80000101

# TIMING_CONFIG_1
# bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles
# bit 5-7 = 7 - ACTTOPRE activate to precharge interval 7 clock cycles
# bit 9-11 = 5 = ACTTORW activate to r/w interval 5 cloc cycles
# bit 13 - 15 = 4 - CASLAT CAS latency 4 clock cycles
# bit 16 - 19 = 4 - REFREC refresh recovery time 4 clock cycles
# bit 22 - 23 = 3 - WRREC data to precharge interval 3 clock cycles
# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
# bit 30 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle
writemem.l	0x40002108 0x37534321

# TIMING_CONFIG_2
# bit 19-21  = b010  - WR_DATA_DELAY - 4/8 clock delay
writemem.l	0x4000210C 0x00000800

# disable the memory interface with DDR_SDRAM_CFG[MEM_EN]
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 0 - SREN disable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l	0x40002110 0x02000000

# DDR_SDRAM_MODE
# bit 0 - 15 = 0x0000 
# bit 16 - 31 = 0x0062 SDMODE 
writemem.l	0x40002118 0x00000062

# DDR_SDRAM_INTERVAL
# bit 2 - 15 = 0x03a3 - REFINT 
# bit 18 - 31 = 0  - BSTOPRE auto precharge r/w commands used
writemem.l	0x40002124 0x03a30100

sleep 200

# enable the memory interface
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic is disabled
writemem.l	0x40002110 0xc2000000


##################################################################################
# configure local bus memory controller

# The CS0 configuration for PQIII-8560ADS board rev. Pilot
writemem.l 0x40005000 0xFF801001 # BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid
writemem.l 0x40005004 0xFF806F97 # OR0 8MB flash size, 15 w.s., timing relaxed
writemem.l 0x4000500C 0xFF806F97 # OR1 8MB flash size, 15 w.s., timing relaxed
writemem.l 0x40005008 0xFF001001 # BR1 base address at 0xFF000000, port size 16 bit, GPCM, valid

writemem.l 0x40005014 0xfc006901 # OR2
writemem.l 0x40005010 0xc0001861 # BR2
writemem.l 0x400050d0 0x00000000 # LBCR (configuration register)
writemem.l 0x400050d4 0x80030008 # LCRR
writemem.l 0x400050a4 0x3f000000 # LSRT
writemem.l 0x40005084 0x20000000 # MPTPR
writemem.l 0x40005094 0x0063b723 # LSDMR 

writemem.l 0x40005094 0x2863b723 # LSDMR - init sdram sequence
writemem.l 0xC0000000 0x000000ff # 
writemem.l 0x40005094 0x0863b723 # 
writemem.l 0xC0000000 0x000000ff #
writemem.l 0xC0000000 0x000000ff #
writemem.l 0xC0000000 0x000000ff #
writemem.l 0xC0000000 0x000000ff #
writemem.l 0xC0000000 0x000000ff #
writemem.l 0xC0000000 0x000000ff #
writemem.l 0xC0000000 0x000000ff #
writemem.l 0xC0000000 0x000000ff #
writemem.l 0x40005094 0x1863B723 #
writemem.l 0xC00000cc 0x000000ff #
writemem.l 0x40005094 0x4063B723 #


####################################################################
# interrupt vectors initialization

###
# interrupt vectors in DDR
#
writereg	IVPR 0x00000000 	# IVPR (default reset value) 

# interrupt vector offset registers 
writespr	400 0x00000100	# IVOR0 - critical input
writespr	401 0x00000200	# IVOR1 - machine check
writespr	402 0x00000300	# IVOR2 - data storage
writespr	403 0x00000400	# IVOR3 - instruction storage
writespr	404 0x00000500	# IVOR4 - external input
writespr	405 0x00000600	# IVOR5 - alignment
writespr	406 0x00000700	# IVOR6 - program
writespr	408 0x00000c00	# IVOR8 - system call
writespr	410 0x00000900	# IVOR10 - decrementer
writespr	411 0x00000f00	# IVOR11 - fixed-interval timer interrupt
writespr	412 0x00000b00	# IVOR12 - watchdog timer interrupt
writespr	413 0x00001100	# IVOR13 - data TLB errror
writespr	414 0x00001000	# IVOR14 - instruction TLB error
writespr	415 0x00001500	# IVOR15 - debug
writespr	528 0x00001600	# IVOR32 - SPE-APU unavailable
writespr	529 0x00001700	# IVOR33 - SPE-floating point data exception
writespr	530 0x00001800	# IVOR34 - SPE-floating point round exception
writespr	531 0x00001900	# IVOR35 - performance monitor


#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200


############
#
# time base enable
writespr	1008	0x00004000	# HID0

######
#
# CW debugger settings
#

#Trap debug event enable
writereg	DBCR0		0x41000000

#  set the PC at the reset address (for debug-->connect)
writereg	PC	0xfffffffc
# put a valid opcode at 0x700
writemem.l 0x00000700 0x48000000
writemem.l 0x00001500 0x48000000
# for debugging starting at program entry point when stack is not initialized
writereg	SP	0x0000000F

