#######################################
#FILE
# $RCSfile: 8349MDS_init.cfg,v $
# $Date: 2005/12/22 12:41:59 $
# $Revision: 1.5 $
#DESCRIPTION
#
#COPYRIGHT 
# (c) 2004 Metrowerks Corporation
# All rights reserved.
#HISTORY
# $Log: 8349MDS_init.cfg,v $
# Revision 1.5  2005/12/22 12:41:59  adrpopa1
# Update with Mandy's recommendations.
#
# Revision 1.4  2005/12/13 16:07:43  vcambrea
# fix from Mandy .
#
# Revision 1.3  2005/10/06 08:25:07  milies
# Use ANDMem.l instead of writemem.l for ACR register
# Bits 10-11 should get a value different than '00' when the core is operating at below x2 of the system clock (i.e. x1.5).
#
# Revision 1.2  2005/09/14 13:56:37  vcambrea
# updated with 8349MDS Rev. A DDR timings
#
# Revision 1.1  2005/09/09 12:32:13  mposirca
# were renamed into for board rename into 8349MDS
#
# Revision 1.2  2005/03/29 14:29:45  vcambrea
# Initialize Local Access Window 0 with the internal memory map location
#
# Revision 1.1  2004/12/22 14:31:20  vcambrea
# debugger initialization file for the 8349SYS board
# 1st revision
# 
########################################

#setMMRBaseAddr 0xFF400000
writereg	MBAR	0xFF400000

# change internal MMR base from 0xff400000 (reset value) to 0xe0000000
writemem.l 0xff400000 0xe0000000 # IMMRBAR = 0xe0000000

#setMMRBaseAddr 0xe0000000
writereg	MBAR	0xe0000000


##############################################
# System Configuration - Local Access Windows 
##############################################

# Local Bus Local Access Windows
#################################
# WINDOW 0 - configuration space - Initially mapped by RCWHR[BMS], relocated to 0xe0000000
writemem.l 0xe0000020 0xe0000000 # LBLAWBAR0  - begining at 0xe0000000

# WINDOW 1 - FLASH
writemem.l 0xe0000028 0xff800000 # LBLAWBAR1  - begining at 0xff800000
writemem.l 0xe000002c 0x80000016 # LBLAWAR1   - enable, size = 8MB 

# WINDOW 2 - board BCSRs
writemem.l 0xe0000030 0xf8000000 # LBLAWBAR2  - begining at 0xf8000000
writemem.l 0xe0000034 0x8000000e # LBLAWAR2   - enable, size = 32KB 

# WINDOW 3 - local bus SDRAM
writemem.l 0xe0000038 0xf0000000 # LBLAWBAR3  - begining at 0xf0000000
writemem.l 0xe000003c 0x80000019 # LBLAWAR3   - enable, size = 64MB


# PCI Local Access Windows
#################################
# WINDOW 0
writemem.l 0xe0000060 0x80000000 # PCILAWBAR0 - begining at 0x80000000
writemem.l 0xe0000064 0x8000001c # PCILAWAR0  - enable, size = 512MB

# WINDOW 1
writemem.l 0xe0000068 0xa0000000 # PCILAWBAR1 - begining at 0xa0000000
writemem.l 0xe000006c 0x8000001c # PCILAWAR1  - enable, size = 512MB

# DDR Local Access Windows
#################################
# WINDOW 0 - 1st DDR SODIMM
writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000
writemem.l 0xe00000a4 0x8000001b # DDRLAWAR0  - enable, size = 256MB

# WINDOW 1 - 2nd DDR SODIMM
writemem.l 0xe00000a8 0x10000000 # DDRLAWBAR1 - begining at 0x10000000
writemem.l 0xe00000ac 0x8000001b # DDRLAWAR1  - enable, size = 256MB


##############################################
# DDR Controller Configuration
##############################################

# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002000 0x00100017 ; 0x10000000 - 0x17FFFFFF

# CS0_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 21 - 23 = 0 - ROW_BITS_CS_0 13 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 9 columns
writemem.l 0xe0002080 0x80000101

# CS1_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002008 0x0018001f ; 0x18000000 - 0x1FFFFFFF

# CS1_CONFIG
# bit 0 = 1 - CS_1_EN CS1 enable
# bit 21 - 23 = 1 - ROW_BITS_CS_1 13 rows
# bit 29 - 31 = 1 - COL_BITS_CS_1 9 columns
writemem.l 0xe0002084 0x80000101

# CS2_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002010 0x00000007 ; 0x00000000 - 0x07FFFFFF

# CS2_CONFIG
# bit 0 = 1 - CS_2_EN CS2 enable
# bit 21 - 23 = 1 - ROW_BITS_CS_2 13 rows
# bit 29 - 31 = 1 - COL_BITS_CS_2 9 columns
writemem.l 0xe0002088 0x80000101

# CS3_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xe0002018 0x0008000f  ; 0x08000000 - 0x09FFFFFF

# CS3_CONFIG
# bit 0 = 1 - CS_3_EN CS3 enable
# bit 21 - 23 = 1 - ROW_BITS_CS_3 13 rows
# bit 29 - 31 = 1 - COL_BITS_CS_3 9 columns
writemem.l 0xe000208C 0x80000101

# TIMING_CONFIG_1
# bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles
# bit 4-7 = 7 - ACTTOPRE activate to precharge interval 7 clock cycles
# bit 9-11 = 3 = ACTTORW activate to r/w interval 3 clock cycles 
# bit 13 - 15 = 3 - CASLAT CAS latency 2.5 clock cycles
# bit 16 - 19 = 3 - REFREC refresh recovery time 11 clock cycles 
# bit 21 - 23 = 3 - WRREC data to precharge interval 3 clock cycles 
# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
# bit 29 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle
writemem.l 0xe0002108 0x36332321

# TIMING_CONFIG_2
# bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay
writemem.l 0xe000210C 0x00000800

# temporary disable the memory interface for reconfiguration
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l 0xe0002110 0x42000000

# DDR_SDRAM_MODE
# bit 0 - 15 = 0x2000  - ESDMODE
# bit 16 - 31 = 0x0162 - SDMODE 
writemem.l 0xe0002118 0x00000022

# DDR_SDRAM_INTERVAL
# bit 2 - 15 = 0x45b0 - REFINT 
# bit 18 - 31 = 0x0100  - BSTOPRE auto precharge r/w commands used
writemem.l 0xe0002124 0x04060100

sleep 300

# enable the DDR memory controller
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic enabled
writemem.l 0xe0002110 0xc2008000 

# DDR_SDRAM_CLK_CNTL
writemem.l 0xE0002130 0xC2000000


##############################################
# Local Bus Interface (LBIU) Configuration
##############################################

# CS0 - 8MB FLASH 
writemem.l 0xe0005000 0xff801001 # BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid
writemem.l 0xe0005004 0xff806ff7 # OR0 8MB flash size, 15 w.s., timing relaxed

# CS1 - board BCSRs
writemem.l 0xe0005008 0xf8000801 # BR1 base address at 0xF8000000, port size 8 bit, GPCM, valid
writemem.l 0xe000500c 0xffffe9f7 # OR1 32KB size, 15 w.s., timing relaxed

# CS2 - 64MB SDRAM
writemem.l 0xe0005014 0xfc006901 # OR2 32KB size, 13 rows, 9 cols, 64MB
writemem.l 0xe0005010 0xf0001861 # BR2 base address at 0xF0000000, port size 32 bit, SDRAM, valid

# LBCR - local bus enable
writemem.l 0xe00050d0 0x00000000

# LCRR
# bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles 
# bit 28 - 31 = 0x0100  - CLKDIV - system clock:memory bus clock = 4
writemem.l 0xe00050d4 0x00030004

# LSRT - refresh timer
writemem.l 0xe00050a4 0x3f000000

# MRTPR - refresh timer prescaler
writemem.l 0xe0005084 0x20000000 

# LSDMR - init sdram sequence
writemem.l 0xe0005094 0x0063b723 
writemem.l 0xe0005094 0x2863b723
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xe0005094 0x0863b723
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xf0000000 0x000000ff 
writemem.l 0xe0005094 0x1863b723
writemem.l 0xf00000cc 0x000000ff 
writemem.l 0xe0005094 0x4063b723


ANDMem.l 0xe0000118 0x00000003 # SICRH

writereg MSR 0x3000 #machine check enable, exception vectors at 0x0000_0000

#unlock flash in BCSR1
writemem.b 0xf8000001 0x0C

#writemem.l 0xe0000800 0x00000000 # ACR
ANDMem.l    0xe0000800 0x00300000 # ACR - bits 10-11 should get a value different than '00'
                                  #       when the core is operating at below x2 of the system clock


#writemem.l 0x6FC 0x60000000 # 
#writemem.l 0x700 0x48000000 # write a valid opcode at program exception
