set msc8144sc_core_regs(core) {
    d0
    d0_e
    d1
    d1_e
    d2
    d2_e
    d3
    d3_e
    d4
    d4_e
    d5
    d5_e
    d6
    d6_e
    d7
    d7_e
    d8
    d8_e
    d9
    d9_e
    d10
    d10_e
    d11
    d11_e
    d12
    d12_e
    d13
    d13_e
    d14
    d14_e
    d15
    d15_e
    r0
    r1
    r2
    r3
    r4
    r5
    r6
    r7
    r8
    r9
    r10
    r11
    r12
    r13
    r14
    r15
    n0
    n1
    n2
    n3
    m0
    m1
    m2
    m3
    sa0
    sa1
    sa2
    sa3
    lc0
    lc1
    lc2
    lc3
    sr
    sp
    osp
    mctl
    emr
    vba
    pctl0
    pctl1
    pc
    idcode
    esr
    emcr
    ercv_lo
    ercv_hi
    etrsmt_lo
    etrsmt_hi
    ee_ctrl
    pc_excp
    pc_next
    pc_last
    pc_detect
    edca0_ctrl
    edca1_ctrl
    edca2_ctrl
    edca3_ctrl
    edca4_ctrl
    edca5_ctrl
    edca0_refa
    edca1_refa
    edca2_refa
    edca3_refa
    edca4_refa
    edca5_refa
    edca0_refb
    edca1_refb
    edca2_refb
    edca3_refb
    edca4_refb
    edca5_refb
    edca0_mask
    edca1_mask
    edca2_mask
    edca3_mask
    edca4_mask
    edca5_mask
    edcd_ctrl
    edcd_ref
    edcd_mask
    ecnt_ctrl
    ecnt_val
    ecnt_ext
    esel_ctrl
    esel_dm
    esel_di
    esel_etb
    esel_dtb
    tb_ctrl
    tb_rd
    tb_wr
    tb_buff
    btr0
    btr1
    gcr
    idcr
}

#Create all the registers
set index 0
foreach mreg $msc8144sc_core_regs(core) {
    addreg $mreg
#$index
#    lappend core_regs(core)

#    incr index
}

#Create configuration options
addcfg scratch_mem_addr
addcfg scratch_mem_action
addcfg fast_mem
addcfg endian
addcfg slow_memory
addcfg msc8101_sypcr
addcfg disable_polling
addcfg eonce_base

set Stat(inst) 2
set Stat(icnt) 6
set Stat(vname) sc
set Stat(core) "StarCore"
set Stat(reg)  {d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 osp r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 m0 m1 m2 m3 n0 n1 n2 n3 mctl sr esr sp sa0 sa1 sa2 sa3 lc0 lc1 lc2 lc3 vba pctl0 pctl1 emcr d0_e d1_e d2_e d3_e d4_e d5_e d6_e d7_e d8_e d9_e d10_e d11_e d12_e d13_e d14_e d15_e idcode pc}
set Stat(size) {8  8  8  8  8  8  8  8  8  8  8   8   8   8   8   8   8   8  8  8  8  8  8  8  8  8  8  8   8   8   8   8   8   8  8  8  8  8  8  8  8  8    8  8   8  8   8   8   8   8   8   8   8   8   8     8     8    3    3    3    3    3    3    3    3    3    3    3     3     3     3     3     3     8      8}
set    Stat(fmt) { d0 $fmt(d0)\t  d1 $fmt(d1)\t  d2 $fmt(d2)\t  d3 $fmt(d3)\n}
append Stat(fmt) { d4 $fmt(d4)\t  d5 $fmt(d5)\t  d6 $fmt(d6)\t  d7 $fmt(d7)\n}
append Stat(fmt) { d8 $fmt(d8)\t  d9 $fmt(d9)\t d10 $fmt(d10)\t d11 $fmt(d11)\n}
append Stat(fmt) {d12 $fmt(d12)\t d13 $fmt(d13)\t d14 $fmt(d14)\t d15 $fmt(d15)\n}
append Stat(fmt) { r0 $fmt(r0)\t  m0 $fmt(m0)\t  n0 $fmt(n0)\tmctl $fmt(mctl)\n}
append Stat(fmt) { r1 $fmt(r1)\t  m1 $fmt(m1)\t  n1 $fmt(n1)\t  sr $fmt(sr)\n}
append Stat(fmt) { r2 $fmt(r2)\t  m2 $fmt(m2)\t  n2 $fmt(n2)\t esr $fmt(esr)\n}
append Stat(fmt) { r3 $fmt(r3)\t  m3 $fmt(m3)\t  n3 $fmt(n3)\t  sp $fmt(sp)\n}
append Stat(fmt) { r4 $fmt(r4)\t sa0 $fmt(sa0)\t lc0 $fmt(lc0)\t osp $fmt(osp)\n}
append Stat(fmt) { r5 $fmt(r5)\t sa1 $fmt(sa1)\t lc1 $fmt(lc1)\t vba $fmt(vba)\n}
append Stat(fmt) { r6 $fmt(r6)\t sa2 $fmt(sa2)\t lc2 $fmt(lc2)\tpctl0$fmt(pctl0)\n}
append Stat(fmt) { r7 $fmt(r7)\t sa3 $fmt(sa3)\t lc3 $fmt(lc3)\tpctl1$fmt(pctl1)\n}
append Stat(fmt) { r8 $fmt(r8)\td0_e $fmt(d0_e)\td1_e $fmt(d1_e)\temcr $fmt(emcr)\n}
append Stat(fmt) { r9 $fmt(r9)\td2_e $fmt(d2_e)\td3_e $fmt(d3_e)\n}
append Stat(fmt) {r10 $fmt(r10)\td4_e $fmt(d4_e)\td5_e $fmt(d5_e)\n}
append Stat(fmt) {r11 $fmt(r11)\td6_e $fmt(d6_e)\td7_e $fmt(d7_e)\n}
append Stat(fmt) {r12 $fmt(r12)\td8_e $fmt(d8_e)\td9_e $fmt(d9_e)\n}
append Stat(fmt) {r13 $fmt(r13)\td10e $fmt(d10_e)\td11e $fmt(d11_e)\n}
append Stat(fmt) {r14 $fmt(r14)\td12e $fmt(d12_e)\td13e $fmt(d13_e)\n}
append Stat(fmt) {r15 $fmt(r15)\td14e $fmt(d14_e)\td15e $fmt(d15_e)\tidcode $fmt(idcode)\n}
append Stat(fmt) { pc $fmt(pc)}
