#######################################
#FILE
# $RCSfile: Sandpoint_init.cfg,v $
# $Date: 2005/04/07 09:58:10 $
# $Revision: 1.7 $
#DESCRIPTION
#--------------------------------------
# Code Warrior config file for:
# Altimus X2/X3 with MPC7xx, MPC74x0
# Valis X2 with MPC745x
# Unity X4 with MPC8245
#--------------------------------------
#COPYRIGHT 
# (c) 2004 Metrowerks Corporation
# All rights reserved.
#HISTORY
# $Log: Sandpoint_init.cfg,v $
# Revision 1.7  2005/04/07 09:58:10  milies
# - added stop-sleep-reset sequence (make sure the processor is stopped prior to requesting a "reset to debug")
# - disabled the write protect to the Sandpoint motherboard flash
#
# Revision 1.6  2005/03/19 09:08:49  milies
# modified CDCR offset
#
# Revision 1.5  2005/03/19 08:42:13  milies
# changed the offsets for the ODCR, CDCR, and write the MDCR (according to Dink initialization)
#
# Revision 1.4  2005/01/26 16:59:49  c-dnegrea
# removed workaround for 755
#
# Revision 1.3  2004/12/22 08:10:38  milies
# set breakpoint at 0x700 - necessary for flash programmer
#
# Revision 1.2  2004/12/15 17:28:08  milies
# added a workaround to let ccs know where CW set the PC after reset:
# set hw breakpoint at reset address & run & stop
#
# Revision 1.1  2004/11/15 13:56:35  c-dnegrea
# files moved from Initialization_Files/JTAG to Initialization_Files/Host
#
# Revision 1.4  2004/07/09 09:00:59  vcambrea
# changed default value for RCS0 in PICR1 - flash located on processor bus (MTWX7474)
#
# Revision 1.3  2004/05/26 13:04:11  C-vcambrea
# unified SandPoint PMCs support (Altimus X2/X3, Valis X2, Unity X4)
# 
########################################

;------------------------------------------------------------------
; Note that all registers are indirectly addressed through 
; 0xFEC0_0000, and data is written through 0xFEE0_0000.  Note also
; that the MPC107 is little-endian, but the 'writemem' instruction
; is big-endian, so that all data had to be byte-swapped manually.
;------------------------------------------------------------------

stop
sleep 0x200
reset 1

; ----- MPC107 is the PCI bus master (PCICR) ----------------------
writemem.l	0xFEC00000	0x04000080	 
writemem.b	0xFEE00000	0x06	 	; Bus master, memory space

; ----- 8 Memory Banks (64MB each) ---------------------------------
writemem.l	0xFEC00000	0x80000080	; mem_starting_address_1
writemem.l	0xFEE00000	0x004080c0	 
writemem.l	0xFEC00000	0x84000080	; mem_starting_address_2
writemem.l	0xFEE00000	0x004080c0
writemem.l	0xFEC00000	0x88000080	; extended_mem_starting_address_1
writemem.l	0xFEE00000	0x00000000
writemem.l	0xFEC00000	0x8c000080	; extended_mem_starting_address_2
writemem.l	0xFEE00000	0x01010101
writemem.l	0xFEC00000	0x90000080	; mem_ending_address_1
writemem.l	0xFEE00000	0x3f7fbfff
writemem.l	0xFEC00000	0x98000080	; extended_mem_ending_address_1
writemem.l	0xFEE00000	0x00000000
writemem.l	0xFEC00000	0x94000080	; mem_ending_address_2
writemem.l	0xFEE00000	0x3f7fbfff
writemem.l	0xFEC00000	0x9c000080	; extended_mem_ending_address_2
writemem.l	0xFEE00000	0x01010101

; ----- Enable Bank 0 and Bank 1, Disable page mode ---------------
writemem.l	0xFEC00000	0xa0000080	; mem_bank_enable, page_mode
writemem.b	0xFEE00000	0x03

; ----- map B, flash write, processor parked on the data bus ------
writemem.l	0xFEC00000	0xa8000080 	; picr_1
writemem.l	0xFEE00000	0x981a14ff

; ----- ROM/Flash remapping enabled -------------------------------
writemem.l	0xFEC00000	0xac000080	; picr_2
writemem.l	0xFEE00000	0x00000004

; ----- Embedded Utilities Base Address Register -----------------
writemem.l	0xFEC00000	0x78000080	;select EUMBBAR
writemem.l	0xFEE00000	0x000000FC	;Embedded utility memory block at 0xFC000000

; ----- Clear ECC Single-Bit Error Counter ------------------------
writemem.l	0xFEC00000	0xb8000080	; ecc_single_bit_error_ctr
writemem.b	0xFEE00000	0x00

; ----- taken from DINK startup -----------------------------------
writemem.l	0xFEC00000	0xf4000080	; mccr2
writemem.l	0xFEE00000	0xcc044004
writemem.l	0xFEC00000	0xf8000080	; mccr3
writemem.l	0xFEE00000	0x00004078
writemem.l	0xFEC00000	0xfc000080	; mccr4
writemem.l	0xFEE00000	0x39323235

; ----- Enable memory, 8-bit data path for ROM back 0, enable refresh
; ----- during sleep, RAM type = SDRAM, 11 or 12 row bits
writemem.l	0xFEC00000	0xf0000080	; mccr1
writemem.l	0xFEE00000	0x0000e875

writemem.l	0xFEC00000	0x72000080	; PMCR2 
writemem.b	0xFEE00000	0xe0

writemem.l	0xFEC00000	0x73000080	; ODCR 
writemem.b	0xFEE00003	0xd1

writemem.l	0xFEC00000	0x74000080	; CDCR
writemem.w	0xFEE00002	0x00fd	

writemem.l	0xFEC00000	0x76000080	; MDCR
writemem.b	0xFEE00002	0x40

writemem.l	0xFEC00000	0xa3000080	; PGMAX
writemem.b	0xFEE00003	0x32
	


; ----- disable the write protect to the Sandpoint motherboard flash
writemem.l	0xFEC00000	0x4c580080	; winbond chip-select control 
writemem.l	0xFEE00000	0x00130600      ; register

writereg MSR 0x1002 ;machine check exceptions enable

;valid opcode at program exception
writemem.l	0x700	0x48000000

;breakpoint at 0x700 - necessary for flash programmer
writereg IABR	0x702

; prevent stack walk
writereg SP 0xF
