
writereg	MBAR	0xFF400000

#################################
# Local Bus Local Access Windows
#################################

# WINDOW 1 - FLASH
writemem.l 0xff400028 0xFE000000 # LBLAWBAR1  - begining at 0xff000000
writemem.l 0xff40002C 0x80000018 # LBLAWAR1   - enable, size = 32MB 

# WINDOW 2 - board BCSRs
writemem.l 0xff400030 0xf8000000 # LBLAWBAR2  - begining at 0xf8000000
writemem.l 0xff400034 0x8000000e # LBLAWAR2   - enable, size = 32KB 

# Uncomment to use on-board SDRAM (if available)
# WINDOW 3 - local bus SDRAM
#writemem.l 0xff400038 0xf0000000 # LBLAWBAR3  - begining at 0xf0000000
#writemem.l 0xff40003c 0x80000019 # LBLAWAR3   - enable, size = 64MB

#################################
# PCI Local Access Windows
#################################
# WINDOW 0
writemem.l 0xff400060 0x80000000 # PCILAWBAR0 - begining at 0x80000000
writemem.l 0xff400064 0x8000001c # PCILAWAR0  - enable, size = 512MB

# WINDOW 1
writemem.l 0xff400068 0xa0000000 # PCILAWBAR1 - begining at 0xa0000000
writemem.l 0xff40006c 0x8000001c # PCILAWAR1  - enable, size = 512MB

#################################
# DDR Local Access Windows
#################################
# WINDOW 0 - 1st DDR SODIMM
writemem.l 0xff4000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000
writemem.l 0xff4000a4 0x8000001b # DDRLAWAR0  - enable, size = 256MB


##############################################
# DDR Controller Configuration
##############################################

# DDRCDR
# hardware compensation 150ohm
# Drain queue before sleep
writemem.l 0xff400128 0x80080001

# CS2_BNDS
writemem.l 0xff402010 0x0000000f

# CS2_CONFIG
writemem.l 0xff402088 0x80440102

# TIMING_CONFIG_0
writemem.l 0xff402104 0x00220802

# TIMING_CONFIG_1
writemem.l 0xff402108 0x3835a322

# TIMING_CONFIG_2
writemem.l 0xff40210c 0x2f9048ca

# TIMING_CONFIG_3
writemem.l 0xff402100 0x00000000


# temporary disable the memory interface for reconfiguration
# DDR_SDRAM_CFG
writemem.l 0xff402110 0x43000000

# DDR_SDRAM_CFG_2
writemem.l 0xff402114 0x00401000

# DDR_SDRAM_MODE
writemem.l 0xff402118 0x07940432

# DDR_SDRAM_INTERVAL
writemem.l 0xff402124 0x03cf0080

sleep 300

# enable the DDR memory controller
# DDR_SDRAM_CFG
writemem.l 0xff402110 0xc3000000 


##############################################
# Local Bus Interface (LBIU) Configuration
##############################################

# CS0 - 16MB FLASH 
writemem.l 0xff405000 0xff001001 # BR0 base address at 0xFF000000, port size 16 bit, GPCM, valid
writemem.l 0xff405004 0xff006ff7 # OR0 16MB flash size, 15 w.s., timing relaxed

# CS1 - board BCSRs
writemem.l 0xff405008 0xf8000801 # BR1 base address at 0xF8000000, port size 8 bit, GPCM, valid
writemem.l 0xff40500c 0xffffe9f7 # OR1 32KB size, 15 w.s., timing relaxed

# Uncomment to use on-board SDRAM (if available)
# CS2 - 64MB SDRAM
#writemem.l 0xff405014 0xfc006901 # OR2 32KB size, 13 rows, 9 cols, 64MB
#writemem.l 0xff405010 0xf0001861 # BR2 base address at 0xF0000000, port size 32 bit, SDRAM, valid

# LBCR - local bus enable
writemem.l 0xff4050d0 0x00000000

# LCRR
writemem.l 0xff4050d4 0x00010002

# MRTPR - refresh timer prescaler
writemem.l 0xff405084 0x20000000 

# SICRL
writemem.l 0xff400114 0x80000000

# SICRH
writemem.l 0xff400118 0x00000002

#Enable Core in ACR
writemem.l 0xff400800 0x00000000

# Uncomment to use on-board SDRAM (if available)
# LSRT - refresh timer
#writemem.l 0xff4050a4 0x3f000000
# LSDMR - init sdram sequence
#writemem.l 0xff405094 0x0063b723 
#writemem.l 0xff405094 0x2863b723
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xff405094 0x0863b723
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xf0000000 0x000000ff 
#writemem.l 0xff405094 0x1863b723
#writemem.l 0xf00000cc 0x000000ff 
#writemem.l 0xff405094 0x4063b723

writereg MSR 0x3000 #machine check enable, exception vectors at 0x0000_0000

#workaround for write to BCSRs
writemem.l 0xE00050d4 0x00010008 #LCRR = 0x00010008

#unlock flash in BCSR1
writemem.b 0xf8000001 0x0C

#restore LCRR
writemem.l 0xE00050d4 0x00010002 #LCRR = 0x00010002

ANDMem.l    0xff400800 0x00300000 # ACR - bits 10-11 should get a value different than '00'
                                  #       when the core is operating at below x2 of the system clock
