#######################################

#FILE

# $RCSfile: 8349MDS_rev1_init_Linux.cfg,v $

# $Date: 2006/11/30 10:24:00 $

# $Revision: 1.1 $

#DESCRIPTION

#

#COPYRIGHT 

# (c) 2005 Metrowerks Corporation

# All rights reserved.

#HISTORY

# Revision 1.0 2005/08/19 daveliu 

# modified for CodeWarrior linux kernel debug without u-boot

# from 8349SYS_init.cfg revision 1.1 vcambrea
# 
########################################



# Reset and stop

reset    1



writereg	MBAR	0xFF400000



# change internal MMR base from 0xff400000 (reset value) to 0xe0000000

writemem.l 0xff400000 0xe0000000 # IMMRBAR = 0xe0000000



writereg	MBAR	0xe0000000





##############################################

# System Configuration - Local Access Windows 

##############################################



# Local Bus Local Access Windows

#################################

# WINDOW 0 - configuration space - mapped by IMMRBAR



# WINDOW 1 - FLASH

writemem.l 0xe0000028 0xfe000000 # LBLAWBAR1  - begining at 0xfe000000

writemem.l 0xe000002c 0x80000016 # LBLAWAR1   - enable, size = 8MB 



# WINDOW 2 - board BCSRs

writemem.l 0xe0000030 0xf8000000 # LBLAWBAR2  - begining at 0xf8000000

writemem.l 0xe0000034 0x8000000e # LBLAWAR2   - enable, size = 32KB 



# WINDOW 3 - local bus SDRAM

writemem.l 0xe0000038 0xf0000000 # LBLAWBAR3  - begining at 0xf0000000

writemem.l 0xe000003c 0x80000019 # LBLAWAR3   - enable, size = 64MB





# PCI Local Access Windows

#################################

# WINDOW 0

writemem.l 0xe0000060 0x80000000 # PCILAWBAR0 - begining at 0x80000000

writemem.l 0xe0000064 0x8000001c # PCILAWAR0  - enable, size = 512MB



# WINDOW 1

writemem.l 0xe0000068 0xa0000000 # PCILAWBAR1 - begining at 0xa0000000

writemem.l 0xe000006c 0x8000001c # PCILAWAR1  - enable, size = 512MB



# DDR Local Access Windows

#################################

# WINDOW 0 - 1st DDR SODIMM

writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000

writemem.l 0xe00000a4 0x8000001b # DDRLAWAR0  - enable, size = 256MB



# WINDOW 1 - 2nd DDR SODIMM

writemem.l 0xe00000a8 0x10000000 # DDRLAWBAR1 - begining at 0x10000000

writemem.l 0xe00000ac 0x8000001b # DDRLAWAR1  - enable, size = 256MB





##############################################

# DDR Controller Configuration

##############################################



# CS0_BNDS

# bit 8-15 - starting address

# bit 24-31 - ending address

writemem.l 0xe0002000 0x00100017 ; 0x10000000 - 0x17FFFFFF



# CS0_CONFIG

# bit 0 = 1 - CS_0_EN CS0 enable

# bit 21 - 23 = 0 - ROW_BITS_CS_0 13 rows

# bit 29 - 31 = 2 - COL_BITS_CS_0 9 columns

writemem.l 0xe0002080 0x80000101



# CS1_BNDS

# bit 8-15 - starting address

# bit 24-31 - ending address

writemem.l 0xe0002008 0x0018001f ; 0x18000000 - 0x1FFFFFFF



# CS1_CONFIG

# bit 0 = 1 - CS_1_EN CS1 enable

# bit 21 - 23 = 1 - ROW_BITS_CS_1 13 rows

# bit 29 - 31 = 1 - COL_BITS_CS_1 9 columns

writemem.l 0xe0002084 0x80000101



# CS2_BNDS

# bit 8-15 - starting address

# bit 24-31 - ending address

writemem.l 0xe0002010 0x00000007 ; 0x00000000 - 0x07FFFFFF



# CS2_CONFIG

# bit 0 = 1 - CS_2_EN CS2 enable

# bit 21 - 23 = 1 - ROW_BITS_CS_2 13 rows

# bit 29 - 31 = 1 - COL_BITS_CS_2 9 columns

writemem.l 0xe0002088 0x80000101



# CS3_BNDS

# bit 8-15 - starting address

# bit 24-31 - ending address

writemem.l 0xe0002018 0x0008000f  ; 0x08000000 - 0x09FFFFFF



# CS3_CONFIG

# bit 0 = 1 - CS_3_EN CS3 enable

# bit 21 - 23 = 1 - ROW_BITS_CS_3 13 rows

# bit 29 - 31 = 1 - COL_BITS_CS_3 9 columns

writemem.l 0xe000208C 0x80000101



# TIMING_CONFIG_1

# bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles

# bit 4-7 = 7 - ACTTOPRE activate to precharge interval 7 clock cycles

# bit 9-11 = 3 = ACTTORW activate to r/w interval 3 clock cycles 

# bit 13 - 15 = 3 - CASLAT CAS latency 2.5 clock cycles

# bit 16 - 19 = 3 - REFREC refresh recovery time 11 clock cycles 

# bit 21 - 23 = 3 - WRREC data to precharge interval 3 clock cycles 

# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles

# bit 29 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle

writemem.l 0xe0002108 0x37343321



# TIMING_CONFIG_2

# bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay

writemem.l 0xe000210C 0x00000800



# temporary disable the memory interface for reconfiguration

# DDR_SDRAM_CFG

# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled

# bit 1 = 1 - SREN enable self refresh during sleep

# bit 2 = 0 - ECC_EN disable ECC interrupt generation

# bit 3 = 0 - RD_EN unbuffered DIMMs

# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM

# bit 10 = 0 - DYN_PWR power management disabled

writemem.l 0xe0002110 0x42000000



# DDR_SDRAM_MODE

# bit 0 - 15 = 0x2000  - ESDMODE

# bit 16 - 31 = 0x0162 - SDMODE 

writemem.l 0xe0002118 0x20000162



# DDR_SDRAM_INTERVAL

# bit 2 - 15 = 0x45b0 - REFINT 

# bit 18 - 31 = 0x0100  - BSTOPRE auto precharge r/w commands used

writemem.l 0xe0002124 0x045b0100

# DDR_SDRAM_CLK_CNTL
writemem.l 0xE0002130 0xC2000000

# Errata workaround for DDR controller (DDR6, only for 8349 rev1.x)
writemem.l 0xE0002F00 0x202c0000


sleep 300



# enable the DDR memory controller

# DDR_SDRAM_CFG

# bit 0 = 1 - MEM_EN SDRAM interface logic enabled

writemem.l 0xe0002110 0xc2008000 




##############################################

# Local Bus Interface (LBIU) Configuration

##############################################



# CS0 - 8MB FLASH 

writemem.l 0xe0005000 0xfe001001 # BR0 base address at 0xfe000000, port size 16 bit, GPCM, valid

writemem.l 0xe0005004 0xff806ff7 # OR0 8MB flash size, 15 w.s., timing relaxed



# CS1 - board BCSRs

writemem.l 0xe0005008 0xf8000801 # BR1 base address at 0xF8000000, port size 8 bit, GPCM, valid

writemem.l 0xe000500c 0xffffe9f7 # OR1 32KB size, 15 w.s., timing relaxed



# CS2 - 64MB SDRAM

writemem.l 0xe0005010 0xf0001861 # BR2 base address at 0xF0000000, port size 32 bit, SDRAM, valid

writemem.l 0xe0005014 0xfc000901 # OR2 32KB size, 13 rows, 9 cols, 64MB



# LBCR - local bus enable

writemem.l 0xe00050d0 0x00000000



# LCRR

# bit 28 - 31 = 0x0100  - CLKDIV - system clock:memory bus clock = 4

writemem.l 0xe00050d4 0x80000004



# LSRT - refresh timer

writemem.l 0xe00050a4 0x3f000000



# MRTPR - refresh timer prescaler

writemem.l 0xe0005084 0x20000000 



# LSDMR - init sdram sequence

writemem.l 0xe0005094 0x0063b723 

writemem.l 0xe0005094 0x2863b723

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xe0005094 0x0863b723

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xf0000000 0x000000ff 

writemem.l 0xe0005094 0x1863b723

writemem.l 0xf00000cc 0x000000ff 

writemem.l 0xe0005094 0x4063b723



# Config I/O pins


ANDMem.l 0xe0000118 0x00000003 # SICRH


# Enable timebase

writemem.l 0xe0000110 0x00400000 # SPCR



# Unlock flash in BCSR1

writemem.b 0xf8000001 0x0C



# Prepare C run env

writereg MSR 0x00003002

writereg SP  0x0ffb3000
writemem.l	0x0ffb3000	0x0	; clear final
writemem.l	0x0ffb3004	0x0	; stack frame


