#setMMRBaseAddr 0xFF400000
writereg	MBAR	0xFF400000

# change internal MMR base from 0xff400000 (reset value) to 0xe0000000
writemem.l 0xff400000 0xe0000000 # IMMRBAR = 0xe0000000

#setMMRBaseAddr 0xe0000000
writereg	MBAR	0xe0000000


##############################################
# System Configuration - Local Access Windows 
##############################################

# Local Bus Local Access Windows
#################################
# WINDOW 0 - FLASH
writemem.l 0xe0000020 0xfe000000 # LBLAWBAR0  - begining at 0xfe000000 
writemem.l 0xe0000024 0x80000017 # LBLAWAR0   - enable, size = 16MB 

# WINDOW 1 - NAND Flash
writemem.l 0xe0000028 0xf8000000 # LBLAWBAR1  - begining at 0xf8000000
writemem.l 0xe000002c 0x80000018 # LBLAWAR1   - enable, size = 32MB 

# WINDOW 2 - VSC7385
writemem.l 0xe0000030 0xf0000000 # LBLAWBAR2  - begining at 0xfc100000
writemem.l 0xe0000034 0x80000010 # LBLAWAR2   - enable, size = 128kB

# WINDOW 3 - Read Write Buffer
writemem.l 0xe0000038 0xfa000000 # LBLAWBAR3  - begining at 0xfa000000
writemem.l 0xe000003c 0x8000000e # LBLAWAR3   - enable, size = 32kB

# PCI Local Access Windows
#################################
# WINDOW 0
writemem.l 0xe0000060 0x80000000 # PCILAWBAR0 - begining at 0x80000000
writemem.l 0xe0000064 0x8000001c # PCILAWAR0  - enable, size = 512MB

# WINDOW 1
writemem.l 0xe0000068 0xa0000000 # PCILAWBAR1 - begining at 0xa0000000
writemem.l 0xe000006c 0x8000001c # PCILAWAR1  - enable, size = 512MB

# DDR Local Access Windows
#################################
# WINDOW 0 - 1st DDR SODIMM
writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000
writemem.l 0xe00000a4 0x8000001a # DDRLAWAR0  - enable, size = 128MB

# WINDOW 1 - 2nd DDR SODIMM
#writemem.l 0xe00000a8 0x10000000 # DDRLAWBAR1 - begining at 0x10000000
#writemem.l 0xe00000ac 0x8000001b # DDRLAWAR1  - enable, size = 256MB

writemem.l 0xe00000e0 0x08000000 # DDRLAWBAR0 - begining at 0x08000000
writemem.l 0xe00000e4 0x8000001a # DDRLAWAR0  - enable, size = 128MB


	#*********************************
	# DDR2 Controller Registers
	#*********************************

	#DDRCDR
	writemem.l 0xE0000128 0x73000002

	# DDR_SDRAM_CLK_CNTL
	# CLK_ADJST = b'010' ; 2 Clocks
        writemem.l 0xE0002130 0x02000000

	# CS0_BNDS
	# SA0 = b'000000000000'
	# EA0 = b'000000000111'
	writemem.l 0xE0002000 0x00000007 ;# 128MB
	
	# CS0_CONFIG
	# CS_0_EN = b'1'
	# AP_0_EN = b'1'
	# ODT_RD_CFG = b'0'
	# ODT_WR_CFG = b'1'
	# BA_BITS_CS_0 = b'00'
	# ROW_BITS_CS_0 = b'001' ; 13 row bits
	# COL_BITS_CS_0 = b'010' ; 10 columns bits
	writemem.l 0xE0002080 0x80840102

	# TIMING_CFG_3
	# EXT_REFREC = b'000' ; 0 Clocks
	writemem.l 0xE0002100 0x00000000
	

	# TIMING_CONFIG_1
	# bit 1-3 = 2 - PRETOACT precharge activate interval 2 clock cycles
	# bit 4-7 = 6 - ACTTOPRE activate to precharge interval 6 clock cycles
	# bit 9-11 = 2 = ACTTORW activate to r/w interval 2 clock cycles 
	# bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles
	# bit 16 - 19 = 6 - REFREC refresh recovery time 14 clock cycles 
	# bit 21 - 23 = 2 - WRREC data to precharge interval 2 clock cycles 
	# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
	# bit 29 - 31 = 2 - WRTORD write data to read command interval 2 clock cycles
	writemem.l 0xe0002108 0x26256222

	# TIMING_CONFIG_2
	# bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay
	writemem.l 0xe000210C 0x0f9028c7


	
	# TIMING_CFG_0
	# RWT = b'00' ; 0 Clocks
	# WRT = b'00' ; 0 Clocks
	# RRT = b'00' ; 0 Clocks
	# WWT = b'00' ; 0 Clocks
	# ACT_PD_EXIT = b'010' ; 2 Clocks
	# PRE_PD_EXIT = b'010' ; 2 Clocks
	# ODT_PD_EXIT = b'1000' ; 8 Clocks
	# MRS_CYC = b'0010' ; 2 Clocks
	writemem.l 0xE0002104 0x00220802

	# DDR_SDRAM_CFG
	# MEM_EN = b'0'
	# SREN = b'1'
	# RD_EN = b'0'
	# SDRAM_TYPE = b'011'
	# DYN_PWR = b'0'
	# 32_BE = b'1'
	# 8_BE = b'0'
	# NCAP = b'0'
	# 2T_EN = b'0'
	# x32_EN = b'0'
	# PCHB8 = b'0'
	# HSE = b'0'
	# MEM_HALT = b'0'
	# BI = b'0'
	writemem.l 0xE0002110 0x43080000
	
	# DDR_SDRAM_CFG_2
	# FRC_SR = b'0'
	# DQS_CFG = b'00'
	# ODT_CFG = b'10'
	# NUM_PR = b'0001'
	# D_INIT = b'0'
	writemem.l 0xE0002114 0x00401000

	# DDR_SDRAM_MODE
	# Extended Mode Register: Outputs=0 or 1?
	# Mode Register
	writemem.l 0xE0002118 0x44400232
	
	# DDR_SDRAM_MODE_2
	# Extended Mode Register 2
	# Extended Mode Register 3
	writemem.l 0xE000211C 0x8000c000
		
	# DDR_SDRAM_INTERVAL
	# REFINT = 800 Clocks
	# BSTOPRE = 100 Clocks
	writemem.l 0xE0002124 0x03200064
	
	#delay before enable
	sleep 300
	#Enable: DDR_SDRAM_CFG
	writemem.l 0xE0002110 0xc3080000


##############################################
# Local Bus Interface (LBIU) Configuration
##############################################

# CS0 - 8MB NOR FLASH 
writemem.l 0xe0005000 0xfe001001 # BR0 base address at 0xFE000000, port size 16 bit, GPCM, valid
writemem.l 0xe0005004 0xff806ff7 # OR0 8MB flash size, 15 w.s., timing relaxed

# CS1 - NAND FLASH      10/4/2006 4:06PM
writemem.l	0xE0005008	0xF8000C21 # BR2 base address at 0xF8000000, port size 8 bit, FCM, valid
writemem.l	0xE000500c	0xFFFF93CC # OR2 32KB flash size, small page

# CS2 - VSC7385
writemem.l 0xe0005010 0xf0000801 # BR2 base address at 0xF0000000, port size 8 bit, GPCM, valid
writemem.l 0xe0005014 0xFFFE09FF # OR2 128KB

# CS3 - Read Write Buffer
writemem.l 0xe0005018 0xfa000801 # BR3 base address at 0xfa000000, port size 8 bit, GPCM, valid
writemem.l 0xe000501c 0xFFFF8FF7 # OR3 32KB

# LBCR - local bus enable
writemem.l 0xe00050d0 0x00000000

# LCRR
# bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles 
# bit 28 - 31 = 0x0010  - CLKDIV - system clock:memory bus clock = 2
writemem.l 0xe00050d4 0x00030002


writereg MSR 0x2000 # FP available, machine check disable, exception vectors at 0x0000_0000

writemem.l 0xE0000800 0x00000000 # ACR - Enable Core


writemem.l 0xfa000000 0x00000000 # write board LEDs

#
# NAND Flash settings
#
writemem.l	0xE00050E0	0x0000E000 # FMR


# MRTPR - refresh timer prescaler
writemem.l 0xe0005084 0x20000000 



writereg SP 0xf