#------------------------------------------------------------------------------------------
# MSC7115/6 ADS Initialization file, host side
#
# IMMR assumed to be at 0x0f000000 due to hw config word

# Set the IMMR so the debugger plugin knows where it is since
# the IMMR itself is a memory mapped register. This does not
# actually write anything to the target, it is simply to inform
# the debugger plugin where the IMMR is
#------------------------------------------------------------------------------------------

#setMMRBaseAddr 0x0f000000
writereg	MBAR	0x0f000000

# SYPCR: turn off watchdog timer
writemmr	SYPCR	0xffffffc3

writemmr	IMMR	0x04700000

#setMMRBaseAddr 0x04700000
writereg	MBAR	0x04700000

writemmr	SCCR	0x00000001

writemmr	RMR	    0x0001		# RMR=1: Set checkstop reset enable in the Reset Mode Register
writemmr	MPTPR	0x2800		# MPTPR: Set the Memory Periodic Timer Prescaler

# Setup the chip selects as described in "PowerQUICC II Reference Plantforms"

# CS0 is flash at 0xff800000, 32-bit port, no error checking, writable, GPCM, 60x bus, valid

writemmr	BR0		0xff801001
writemmr	OR0		0xff800054

# CS1 is board control & status registers at 0x04500000, 32-bit port, gpcm

writemmr	BR1		0x04501801
writemmr	OR1		0xffff8020

# CS3 is E1/T1 Framer at 0x04600000, 8-bit port, gpcm

writemmr	BR3		0x04600801
writemmr	OR3		0xffff8ea6

# CS5 is MPI Controller at 0x04608000, 32-bit port, gpcm

writemmr	BR5		0x04609801
writemmr	OR5		0xffff8020

# CS4 is TSI at 0x04610000, 8bit port, UPMA

writemmr	BR4		0x04610881
writemmr	OR4		0xFFFF8100

# UPMA write

writemem.l 0x04710170 0x10015418 # MAMR
writemem.l 0x04710188 0xFFFFFD00 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0FFFFC00 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0FF33C80 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0FF33C80 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0FFFFC00 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x3FFFFC05 # MDR
writemem.b  0x04610000 0x0

# UPMA read

writemem.l 0x04710170 0x10015400 # MAMR
writemem.l 0x04710188 0xFFFFFD00 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0F0CFC80 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0F0CFC80 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0F0CFC04 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0FFFFC00 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0x0FFFFD00 # MDR
writemem.b  0x04610000 0x0
writemem.l 0x04710188 0xFFFFFC01 # MDR
writemem.b  0x04610000 0x0

# UPMA exception

writemem.l 0x04710170 0x1001543C # MAMR
writemem.l 0x04710188 0xffffcc05 # MDR
writemem.b  0x04610000 0x0

# UPMA normal

writemem.l 0x04710170 0x00015400 # MAMR
writemem.b  0x04610000 0x0

# CS2 is SDRAM, 64-bit port at 0x00000000

writemmr BCR  0x00000000

# set 60x Bus assigned SDRAM Refresh Timer (PSRT)
writemmr	PSRT		0x0e

# The MSR comes up with a value of 0x40, which means the exception prefix
# is 0xfff00000.  The trap exception fails to execute properly so we can
# setup breakpoints unless MSR[IP] = 0.
writemmr	OR2		0xfc002cc0
writemmr	BR2		0x00000041

writemmr	PSRT		0x13

writemmr	MPTPR		0x2800

# precharge all banks
writemmr	PSDMR		0x834f36a3
writemmr	PSDMR		0xab4f36a3 

# perform an access
writemem.b	0x00000000	0xFF

# cbr refresh
writemmr	PSDMR		0x8b4f36a3

# perform 8 accesses
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF

#Issue Mode register write
writemmr	PSDMR		0x9b4f36a3

writemem.b	0x00000190	0x00

writemmr	PSDMR		0xc34f36a3

writemmr BCR  0x100c0000



writemmr	TESCR1	0x00004000 

writemmr	SIUMCR	0x0e600000


# PCI registers
writemem.l 	0x04710880 	0x01000000 #PCI_GCR PCI General Control Register

writemem.l 	0x047101c4 	0xff800000 #PCIMSK0
writemem.l 	0x047101ac 	0x04800001 #PCIBR0
writemem.l 	0x047101c8 	0xc0000000 #PCIMSK1
writemem.l 	0x047101b0 	0x80000001 #PCIBR1


writemmr 	PPC_ALRH 	0x30126745
writemmr 	PPC_ACR 	0x03


# The MSR comes up with a value of 0x40, which means the exception prefix
# is 0xfff00000.  The trap exception fails to execute properly so we can
# setup breakpoints unless MSR[IP] = 0.

writereg	MSR		0x00001002

