#
# Initialization file for Analogue & Micro RATTLER MPC8280 PCI board 
# MPC8280; 
# PVR = 0x80822011
#

#setMMRBaseAddr 0xF0000000
writereg	MBAR	0xF0000000

#Turn on LEDs
writemmr PDIRA 0xFFFFFFFF
writemmr PDATA 0x00000000

#Main System Clock Configuration Registers 

writemmr	SYPCR	0xFFFFFFC3 # SYPCR: turn off watchdog timer

writemmr	SCCR	0x00000000 #  Force baud rate clock divisor = 4

writemmr	RMR	0x0001	   # generate reset when core enters checkstop state.

# Setup the chip selects

# CS0 - 8MB flash
writemmr	BR0		0xFF801001
writemmr	OR0		0xFF800E76

# CS1 - 16MB DRAM
writemmr	OR1		0xFF003080
writemmr	BR1		0x00000041

# CS4 - 1MB external
writemmr	OR4		0xFFF00000
writemmr	BR4		0x80001801


writemmr	MPTPR		0x2000	# MPTPR: Set the Memory Periodic Timer Prescaler
writemmr	PSRT		0x1F	# set 60x Bus assigned SDRAM Refresh Timer (PSRT) ~ 15.6us

#SDRAM controller
writemmr	PSDMR		0xEA69A452 #Precharge all banks.
writemem.b	0x00000000	0xFF
writemmr	PSDMR		0xCA69A452 #CBR refresh.

# perform 8 accesses
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF

writemmr	PSDMR		0xDA69A452 #Mode Register write.
writemem.b	0x00000000	0xFF
writemmr	PSDMR		0xC269A452 #Normal operation.

# Registers programmed, starting up DRAM
sleep 100

writemmr 	SIUMCR	0x0E24C000 # Set SIU configuration bits

writemmr	TESCR1	 0x00004000  # 60x bus data errors disabled 
writemmr	L_TESCR1 0x00004000 

writereg 	MSR	0x3002	   # Machine Mode Register

#Turn OFF LEDs
writemmr PDATA 0xFFFFFFFF

