#reset 0		# reset & run
#sleep 0x100
#stop

# set interrupt vectors
writereg	IVPR 	0xFFFF0000 	# IVPR (compatible to the Flash) 
writereg	IVOR15	0x0000F000	# debug - (a valid instruction should exist to be fetched)
writereg	IVOR6	0x0000F700	# program

#######################################################################
# Set a breakpoint at the reset address 
writereg	IAC1		0xfffffffc
writereg	DBCR0		0x40800000
writereg	DBCR1		0x00000000
writereg	MSR			0x02000200

run
sleep 0x10
stop

writereg	DBCR0	0x41000000
writereg	IAC1	0x00000000

# 
#######################################################################

# activate debug interrupt
writereg	MSR 0x00000200

# invalidate BR0
writemem.l 0xFF705000 0x00001000 

# ABIST off
writemem.l	0xFF720E44 0x0000000C	# L2ERRDIS[MBECCDIS]=1 L2ERRDIR[SBECCDIS]=1

####################################################################################
# configure internal SRAM to cover the default 4KB MMU page: 0xFFFFF000 - 0xFFFFFFFF

# L2CTL
# bit 0 = 0 		- L2E: L2 SRAM disabled
# bit 4-5 = 01 		- L2BLKSZ: = 512KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0x00010000

# L2SRBAR0
# bit 0-17 = BASE addr: 4GB-512KB
writemem.l	0xFF720100	0x0FFF8000

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM enable
# bit 4-5 = 01 		- L2BLKSZ: = 512KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0x80010000


#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200


##################################################################################
#	
#	Memory Map - LAW(Local Access Window) configuration
#
#	0x40000000	0x400fffff	TLB1_1	CCSR	1M
#	0x00000000	0x0fffffff	TLB1_3	DDR	256M
#	0x10000000	0x1fffffff	TLB1_4	DDR	256M
#	0xff000000	0xffffffff	TLB1_5	FLASH	16M
#	0x80000000	0x8fffffff	TLB1_6	PCI0	256M
#	0x90000000	0x9fffffff	TLB1_7	PCI0	256M
#	0x20000000	0x2003ffff	TLB1_8	L2 SRAM	1M (only 512K is used for SRAM)
#


##################################################################################
# MMU initialization
#

###
# define 1MB TLB1 entry 1: 0x40000000 - 0x400FFFFF
writereg128		L2MMU_CAM1  0x500003C8 0xFC000000 0x40000000 0x40000001
#For Solaris, use the following line instead of the line above#
#writereg128	L2MMU_CAM1  0x40000001 0x40000000 0xFC000000 0x500003C8

###
# define 256MB TLB1 entry 3: 0x00000000 - 0x0FFFFFFF
# for DDR
writereg128		L2MMU_CAM3 0x90003FC0 0xFC000000 0x00000000 0x00000001 
#For Solaris, use the following line instead of the line above#
#writereg128	L2MMU_CAM3 0x00000001 0x00000000 0xFC000000 0x90003FC0 

###
# define 256MB TLB1 entry 4: 0x10000000 - 0x1FFFFFFF
# for DDR
writereg128		L2MMU_CAM4 0x90003FC0 0xFC000000 0x10000000 0x10000001
#For Solaris, use the following line instead of the line above#
#writereg128	L2MMU_CAM4 0x10000001 0x10000000 0xFC000000 0x90003FC0

###
# define 16MB TLB entry 5: 0xFF000000 - 0xFFFFFFFF
# for FLASH bank #0 and bank #1
writereg128		L2MMU_CAM5 0x70000FC8 0xFC000000 0xFF000000 0xFF000001
#For Solaris, use the following line instead of the line above#
#writereg128	L2MMU_CAM5 0xFF000001 0xFF000000 0xFC000000 0x70000FC8

###
# define 256MB TLB1 entry 6: 0x80000000 - 0x8FFFFFFF
# for PCI0
writereg128		L2MMU_CAM6 0x90003FC0 0xFC000000 0x80000000 0x80000001
#For Solaris, use the following line instead of the line above#
#writereg128	L2MMU_CAM6 0x80000001 0x80000000 0xFC000000 0x90003FC0

###
# define 256MB TLB1 entry 7: 0x90000000 - 0x9FFFFFFF
# for PCI0
writereg128		L2MMU_CAM7 0x90003FC0 0xFC000000 0x90000000 0x90000001
#For Solaris, use the following line instead of the line above#
#writereg128	L2MMU_CAM7 0x90000001 0x90000000 0xFC000000 0x90003FC0

###
# define 256KB TLB1 entry 8: 0x20000000 - 0x2007ffff
# for SRAM
writereg128		L2MMU_CAM8 0x500003C0 0xFC000000 0x20000000 0x20000001
#For Solaris, use the following line instead of the line above#
#writereg128	L2MMU_CAM8 0x20000001 0x20000000 0xFC000000 0x500003C0

##################################################################################
# move CCSR at 0x40000000
# 

# CCSRBAR
# bit 12 - 23 - BASE_ADDR
writemem.l	0xFF700000	0x00040000

# debugger does not need anymore to be informed about the 8560 memory-mapped register base CCSRBAR. 
# It will read CCSRBAR value through JTAG
#setMMRBaseAddr 0x40000000


##################################################################################
# config BPTR register (Boot Page Translation Register)
# remove the 4k boot page from 0xFFFFF000 address
writemem.l  0x40000020  0x00000000 

# Invalidate again BR0 to prevent flash data damage in case 
# the boot sequencer re-enables CS0 access
writemem.l 0x40005000 0x00001000 


##################################################################################
# configure internal SRAM at 0x20000000

# L2CTL
# bit 0 = 0 		- L2E: L2 SRAM disabled
# bit 4-5 = 01 		- L2BLKSZ: = 512KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0x40020000	0x00010000

# L2SRBAR0
# bit 0-17 = BASE addr: 0x20000000
writemem.l	0x40020100	0x02000000

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM enable
# bit 4-5 = 01 		- L2BLKSZ: = 512KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0x40020000	0x80010000





##################################################################################
#	
#	Memory Windows
#
#	0x00000000	0x1ffffff	LAW0	DDR
#	0xc0000000	0xfffffff	LAW1	Local Bus
#	0x80000000	0x9ffffff	LAW2	PCI0
#



##################################################################################
# configure local access windows
# 
# window 0: DDR = F
# window 1: Local Bus = 4
# Window 2: PCI0 = 0

# LAWBAR0
# bit 12 - 31 = 0x00000000 - base addr
writemem.l	0x40000c08 	0x00000000

# LAWAR0
# bit 1 = 1 - enable window
# bit 8-11 = F - DDR
# bit 26 - 31  = 512MB - size
writemem.l	0x40000c10	0x80f0001c

# LAWBAR1
# bit 12 - 31 = 0xc0000000 - base addr
writemem.l	0x40000c28 	0x000c0000

# LAWAR1
# bit 1 = 1 - enable window
# bit 8-11 = 4 - local bus
# bit 26 - 31  = 1GB - size
writemem.l	0x40000c30	0x8040001D

# LAWBAR2
# bit 12 - 31 = 0x80000000 - base addr
writemem.l	0x40000c48 	0x00080000

# LAWAR2
# bit 1 = 1 - enable window
# bit 8-11 = 0 - PCI0
# bit 26 - 31  = 512M - size
writemem.l	0x40000c50	0x8000001c


####################################################################
#
# DDR initalization
#

###  Clocks: CPU: 990 MHz, CCB: 396 MHz, DDR: 198 MHz

# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l	0x40002110 0x42000000

# configure the appropriate DDR controller registers

# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002000 0x0000000f ; DDR CS0

# CS0_CONFIG
writemem.l 0x40002080 0x80010102

# CS1_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002008 0x0010001f ; DDR CS1

# CS1_CONFIG
writemem.l 0x40002084 0x80010102

# TIMING_CFG_0
writemem.l	0x40002104 0x00260802

# TIMING_CFG_1
writemem.l	0x40002108 0x39397322

# TIMING_CFG_2
writemem.l	0x4000210C 0x04a04cc8

# DDR_SDRAM_MODE
writemem.l	0x40002118 0x00400452

# DDR_SDRAM_INTERVAL
writemem.l	0x40002124 0x06090100

# DDR_SDRAM_CFG2
writemem.l	0x40002114 0x04400000

# DDR_SDRAM_CLK_CNTL
writemem.l	0x40002130 0x03800000

sleep 200

# enable the memory interface
# DDR_SDRAM_CFG
# enable the memory interface
writemem.l	0x40002110 0xc3008000



##################################################################################
# configure local bus memory controller 

# CS0 - Flash Bank #0
writemem.l 0x40005000 0xFF801001 # BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid
writemem.l 0x40005004 0xFF806E65 # OR0 8MB flash size

# CS1 - Flash Bank #1
writemem.l 0x40005008 0xFF001001 # BR1 base address at 0xFF000000, port size 16 bit, GPCM, valid
writemem.l 0x4000500C 0xFF806E61 # OR1 8MB flash size

# CS2 - Local SDRAM
#writemem.l 0x40005014 0xfc006901 # OR2
#writemem.l 0x40005010 0xc0001861 # BR2
writemem.l 0x400050d4 0x80000008 # LCRR	

# CS3 - CADMUS
writemem.l 0x40005018 0xFD000801 # BR3 base address at 0xFD000000
writemem.l 0x4000501C 0xFF000FF7 # OR3 16MB 


####################################################################
# interrupt vectors initialization

###
# interrupt vectors in DDR
#
writereg	IVPR 0x00000000 	# IVPR (default reset value) 

# interrupt vector offset registers 
writespr	400 0x00000100	# IVOR0 - critical input
writespr	401 0x00000200	# IVOR1 - machine check
writespr	402 0x00000300	# IVOR2 - data storage
writespr	403 0x00000400	# IVOR3 - instruction storage
writespr	404 0x00000500	# IVOR4 - external input
writespr	405 0x00000600	# IVOR5 - alignment
writespr	406 0x00000700	# IVOR6 - program
writespr	408 0x00000c00	# IVOR8 - system call
writespr	410 0x00000900	# IVOR10 - decrementer
writespr	411 0x00000f00	# IVOR11 - fixed-interval timer interrupt
writespr	412 0x00000b00	# IVOR12 - watchdog timer interrupt
writespr	413 0x00001100	# IVOR13 - data TLB errror
writespr	414 0x00001000	# IVOR14 - instruction TLB error
writespr	415 0x00001500	# IVOR15 - debug
writespr	528 0x00001600	# IVOR32 - SPE-APU unavailable
writespr	529 0x00001700	# IVOR33 - SPE-floating point data exception
writespr	530 0x00001800	# IVOR34 - SPE-floating point round exception
writespr	531 0x00001900	# IVOR35 - performance monitor

# put a valid opcode at debug and progrm exception vector address
writemem.l 0x00000700 0x48000000
writemem.l 0x00001500 0x48000000

#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200

############
#
# time base enable
writespr	1008	0x00004000	# HID0

######
#
# CW debugger settings
#

#Trap debug event enable
writereg	DBCR0		0x41000000

#  set the PC at the reset address (for debug-->connect)
writereg	PC	0xfffffffc
# for debugging starting at program entry point when stack is not initialized
writereg	SP	0x0000000F

