#######################################
#FILE
#	$RCSfile: 8555CDS_init_ROM.cfg,v $
#	$Date: 2006/09/22 14:30:18 $
#	$Revision: 1.7 $
#DESCRIPTION
#   Initialization file for debugging in ROM
#   on 8555CDS board
#
#COPYRIGHT	
#	(c) 2003 Freescale Semiconductor
#	All rights reserved.
#HISTORY
#   $Log: 8555CDS_init_ROM.cfg,v $
#   Revision 1.7  2006/09/22 14:30:18  vcambrea
#   clear debug event status after all breakpoint hits
#
#   Revision 1.6  2005/11/14 13:36:34  adrpopa1
#   Remove comments containing "workaround" word.
#
#   Revision 1.5  2005/10/11 08:30:49  vcambrea
#   updated with the DDR_SDRAM_CLK_CNTL initialization value
#
#   Revision 1.4  2005/07/21 12:06:12  milies
#   revert changes for the new DDR DIMM (boards will be shipped in the initial configuration)
#
#   Revision 1.2  2005/02/09 08:14:44  milies
#   Set TRLX bit in OR0 for flash operation
#   to fix the known issue of CDS 1.1a new batch boards
#
#   Revision 1.1  2004/11/15 14:13:04  c-dnegrea
#   files moved from Initialization_Files/JTAG to Initialization_Files/PQ3
#
#   Revision 1.4  2004/07/01 14:41:36  tmadan
#   commented out setMMRBaseAddr command (it is obsolete)
#
#   Revision 1.3  2004/05/10 08:54:14  milies
#   updated DDR initialization
#
#   Revision 1.2  2004/04/02 21:55:55  milies
#   initialization for 8555CDS
#
#   Revision 1.1  2004/02/27 12:55:03  milies
#   8555CDS init files, just for the wizard;
#   nothing specific for the CDS board; it's only a copy-paste from 8560ADS files
#
########################################

# debugger does not need anymore to be informed about the 8560 memory-mapped register base CCSRBAR. 
# It will read CCSRBAR value through JTAG
#setMMRBaseAddr 0xFF700000		# CCSR default

writemem.l 0xFF705000 0x00001000 # invalidate BR0

##################################################################################
# in case of booting with boot sequencer, un-comment the following two commands:
#
# config BPTR register (Boot Page Translation Register)
# disable boot page (if enabled by boot sequencer)
#writemem.l  0xFF700020  0x00000000 
# move CCSRBAR at the reset address
#writemem.l 0x40000000  0xFF700000  # if boot seq uses another address for moving 
                                    #  CCSRBAR, replace 0x40000000 with the right address

##################################################################################
# configure internal SRAM at highest memory address to cover the default MMU page

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM disabled
# bit 4-5 = 01 		- L2BLKSZ: = 128KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0x64010000

# L2SRBAR0
# bit 0-17 = 0xFFFE0000 - BASE addr: 4GB-128KB
writemem.l	0xFF720100	0xFFFE0000

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM enable
# bit 4-5 = 01 		- L2BLKSZ: = 128KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0xA4010000

#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200


#######################################################################
#

# set IVOR15 (debug) interrupt vectors in SRAM at 0xFFFFF000
writereg	IVPR 	0xFFFF0000 	# IVPR (default reset value) 
writereg	IVOR15	0x0000F000	# IVOR15 - debug

# write at the reset address a branch to 0xFFFFF000
writemem.l  0xfffffffc  0x4BFFF004  # branch to 0xfffff000

# set hardware breakpoint at 0xFFFFF000 address
writereg	DBCR0		0x41800000
writereg	IAC1		0xFFFFF000
writemem.l	0xFFFFF000	0x60000000	# nop (or any valid opcode)

run
sleep 0x10
stop

writereg	DBSR	0xA0800000		#clear DBSR
writereg	DBCR0	0x41000000
writereg	IAC1	0x00000000

#
#######################################################################


###################################################################################
# Invalidate cache
###################################################################################
writemem.l	0xFFFFF008	0x7C12FAA6	#	mfspr	r0,L1CSR0	/* invalidate d-cache */
writemem.l	0xFFFFF00C	0x60000002	#	ori	r0,r0,0x0002
writemem.l	0xFFFFF010	0x7C0004AC	#	sync		
writemem.l	0xFFFFF014	0x4C00012C	#	isync		
writemem.l	0xFFFFF018	0x7C12FBA6	#	mtspr	L1CSR0,r0
writemem.l	0xFFFFF01C	0x4C00012C	#	isync		
writemem.l	0xFFFFF020	0x7C12FAA6	#	mfspr	r0,L1CSR0	/* disable d-cache */
writemem.l	0xFFFFF024	0x3C20FFFF	#	lis	rsp,-1
writemem.l	0xFFFFF028	0x6021FFFE	#	ori	rsp,rsp,0xfffe
writemem.l	0xFFFFF02C	0x7C000838	#	and	r0,r0,rsp
writemem.l	0xFFFFF030	0x7C0004AC	#	sync		
writemem.l	0xFFFFF034	0x4C00012C	#	isync		
writemem.l	0xFFFFF038	0x7C12FBA6	#	mtspr	L1CSR0,r0
writemem.l	0xFFFFF03C	0x4C00012C	#	isync		
writemem.l	0xFFFFF040	0x7C13FAA6	#	mfspr	r0,L1CSR1	/* invalidate i-cache */
writemem.l	0xFFFFF044	0x60000002	#	ori	r0,r0,0x0002
writemem.l	0xFFFFF048	0x7C13FBA6	#	mtspr	L1CSR1,r0
writemem.l	0xFFFFF04C	0x4C00012C	#	isync		
writemem.l	0xFFFFF050	0x7C13FAA6	#	mfspr	r0,L1CSR1	/* disable i-cache */
writemem.l	0xFFFFF054	0x3C20FFFF	#	lis	rsp,-1
writemem.l	0xFFFFF058	0x6021FFFE	#	ori	rsp,rsp,0xfffe
writemem.l	0xFFFFF05C	0x7C000838	#	and	r0,r0,rsp
writemem.l	0xFFFFF060	0x7C13FBA6	#	mtspr	L1CSR1,r0
writemem.l	0xFFFFF064	0x4C00012C	#	isync		
writemem.l	0xFFFFF068	0x7C0004AC	#	sync		
writemem.l	0xFFFFF06C	0x38800055	# 	li 	r4, 0x55 	/* to confirm the running */
writemem.l	0xFFFFF070	0x48000000	# 	 			/* infinite loop */


writereg	PC	0xfffff008

run
sleep 0x10
stop


###
# define 256MB TLB1 entry 3 - DDR: 0x00000000 - 0x0FFFFFFF
writespr	624 0x10030000	# MAS0 
writespr	625 0x80000900	# MAS1 
writespr	626 0x00000000	# MAS2 
writespr	627 0x0000003f	# MAS3 

writemem.l	0xFFFFF000	0x7C0007A4	# tlbwe
writemem.l	0xFFFFF004	0x4C00012C	# isync
writemem.l	0xFFFFF008	0x7C0004AC	# msync
writemem.l	0xFFFFF00c	0x48000000	# infinite loop
# write tlb entry
writereg	PC	0xfffff000
run
stop

###
# define 256MB TLB1 entry 4 - DDR: 0x10000000 - 0x1FFFFFFF
writespr	624 0x10040000	# MAS0 
writespr	625 0x80000900	# MAS1 
writespr	626 0x10000000	# MAS2 
writespr	627 0x1000003f	# MAS3 
# write tlb entry
writereg	PC	0xfffff000
run
stop





##################################################################################
# disable internal SRAM (used for MMU initialization)

# L2CTL
# bit 0 = 0 		- L2E: L2 SRAM disable
# bit 4-5 = 01 		- L2BLKSZ: = 128KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0x20000000


##################################################################################
# configure local access windows
# 
# window 0: DDR = F

# LAWBAR0
# bit 12 - 31 = 0x0 - base addr
writemem.l	0xFF700c08 	0x00000000

# LAWAR0
# bit 1 = 1 - enable window
# bit 8-11 = F - DDR
# bit 26 - 31  = 512MB - size
writemem.l	0xFF700c10	0x80f0001c



####################################################################
#
# DDR initalization
#

# disable the memory interface with DDR_SDRAM_CFG[MEM_EN]
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l	0x40002110 0x42000000

# configure the appropriate DDR controller registers

# CS0_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002000 0x0000000F ; DDR CS0

# CS0_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 8 = 0 - AP_0_EN auto precharge for w/r enable
# bit 21 - 23 = 1 - ROW_BITS_CS_0 13 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 10 columns
writemem.l 0x40002080 0x80000102

# CS1_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0x40002008 0x0010001F ; DDR CS1

# CS1_CONFIG
# bit 0 = 1 - CS_0_EN CS0 enable
# bit 8 = 0 - AP_0_EN auto precharge for w/r enable
# bit 21 - 23 = 1 - ROW_BITS_CS_0 13 rows
# bit 29 - 31 = 2 - COL_BITS_CS_0 10 columns
writemem.l 0x40002084 0x80000102


# TIMING_CONFIG_1
# bit 1-3 = 2 - PRETOACT precharge activate interval 2 clock cycles
# bit 5-7 = 6 - ACTTOPRE activate to precharge interval 6 clock cycles
# bit 9-11 = 2 = ACTTORW activate to r/w interval 2 cloc cycles
# bit 13 - 15 = 3 - CASLAT CAS latency 3 clock cycles
# bit 16 - 19 = 1 - REFREC refresh recovery time 1 clock cycles
# bit 22 - 23 = 3 - WRREC data to precharge interval 3 clock cycles
# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
# bit 30 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle
writemem.l	0x40002108 0x26231321

# TIMING_CONFIG_2
# bit 19-21  = b010  - WR_DATA_DELAY - 4/8 clock delay
writemem.l	0x4000210C 0x00000800

# DDR_SDRAM_MODE
# bit 0 - 15 = 0x0000
# bit 16 - 31 = 0x0062 SDMODE
writemem.l	0x40002118 0x00000022	#0x00000062

# DDR_SDRAM_INTERVAL
# bit 2 - 15 = 0x0520 - REFINT 
# bit 18 - 31 = 0  - BSTOPRE auto precharge r/w commands used
writemem.l	0x40002124 0x03d00100	#0x05200000

# DDR_SDRAM_CLK_CNTL 
# bit 0 = 1 - SS_EN The address and command are sent to the DDR SDRAMs source synchronously.
# bit 5-7 = 0x3 - CLK_ADJST Applied clock is launched 3/4 of one SDRAM clock cycle after address/command
writemem.l	0x40002130 0x83000000

sleep 200

# enable the memory interface
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic is disabled
writemem.l	0x40002110 0xc2000000	#0xc2008000


##################################################################################
# configure local bus memory controller

# CS0 - Flash Bank #0
writemem.l 0xFF705000 0xFF801001 # BR0 base address at 0xFF000000, port size 16 bit, GPCM, valid
writemem.l 0xFF705004 0xFF806E65 # OR0 8MB flash size

####################################################################
# interrupt vectors initialization

###
# interrupt vectors in DDR
#
writereg	IVPR 0x00000000 	# IVPR (default reset value) 

# interrupt vector offset registers 
writespr	400 0x00000100	# IVOR0 - critical input
writespr	401 0x00000200	# IVOR1 - machine check
writespr	402 0x00000300	# IVOR2 - data storage
writespr	403 0x00000400	# IVOR3 - instruction storage
writespr	404 0x00000500	# IVOR4 - external input
writespr	405 0x00000600	# IVOR5 - alignment
writespr	406 0x00000700	# IVOR6 - program
writespr	408 0x00000c00	# IVOR8 - system call
writespr	410 0x00000900	# IVOR10 - decrementer
writespr	411 0x00000f00	# IVOR11 - fixed-interval timer interrupt
writespr	412 0x00000b00	# IVOR12 - watchdog timer interrupt
writespr	413 0x00001100	# IVOR13 - data TLB errror
writespr	414 0x00001000	# IVOR14 - instruction TLB error
writespr	415 0x00001500	# IVOR15 - debug
writespr	528 0x00001600	# IVOR32 - SPE-APU unavailable
writespr	529 0x00001700	# IVOR33 - SPE-floating point data exception
writespr	530 0x00001800	# IVOR34 - SPE-floating point round exception
writespr	531 0x00001900	# IVOR35 - performance monitor

writemem.l	0x00000100	0x48000000
writemem.l	0x00000200	0x48000000
writemem.l	0x00000300	0x48000000
writemem.l	0x00000400	0x48000000
writemem.l	0x00000500	0x48000000
writemem.l	0x00000600	0x48000000
writemem.l	0x00000700	0x48000000
writemem.l	0x00000800	0x48000000
writemem.l	0x00000900	0x48000000
writemem.l	0x00000a00	0x48000000
writemem.l	0x00000b00	0x48000000
writemem.l	0x00000c00	0x48000000
writemem.l	0x00000d00	0x48000000
writemem.l	0x00000e00	0x48000000
writemem.l	0x00000f00	0x48000000
writemem.l	0x00001000	0x48000000
writemem.l	0x00001100	0x48000000
writemem.l	0x00001200	0x48000000
writemem.l	0x00001300	0x48000000
writemem.l	0x00001400	0x48000000
writemem.l	0x00001500	0x48000000
writemem.l	0x00001600	0x48000000
writemem.l	0x00001700	0x48000000
writemem.l	0x00001800	0x48000000
writemem.l	0x00001900	0x48000000



#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200


############
#
# time base enable
writespr	1008	0x00004000	# HID0

######
#
# CW debugger settings
#

# Trap debug event enable
writereg	DBCR0		0x41000000

# Clear debug event status
writereg	DBSR		0x01CF0000

#  set the PC at the reset address (for debug-->connect)
writereg	PC	0xfffffffc
# for debugging starting at program entry point when stack is not initialized
writereg	SP	0x0000000F

