;----------------------------------------------------------------------
; ROM Initialization Code for 5200 Icecube board
; Author: Alecsandru Soare, alsoare1@motorola.com
; Last Change: Wed June 09 15:04:00 2003
;----------------------------------------------------------------------

; After reset the beginning of the internal memory map is expected to be at 0x80000000
; For ROM debugging the internal memory map will remain at 0x80000000 in init file but
; it will be relocated to 0xF0000000 in 5200_IceCube_init.c file.

writereg	MSR 0x00003002 ; MSR

;writemmr	MM_MBAR 0x0000f000 ; MBAR memory mapped register
;writemem.l 0x80000000 0x0000f000 ; MBAR memory mapped register

writereg	MBAR 0x80000000 ; SPR_MBAR special purpose register: save internal memory offset

; memory controller initialization

;  FLASH

writemmr	CS0STR		0x0000FF00	;CS0 start = 0xff000000
writemmr	CS0STP		0x0000FFFF	;CS0 stop  = 0xffffffff
writemmr	CSBOOTCR	0x00043800	;BOOT ctrl, Boot Device (FLASH) is R/W
writemmr	IPBICR		0x00010001	;CSE: enable CS0, disable CSBOOT

;  SDRAM 32MB (2 x MT48LC8M16A2 SDRAM chips)
writemmr    SDRAMCS0 0x00000018 ;SDRAM CS0, 32MB @ 0x00000000
writemmr    SDRAMCS1 0x02000000 ;SDRAM CS1, disabled @ 0x02000000

;  SDRAM 64MB (2 x MT48LC16M16A2 SDRAM chips)
;writemmr    SDRAMCS0 0x00000019 ;SDRAM CS0, 64MB @ 0x00000000
;writemmr    SDRAMCS1 0x04000000 ;SDRAM CS1, disabled @ 0x04000000

writemmr    PORT_CONFIG 0x80000000 ;GPIO Enable CS1

writemmr    CONFIG1 0xC2222600 ;SDRAM Config 1
writemmr    CONFIG2 0x88B70004 ;SDRAM Config 2
writemmr    SDRAMCTRL 0xD0470000 ;SDRAM Control
writemmr    SDRAMCTRL 0xD0470002 ;SDRAM Control: precharge all
writemmr    SDRAMMODE 0x048D0000 ;SDRAM Mode
writemmr    SDRAMCTRL 0xD0470002 ;SDRAM Control: precharge all
writemmr    SDRAMCTRL 0xD0470004 ;SDRAM Control: refresh
writemmr    SDRAMMODE 0x008D0000 ;SDRAM Mode
writemmr    SDRAMCTRL 0x50470000 ;SDRAM Control


;writemem.l	0x80000004	0x0000FF80	;CS0 start = 0xff800000
;writemem.l	0x80000008	0x0000FFFF	;CS0 stop  = 0xffffffff
;writemem.l	0x80000300	0x00043801	;BOOT ctrl, Boot Device (FLASH) is RO
;writemem.l	0x80000300	0x00043800	;BOOT ctrl, Boot Device (FLASH) is R/W
;writemem.l	0x80000054	0x00010001	;CSE: enable CS0, disable CSBOOT


;  SDRAM 32MB (2 x MT48LC8M16A2 SDRAM chips)
;writemem.l    0x80000034 0x00000018 ;SDRAM CS0, 32MB @ 0x00000000
;writemem.l    0x80000038 0x02000000 ;SDRAM CS1, disabled @ 0x02000000

;  SDRAM 64MB (2 x MT48LC16M16A2 SDRAM chips)
;writemem.l    0x80000034 0x00000019 ;SDRAM CS0, 64MB @ 0x00000000
;writemem.l    0x80000038 0x04000000 ;SDRAM CS1, disabled @ 0x04000000

;writemem.l    0x80000B00 0x80000000 ;GPIO Enable CS1

;writemem.l    0x80000108 0xC2222600 ;SDRAM Config 1
;writemem.l    0x8000010C 0x88B70004 ;SDRAM Config 2
;writemem.l    0x80000104 0xD0470000 ;SDRAM Control
;writemem.l    0x80000104 0xD0470002 ;SDRAM Control: precharge all
;writemem.l    0x80000100 0x048D0000 ;SDRAM Mode
;writemem.l    0x80000104 0xD0470002 ;SDRAM Control: precharge all
;writemem.l    0x80000104 0xD0470004 ;SDRAM Control: refresh
;writemem.l    0x80000100 0x008D0000 ;SDRAM Mode
;writemem.l    0x80000104 0x50470000 ;SDRAM Control

