#########################################################################
# Initialization file for                                               #
# PQIII-8560ADS board with rev.2 silicon                                #
# Modified by York Sun and Steve Moore                                  #
#########################################################################

#########################################################################
# Edited by York Sun on Sep 15, 2003                                    #
# Changed since last:                                                   #
# 1) Support debug code in Flash                                        #
#                                                                       #
# Contact                                                               #
# York Sun                                                              #
# Embedded System Development Lab, Freescale Semiconductor              #
#########################################################################
#########################################################################
# Edited by Steve Moore on May 12, 2004                                 #
# Changed since last:                                                   #
# 1) Support rev. 2 silicon                                             #
#                                                                       #
# Contact                                                               #
# Steve Moore                                                           #
# Embedded System Development Lab, Freescale Semiconductor				#
#########################################################################


#writereg	CSRR0	0
#writereg	CSRR1	0
#writereg	SRR0	0
#writereg	SRR1	0
# reset 1

# sleep 0x100

# debugger does not need anymore to be informed about the 8560 memory-mapped register base CCSRBAR. 
# It will read CCSRBAR value through JTAG
#setMMRBaseAddr 0xFF700000		# CCSR default

####################################################################
# interrupt vectors initialization

###
# interrupt vectors in SDRAM
#
writereg	IVPR 0xFFFF0000	# IVPR (compatible to the Flash) 

# interrupt vector offset registers 
writespr	415 0x0000F000	# IVOR15 - debug (a valid instruction should exist to be fetched)

##################################################################################
########## smoore: This is needed in order to use L2 SRAM reliably, which
########## is needed for the PQ3 rev 2.0.1.
# ABIST off
writemem.l	0xFF720E44	0x0000000C	# L2ERRDIS[MBECCDIS]=1, L2ERRDIR[SBECCDIS]=1


##################################################################################
########## smoore: This is needed by the PQ3 rev 2.0.1 below
# configure internal SRAM at highest memory address to cover the default MMU page

# L2CTL
# bit 0 = 1 		- L2E: L2 SRAM enable
# bit 4-5 = 10 		- L2BLKSZ: = 256KB
# bit 13-15 = 001 	- L2SRAM: Block 0 = SRAM 0
writemem.l	0xFF720000	0x28010000	#disable L2 SRAM

# L2SRBAR0
# bit 0-17 = 0xFFFC0000 - BASE addr: 4GB-256KB
writemem.l	0xFF720100	0xFFFC0000

writemem.l	0xFF720000	0xA8010000	#enable L2 SRAM

#############
#
# activate debug interrupt and enable SPU
writereg	MSR 0x02000200



#######################################################################
#

# set IVOR15 (debug) interrupt vectors in SRAM at 0xFFFFF000
writereg	IVPR 	0xFFFF0000 	# IVPR (default reset value) 
writereg	IVOR15 	0x0000F000	# IVOR15 - debug


# write at the reset address a branch to 0xFFFFF000
writemem.l  0xfffffffc  0x4BFFF004  # branch to 0xfffff000

# set hardware breakpoint at 0xFFFFF000 address
writereg	DBCR0		0x41800000
#writereg	DBCR1		0x00000000
writereg	IAC1		0xFFFFF000
#writereg	IAC2		0x00000000
writemem.l	0xFFFFF000	0x60000000	# nop (or any valid opcode)

run
sleep 0x10
stop

writereg	DBCR0	0x41000000
writereg	IAC1	0x00000000

# Clear debug event status
writereg	DBSR		0x01CF0000

#
#######################################################################





#######################################################################
########## smoore: cleanup after the PQ3 rev 2.0.1 above
#  set the PC back to the reset address (for debug-->connect)
writereg	PC	0xfffffffc
# re-activate debug interrupt and enable SPU (hitting the HW bp altered it)
writereg	MSR 0x02000200
# clear CSRR0 & CSRR1 to erase the effects of the HW breakpoint - enables
# stepping through 0xfffff000 and 0xfffff004.
writereg	CSRR0	0
writereg	CSRR1	0
#writereg	SRR0	0
#writereg	SRR1	0
# disable the internal SRAM now that we're done with it
writemem.l	0xff720000	0x28010000	#disable L2 SRAM


