#######################################
#FILE
#	$RCSfile: e500_init_dbg.cfg,v $
#	$Date: 2006/10/03 15:15:24 $
#	$Revision: 1.3 $
#DESCRIPTION
#   Initialization file for
#   e500 ISS
#COPYRIGHT	
#	(c) 2003 Metrowerks Corporation
#	All rights reserved.
#HISTORY
#   $Log: e500_init_dbg.cfg,v $
#   Revision 1.3  2006/10/03 15:15:24  vcambrea
#   revert previous commit - workaround for simulator (DBSR bits do not function as "write 1 to clear" bits)
#
#   Revision 1.2  2006/09/22 14:30:28  vcambrea
#   clear debug event status after all breakpoint hits
#
#   Revision 1.1  2004/11/15 14:13:11  c-dnegrea
#   files moved from Initialization_Files/JTAG to Initialization_Files/PQ3
#
#   Revision 1.7  2004/07/01 14:41:39  tmadan
#   commented out setMMRBaseAddr command (it is obsolete)
#
#   Revision 1.6  2004/06/30 16:13:45  tmadan
#   add file header
#
#   
########################################

# debugger does not need anymore to be informed about the 8560 memory-mapped register base CCSRBAR. 
# It will read CCSRBAR value through JTAG
#setMMRBaseAddr 0xFF700000		# CCSRBAR default value
# activate debug interrupt
writereg	MSR 0x00000200

#
# init interrrupt vectors
#

# interrupt vector prefix register
writereg	IVPR 0x00000000 	# IVPR (default reset value) 
#writespr	63 0x00000000 	# IVPR (default reset value) 

# interrupt vector offset registers 
writespr	400 0x00000A00	# IVOR0 - critical input
writespr	401 0x00000200	# IVOR1 - machine check
writespr	402 0x00000300	# IVOR2 - data storage
writespr	403 0x00000400	# IVOR3 - instruction storage
writespr	404 0x00000500	# IVOR4 - external input
writespr	405 0x00000600	# IVOR5 - alignment
writespr	406 0x00000700	# IVOR6 - program
writespr	408 0x00000c00	# IVOR8 - system call
writespr	410 0x00000900	# IVOR10 - decrementer
writespr	411 0x00000f00	# IVOR11 - fixed-interval timer interrupt
writespr	412 0x00000b00	# IVOR12 - watchdog timer interrupt
writespr	413 0x00001100	# IVOR13 - data TLB errror
writespr	414 0x00001000	# IVOR14 - instruction TLB error
writespr	415 0x00001500	# IVOR15 - debug
writespr	528 0x00001600	# IVOR32 - SPE-APU unavailable
writespr	529 0x00001700	# IVOR33 - SPE-floating point data exception
writespr	530 0x00001800	# IVOR34 - SPE-floating point round exception
writespr	531 0x00001900	# IVOR35 - performance monitor

#
# MMU init
#

# MMU read/write and replacement control
# writespr	624 0x10010000	# MAS0 
# descriptor context and configuration control
# writespr	625 0xc0000900	# MAS1 
# EPN and page attributes
# writespr	626 0x00000080	# MAS2 
# RPN and access control
# writespr	627 0x0000003f	# MAS3 
# Hardware replacement assist configuration
# writespr	628 0x00000000	# MAS4


# Assembly code used to generate the instructions in the memory writes below
#            /* -------- */
#            /* init MMU */
#            /* -------- */
#            /* MAS0 - MMU read/write and replacement control */
#            lis                     r10, 0x1001
#            ori                    r10, r10, 0x0000
#            mtspr    624, r10
#            /* MAS1 - descriptor context and configuration control */
#            lis                     r11, 0xC000
#            ori                    r11, r11, 0x0900
#            mtspr    625, r11
#            /* MAS2 - EPN and page attributes */
#            lis                     r12, 0x0000
#            ori                    r12, r12, 0x0000
#            mtspr    626, r12
#            /* MAS3 - RPN and access control */
#            lis                     r13, 0x0000
#            ori                    r13, r13, 0x003f
#            mtspr    627, r13
#            /* TLB entry # */
#            li                       r1, 0
#            /* incrementor for ESEL */
#            lis                     r2, 0x0001
#            /* incrementor for EPN/RPN */
#            lis                     r3, 0x1000
#tlb_loop:
#            /* Write TLB entry */
#            tlbwe
#            /* If this is the last entry, break out of the loop. */
#            cmpwi   cr0, r1, 0xf
#            beq                   tlb_end
#            /* increment entry # */
#            addi      r1, r1, 1
#            /* increment ESEL in MAS0 (4 bits << 16) */
#            add                   r10, r10, r2
#            mtspr    624, r10
#            /* increment EPN in MAS2 (20 bits << 12) */
#            add                   r12, r12, r3
#            mtspr    626, r12
#            /* increment RPN in MAS3 (20 bits << 12) */
#            add                   r13, r13, r3
#            mtspr    627, r13
#            /* rinse, lather, repeat */
#            b                      tlb_loop
#tlb_end:
#            msync

# the following memory writes are writing the instructions generated
# by the above assembly code for the purposes of initializing memory
# on PQIII.
 
writemem.l	0xfffff000	0x3D401001
writemem.l	0xfffff004	0x614A0000
writemem.l	0xfffff008	0x7D509BA6
writemem.l	0xfffff00c	0x3D60C000
writemem.l	0xfffff010	0x616B0900
writemem.l	0xfffff014	0x7D719BA6
writemem.l	0xfffff018	0x3D800000
writemem.l	0xfffff01c	0x618C0000
writemem.l	0xfffff020	0x7D929BA6
writemem.l	0xfffff024	0x3DA00000
writemem.l	0xfffff028	0x61AD003F
writemem.l	0xfffff02c	0x7DB39BA6
writemem.l	0xfffff030	0x38200000
writemem.l	0xfffff034	0x3C400001
writemem.l	0xfffff038	0x3C601000

writemem.l	0xfffff03c	0x7C0007A4
writemem.l	0xfffff040	0x2C01000F
writemem.l	0xfffff044	0x41820024
writemem.l	0xfffff048	0x38210001
writemem.l	0xfffff04c	0x7D4A1214
writemem.l	0xfffff050	0x7D509BA6
writemem.l	0xfffff054	0x7D8C1A14
writemem.l	0xfffff058	0x7D929BA6
writemem.l	0xfffff05c	0x7DAD1A14
writemem.l	0xfffff060	0x7DB39BA6
writemem.l	0xfffff064	0x4BFFFFD8
writemem.l	0xfffff068	0x7C0004AC
writemem.l	0xfffff06c	0x00000000	# stop at the end

writereg PC	0xfffff000

run

sleep 0x100
stop

writemem.l	0xfffff06c	0xffffffff	# tell the simulator that this isn't a breakpoint anymore

#
# The following additional memory init code is needed on the 8540
#

# Map all of 4GB of memory into ecm windows, the register space will have higher priority.
# Also, map one DDR dimm to the 4GB of memory space too.
#
# Set the LAWBAR0 to make an address window start at addr 0
writemem.l	0xff700c08 	0x00000000
# Set the LAWSR0 to make an address window of 2GB
writemem.l	0xff700c10	0x80f0001e
# Set the LAWBAR1 to make an address window start at addr 2GB
writemem.l	0xff700c28	0x00080000
# Set the LAWSR1 to make an address window of 2GB
writemem.l	0xff700c30	0x80f0001e

# Set the DDR memory bank sizes to 1GB (top 8 bits of address)
writemem.l	0xff702000	0x0000003f
# Set the CS1_BNDS
writemem.l	0xff702008	0x0040007f
# Set the CS2_BNDS
writemem.l	0xff702010	0x008000bf
# Set the CS3_BNDS
writemem.l	0xff702018	0x00c000ff

# Enable the DDR memory banks
# Set the CS0_CONFIG
writemem.l	0xff702080	0x80000203
# Set the CS1_CONFIG
writemem.l	0xff702084	0x80000203
# Set the CS2_CONFIG
writemem.l	0xff702088	0x80000203
# Set the CS3_CONFIG
writemem.l	0xff70208c	0x80000203


#Trap debug event enable
writereg	DBCR0		0x41000000

