#
# Initialization file for
# the Motorola ADS target
#
# IMMR assumed to be at 0x0f000000 due to hw config word

# Set the IMMR so the debugger plugin knows where it is since
# the IMMR itself is a memory mapped register. This does not
# actually write anything to the target, it is simply to inform
# the debugger plugin where the IMMR is

#for MPC826x
#setMMRBaseAddr 0x0f000000
writereg	MBAR	0x0f000000

# SYPCR: turn off watchdog timer
writemmr	SYPCR		0xffffffc3

writemmr	IMMR	0x04700000

#for MPC826x
#setMMRBaseAddr 0x04700000
writereg	MBAR	0x04700000

writemmr	SCCR	0x00000000

writemmr	RMR			0x0001		# RMR=1: Set checkstop reset enable in the Reset Mode Register
writemmr	MPTPR		0x3200		# MPTPR: Set the Memory Periodic Timer Prescaler

# Setup the chip selects as described in "PowerQUICC II Reference Plantforms"

# CS0 is flash at 0xff800000, 32-bit port, no error checking, writable, GPCM, 60x bus, valid

writemmr	BR0		0xff801801
writemmr	OR0		0xff800836


# CS1 is board control & status registers at 0x04500000 

writemmr	BR1		0x04501801
writemmr	OR1		0xffff8010


# CS2 is SDRAM, 64-bit port at 0x00000000

writemmr	OR2		0xfe002ec0
writemmr	BR2		0x00000041

writemmr	PSRT		0x13

writemmr	MPTPR		0x2800

# precharge all banks
writemmr	PSDMR		0x824b36a3
writemmr	PSDMR		0xaa4b36a3 

# perform an access
writemem.b	0x00000000	0x00

# cbr refresh
writemmr	PSDMR		0x8a4b36a3

# perform 8 accesses
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF
writemem.b	0x00000000	0xFF

; Issue Mode register write
writemmr	PSDMR		0x9a4b36a3

writemem.b	0x00000190	0x00

writemmr	PSDMR		0xc24b36a3

writemmr	SIUMCR	0x0e200000

writemmr	TESCR1	0x00004000 
writemmr	TESCR2	0x00000000 

writemmr	L_TESCR1	0x00004000 
writemmr	L_TESCR2	0x00000000 

# Local Bus SDRAM (100MHz)
#writemmr PSRT 0x10
writemmr	OR3		0xff803280
writemmr	BR3		0xd0001861

writemmr LSRT 0x13

#writemmr SIUMCR   0x0e600000
#writemmr LSRT 0x00

#writemem.b 0x047101a0 0x00

writemmr	LSDMR	0x828737a3 #0x0086a512

# SDRAM machine init

# precharge all banks
writemmr	LSDMR		0xaa8737a3

# perform an access
writemem.b	0xd0000000	0x00

# cbr refresh
writemmr	LSDMR		0x8a8737a3

# perform 8 accesses
writemem.b	0xd0000000	0xFF
writemem.b	0xd0000000	0xFF
writemem.b	0xd0000000	0xFF
writemem.b	0xd0000000	0xFF

; Issue Mode register write
writemmr	LSDMR		0x9a8737a3

writemem.b	0xd00000cc	0x00

writemmr	LSDMR		0xc28737a3

# The MSR comes up with a value of 0x40, which means the exception prefix
# is 0xfff00000.  The trap exception fails to execute properly so we can
# setup breakpoints unless MSR[IP] = 0.

writereg	MSR		0x00003002

