; This is the reset sequence required for 7447A HPC II.
; Please disable "Reset Target on Launch" option
; in the connection preferences. Otherwise you will
; not be able to properly reset the processor&board.

stop
sleep 0x100
reset 1

setSysCtrlBase 0xC0000000

writereg	MSR	0x02003002	; MSR: set VEC,FP,ME,RI
writereg	HID0	0x84000000	; HID0: set TBEN

# DDR initialization

writemem.l 0xC0004028 0x0FE00000 # SD_D0_BAR : set base address & mask
writemem.l 0xC000402C 0x0FE00200 # SD_D1_BAR : set base address & mask
writemem.l 0xC0004000 0x00000230 # SD_CTRL : 
writemem.l 0xC0004020 0x00110021 # SD_D0_CTRL : set parameters
writemem.l 0xC0004024 0x00110020 # SD_D1_CTRL : set parameters
writemem.l 0xC0004008 0x0308336b # SD_TIMING : set timing
writemem.l 0xC000400C 0x0000061A # SD_REFRESH : set refresh interval
writemem.l 0xC0004080 0x00011102 # SD_ODT_CFG
;writemem.l 0xC00040A0 0x00000000 # SD_OCD_IA_CTRL
;writemem.l 0xC0004090 0x01010404 # SD_ODT_WRITE_PATTERN
;writemem.l 0xC0004098 0x01010404 # SD_ODT_READ_PATTERN

sleep 1000 # delay

writemem.l 0xC0004000 0x80000230 # SD_CTRL : enable

writemem.l 0xC0003800 0x00000201 # PB_BAR1_LOWER_LUT_ADDR0
writemem.l 0xC0003804 0x00000000 # PB_BAR1_UPPER_LUT_ADDR0
writemem.l 0xC0003808 0x00000201 # PB_BAR1_LOWER_LUT_ADDR1
writemem.l 0xC000380C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR1	
writemem.l 0xC0003810 0x00000201 # PB_BAR1_LOWER_LUT_ADDR2
writemem.l 0xC0003814 0x00000000 # PB_BAR1_UPPER_LUT_ADDR2	
writemem.l 0xC0003818 0x00000201 # PB_BAR1_LOWER_LUT_ADDR3	
writemem.l 0xC000381C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR3	
writemem.l 0xC0003820 0x00000201 # PB_BAR1_LOWER_LUT_ADDR4	
writemem.l 0xC0003824 0x00000000 # PB_BAR1_UPPER_LUT_ADDR4	
writemem.l 0xC0003828 0x00000201 # PB_BAR1_LOWER_LUT_ADDR5	
writemem.l 0xC000382C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR5	
writemem.l 0xC0003830 0x00000201 # PB_BAR1_LOWER_LUT_ADDR6	
writemem.l 0xC0003834 0x00000000 # PB_BAR1_UPPER_LUT_ADDR6	
writemem.l 0xC0003838 0x00000201 # PB_BAR1_LOWER_LUT_ADDR7	
writemem.l 0xC000383C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR7	
writemem.l 0xC0003840 0x18000004 # PB_BAR1_LOWER_LUT_ADDR8	
writemem.l 0xC0003844 0x00000000 # PB_BAR1_UPPER_LUT_ADDR8	
writemem.l 0xC0003848 0x19000004 # PB_BAR1_LOWER_LUT_ADDR9	
writemem.l 0xC000384C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR9	
writemem.l 0xC0003850 0x1A000004 # PB_BAR1_LOWER_LUT_ADDR10	
writemem.l 0xC0003854 0x00000000 # PB_BAR1_UPPER_LUT_ADDR10	
writemem.l 0xC0003858 0x1B000004 # PB_BAR1_LOWER_LUT_ADDR11	
writemem.l 0xC000385C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR11	
writemem.l 0xC0003860 0x1C000004 # PB_BAR1_LOWER_LUT_ADDR12	
writemem.l 0xC0003864 0x00000000 # PB_BAR1_UPPER_LUT_ADDR12	
writemem.l 0xC0003868 0x1D000004 # PB_BAR1_LOWER_LUT_ADDR13	
writemem.l 0xC000386C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR13	
writemem.l 0xC0003870 0x1E000004 # PB_BAR1_LOWER_LUT_ADDR14	
writemem.l 0xC0003874 0x00000000 # PB_BAR1_UPPER_LUT_ADDR14	
writemem.l 0xC0003878 0x1F000004 # PB_BAR1_LOWER_LUT_ADDR15	
writemem.l 0xC000387C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR15	
writemem.l 0xC0003880 0x00000201 # PB_BAR1_LOWER_LUT_ADDR16	
writemem.l 0xC0003884 0x00000000 # PB_BAR1_UPPER_LUT_ADDR16	
writemem.l 0xC0003888 0x00000201 # PB_BAR1_LOWER_LUT_ADDR17	
writemem.l 0xC000388C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR17	
writemem.l 0xC0003890 0x00000201 # PB_BAR1_LOWER_LUT_ADDR18	
writemem.l 0xC0003894 0x00000000 # PB_BAR1_UPPER_LUT_ADDR18	
writemem.l 0xC0003898 0x00000201 # PB_BAR1_LOWER_LUT_ADDR19	
writemem.l 0xC000389C 0x00000000 # PB_BAR1_UPPER_LUT_ADDR19	
writemem.l 0xC00038A0 0x00000201 # PB_BAR1_LOWER_LUT_ADDR20	
writemem.l 0xC00038A4 0x00000000 # PB_BAR1_UPPER_LUT_ADDR20	
writemem.l 0xC00038A8 0x00000201 # PB_BAR1_LOWER_LUT_ADDR21	
writemem.l 0xC00038AC 0x00000000 # PB_BAR1_UPPER_LUT_ADDR21	
writemem.l 0xC00038B0 0x00000201 # PB_BAR1_LOWER_LUT_ADDR22	
writemem.l 0xC00038B4 0x00000000 # PB_BAR1_UPPER_LUT_ADDR22	
writemem.l 0xC00038B8 0x00000201 # PB_BAR1_LOWER_LUT_ADDR23	
writemem.l 0xC00038BC 0x00000000 # PB_BAR1_UPPER_LUT_ADDR23	
writemem.l 0xC00038C0 0x00000201 # PB_BAR1_LOWER_LUT_ADDR24	
writemem.l 0xC00038C4 0x00000000 # PB_BAR1_UPPER_LUT_ADDR24	
writemem.l 0xC00038C8 0x00000201 # PB_BAR1_LOWER_LUT_ADDR25	
writemem.l 0xC00038CC 0x00000000 # PB_BAR1_UPPER_LUT_ADDR25	
writemem.l 0xC00038D0 0x00000201 # PB_BAR1_LOWER_LUT_ADDR26	
writemem.l 0xC00038D4 0x00000000 # PB_BAR1_UPPER_LUT_ADDR26	
writemem.l 0xC00038D8 0x00000201 # PB_BAR1_LOWER_LUT_ADDR27	
writemem.l 0xC00038DC 0x00000000 # PB_BAR1_UPPER_LUT_ADDR27	
writemem.l 0xC00038E0 0x02000240 # PB_BAR1_LOWER_LUT_ADDR28	
writemem.l 0xC00038E4 0x00000000 # PB_BAR1_UPPER_LUT_ADDR28	
writemem.l 0xC00038E8 0x01000240 # PB_BAR1_LOWER_LUT_ADDR29	
writemem.l 0xC00038EC 0x00000000 # PB_BAR1_UPPER_LUT_ADDR29	
writemem.l 0xC00038F0 0x03000240 # PB_BAR1_LOWER_LUT_ADDR30	
writemem.l 0xC00038F4 0x00000000 # PB_BAR1_UPPER_LUT_ADDR30	
writemem.l 0xC00038F8 0x00000240 # PB_BAR1_LOWER_LUT_ADDR31	
writemem.l 0xC00038FC 0x00000000 # PB_BAR1_UPPER_LUT_ADDR31	

# Local Bus initialization
# CS0 - FLASH 16MB at 0xFF000000
writemem.l 0xC0000000 0x00000000 # HLP_B0_ADDR
writemem.l 0xC0000004 0xFFF00000 # HLP_B0_MASK
writemem.l 0xC0000008 0x7FFC44C2 # HLP_B0_CTRL0
writemem.l 0xC000000C 0x7C0F2000 # HLP_B0_CTRL1
#CS1 - System Logic
writemem.l 0xC0000010 0x00100000 # HLP_B1_ADDR
writemem.l 0xC0000014 0xFFF00000 # HLP_B1_MASK
writemem.l 0xC0000018 0x7FFC44C0 # HLP_B1_CTRL0
writemem.l 0xC000001C 0x7C0F2000 # HLP_B1_CTRL1
#CS2 - NVRAM
writemem.l 0xC0000020 0x00200000 # HLP_B2_ADDR
writemem.l 0xC0000024 0xFFF00000 # HLP_B2_MASK
writemem.l 0xC0000028 0x7FFC44C0 # HLP_B2_CTRL0
writemem.l 0xC000002C 0x7C0F2000 # HLP_B2_CTRL1
#CS3 - PromJet
writemem.l 0xC0000030 0x00300000 # HLP_B3_ADDR
writemem.l 0xC0000034 0xFFF00000 # HLP_B3_MASK
writemem.l 0xC0000038 0x7FFC44C2 # HLP_B3_CTRL0
writemem.l 0xC000003C 0x7C0F2000 # HLP_B3_CTRL1

# initialize OCN Windows
# PB_REG_BAR at 0xC0003410 is 0xC0000001 at reset
writemem.l 0xC0003414 0xE0000011 # PB_OCN_BAR1 = 
writemem.l 0xC0003418 0x80000001 # PB_OCN_BAR2 = PCI Memory
writemem.l 0xC000341C 0x00000011 # PB_SDRAM_BAR1 = DDR 1st bank
#writemem.l 0xC0003420 0x40010011 # PB_SDRAM_BAR2 = DDR 2nd bank - uncomment if used
writemem.l 0xC0003018 0x00001123 # PB_ARB_CTRL # fix for 200MHz DDR

# for flash programmer:
# eable breakpoint at program exception
writereg IABR	0x702	

# put a valid opcode at program exception
writemem.l 0x700 0x48000000