
# HPCN 8641 debugger initialization file for ROM Version target
##################################################################################

###  Clocks: CPU: 990 MHz, MPX: 396 MHz, DDR: 198 MHz, SYSCLK: 33 MHz

#  Memory Map
#  ----------
# 0x0000_0000 - 0x0fff_ffff   256M -  DDR
# 0xc000_0000 - 0xdfff_ffff   512M -  PEX1 MEM    
# 0xe000_0000 - 0xefff_ffff   256M -  PEX2 MEM
# 0xff70_0000 - 0xff7f_ffff     1M -  CCSR
# 0xf810_0000 - 0xf81f_ffff     1M -  PIXIS
# 0xf820_0000 - 0xf82f_ffff     1M -  CFlash
# 0xfc00_0000 - 0xfcff_ffff    16M -  PEX1 IO
# 0xfd00_0000 - 0xfdff_ffff    16M -  PEX2 IO
# 0xfe00_0000 - 0xfeff_ffff    16M -  FLASH (Alternate/PromJet)
# 0xff80_0000 - 0xffff_ffff     8M -  FLASH (boot)

##################################################################################

# Configure Local Access Memory windows
##################################################################

# window 0: Local bus PIXIS & CFlash
writemem.l	0xff700c08 	0x000f8100 # LAWBAR0 - base address = 0Xf8100000
writemem.l	0xff700c10	0x80400014 # LAWAR0 - local bus, PIXIS & CFlash, 2MB

# window 1: DDR controller 1
writemem.l	0xff700c28 	0x00000000 # LAWBAR1 - base address = 0X00000000
writemem.l	0xff700c30	0x80f0001b # LAWAR1 - DDR controller 1, DDR, 256MB 

# window 2: Big Serdes (PEX1/SRIO)
writemem.l	0xff700c48 	0x000c0000 # LAWBAR2 - base address = 0Xc0000000 
writemem.l	0xff700c50	0x8000001c # LAWAR2 - PEX1, 512MB

# window 3: Small Serdes (PEX2/SRIO)
writemem.l	0xff700c68 	0x000e0000 # LAWBAR3 - base address = 0Xe0000000 
writemem.l	0xff700c70	0x8010001b # LAWAR3 - PEX2, 256MB

# window 4: PCI Express interface 1 I/O
writemem.l	0xff700c88 	0x000fc000 # LAWBAR4 - base address = 0Xfc000000 
writemem.l	0xff700c90	0x80000017 # LAWAR4 - PEX1 I/0, 16MB

# window 5: PCI Express interface 2 I/O
writemem.l	0xff700ca8 	0x000fd000 # LAWBAR5 - base address = 0Xfd000000 
writemem.l	0xff700cb0	0x80100017 # LAWAR5 - PEX2 I/0, 16MB 

# window 6: Local bus Flash (boot)
writemem.l	0xff700cc8 	0x000ff800 # LAWBAR6 - base address = 0Xff800000 
writemem.l	0xff700cd0	0x80400016 # LAWAR6 - boot flash, 8MB



# DDR initalization
##################################################################

writemem.l	0xff702110 0x42000000 # DDR_SDRAM_CFG
writemem.l 	0xff702000 0x0000001f # CS0_BNDS
writemem.l 	0xff702080 0x80010202 # CS0_CONFIG
writemem.l	0xff702104 0x00260802 # TIMING_CFG_0
writemem.l	0xff702108 0x3935d322 # TIMING_CFG_1
writemem.l	0xff70210C 0x14904cc8 # TIMING_CFG_2
writemem.l	0xff702118 0x00480432 # DDR_SDRAM_MODE
writemem.l	0xff702124 0x06180100 # DDR_SDRAM_INTERVAL
writemem.l	0xff702114 0x04400000 # DDR_SDRAM_CFG2
writemem.l	0xff702130 0x03800000 # DDR_SDRAM_CLK_CNTL

sleep 200

# enable the memory interface
writemem.l	0xff702110 0xc3008000 # DDR_SDRAM_CFG


# Configure Local Bus Memory Controller 
##################################################################

# CS0 - Flash (boot)
writemem.l 0xff705000 0xFF001001 # BR0 base address at 0xFF000000, port size 16 bit, GPCM, valid
writemem.l 0xff705004 0xFF006FF7 # OR0 8MB flash size, starting at 0xFF000000 and repeated at 0xFF800000

# CS1 - Flash (Alternate/PromJet) 
writemem.l 0xff705008 0xFE001001 # BR1 base address at 0xFE000000, port size 16 bit, GPCM, valid
writemem.l 0xff70500C 0xFF006FF7 # OR1 16MB flash size

# CS2 - Compact Flash
writemem.l 0xff705010 0xF8201001 # BR2 base address at 0xF8200000
writemem.l 0xff705014 0xFFF06FF7 # OR2 1MB

# CS3 - PIXIS (FPGA board registers)
writemem.l 0xff705018 0xF8100801 # BR3 base address at 0xF8100000
writemem.l 0xff70501C 0xFFF06FF7 # OR3 1MB 


# LCRR
writemem.l 0xff7050d4 0x80000008

# LBCR
writemem.l 0xff7050d0 0x00000000


#############
#
# enable machine check exception and move interrupt handlers to 0x00000000
writereg	MSR 0x00001000

############
#
# time base enable
writespr	1008	0x04000000	# HID0


######
#
# CW debugger settings
#

# put a valid opcode at debug and progrm exception vector address
writemem.l 0x00000700 0x48000000

# enable breakpoints workaround for Flash Programmer
writespr	1010	0x702

#initialize SP with an invalid value to prevent stack trace memory reads
writereg SP 0x0f
