#######################################
#FILE
# $RCSfile: 8349MDS_init_debug_uboot.cfg,v $
# $Date: 2006/01/10 10:29:57 $
# $Revision: 1.3 $
#DESCRIPTION
#
#COPYRIGHT 
# (c) 2004 Metrowerks Corporation
# All rights reserved.
#HISTORY
# Revision 1.1  2005/01/26 16:24:21  sbabeanu
# initialization file for the 8349SYS board for debugging u-boot build at 0xFE000000
#
# Revision 1.1  2004/12/22 14:32:56  vcambrea
# u-boot ROM image debugger initialization file for the 8349SYS board
# 1st revision
# 
########################################

#setMMRBaseAddr 0xFF400000
writereg	MBAR	0xFF400000

##############################################
# System Configuration - Local Access Windows 
##############################################

# Local Bus Local Access Windows
#################################
# WINDOW 0 - FLASH
writemem.l 0xff400020 0xFE000000 # LBLAWBAR1  - begining at 0xfe000000
writemem.l 0xff400024 0x80000019 # LBLAWAR1   - enable, size = 64MB 

# DDR Local Access Windows
#################################
# WINDOW 0 - 1st DDR SODIMM
writemem.l 0xff4000a0 0xe4000000 # DDRLAWBAR0 - begining at 0xe4000000
writemem.l 0xff4000a4 0x80000010 # DDRLAWAR0  - enable, size = 128KB

##############################################
# DDR Controller Configuration
##############################################

# CS2_BNDS
# bit 8-15 - starting address
# bit 24-31 - ending address
writemem.l 0xff402010 0x00e400eb ; 0x00000000 - 0x07FFFFFF

# CS2_CONFIG
# bit 0 = 1 - CS_2_EN CS2 enable
# bit 21 - 23 = 1 - ROW_BITS_CS_2 13 rows
# bit 29 - 31 = 1 - COL_BITS_CS_2 9 columns
writemem.l 0xff402088 0x80000101

# TIMING_CONFIG_1
# bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles
# bit 4-7 = 7 - ACTTOPRE activate to precharge interval 7 clock cycles
# bit 9-11 = 3 = ACTTORW activate to r/w interval 3 clock cycles 
# bit 13 - 15 = 3 - CASLAT CAS latency 2.5 clock cycles
# bit 16 - 19 = 3 - REFREC refresh recovery time 11 clock cycles 
# bit 21 - 23 = 3 - WRREC data to precharge interval 3 clock cycles 
# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
# bit 29 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle
writemem.l 0xff402108 0x36332321

# TIMING_CONFIG_2
# bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay
writemem.l 0xff40210C 0x00000800

# temporary disable the memory interface for reconfiguration
# DDR_SDRAM_CFG
# bit 0 = 0 - MEM_EN SDRAM interface logic is disabled
# bit 1 = 1 - SREN enable self refresh during sleep
# bit 2 = 0 - ECC_EN disable ECC interrupt generation
# bit 3 = 0 - RD_EN unbuffered DIMMs
# bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM
# bit 10 = 0 - DYN_PWR power management disabled
writemem.l 0xff402110 0x42000000

# DDR_SDRAM_MODE
# bit 0 - 15 = 0x2000  - ESDMODE
# bit 16 - 31 = 0x0162 - SDMODE 
writemem.l 0xff402118 0x00000022

# DDR_SDRAM_INTERVAL
# bit 2 - 15 = 0x45b0 - REFINT 
# bit 18 - 31 = 0x0100  - BSTOPRE auto precharge r/w commands used
writemem.l 0xff402124 0x04060100

sleep 300

# enable the DDR memory controller
# DDR_SDRAM_CFG
# bit 0 = 1 - MEM_EN SDRAM interface logic enabled	
writemem.l 0xff402110 0xc2000000 


# System configuration registers

writemem.l 0xff400114 0x40000000 # SICRL

ANDmem.l 0xff400118 0x00000003 # SICRH