#######################################
#FILE
# $RCSfile: 8360MDS_init_ROM.cfg,v $
# $Date: 2006/01/10 10:22:35 $
# $Revision: 1.2 $
#DESCRIPTION
#
#COPYRIGHT 
# (c) 2004 Metrowerks Corporation
# All rights reserved.
#HISTORY
# $Log: 8360MDS_init_ROM.cfg,v $
# Revision 1.2  2006/01/10 10:22:35  vcambrea
# Update with Mandy's recommendations.
#
# Revision 1.1  2005/10/21 14:04:54  vcambrea
# 1st revision
# 
########################################

#setMMRBaseAddr 0xFF400000
writereg	MBAR	0xFF400000

##############################################
# System Configuration - Local Access Windows 
##############################################

# Local Bus Local Access Windows
#################################
# WINDOW 0 - FLASH
writemem.l 0xff400020 0xff000000 # LBLAWBAR0  - begining at 0xff000000 
writemem.l 0xff400024 0x80000017 # LBLAWAR0   - enable, size = 16MB 

##############################################
# Local Bus Interface (LBIU) Configuration
##############################################

# CS0 - 16MB FLASH 
writemem.l 0xff405000 0xff001001 # BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid
writemem.l 0xff405004 0xff006ff7 # OR0 16MB flash size, 15 w.s., timing relaxed

# LBCR - local bus enable
writemem.l 0xff4050d0 0x00000000

# LCRR
# bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles 
# bit 28 - 31 = 0x0010  - CLKDIV - system clock:memory bus clock = 2
writemem.l 0xff4050d4 0x00030002

# LSRT - refresh timer
writemem.l 0xff4050a4 0x3f000000

# System configuration registers

writemem.l 0xff400114 0x40000000 # SICRL

ANDmem.l 0xff400118 0x00000003 # SICRH

ANDMem.l 0xff400800 0x00300000 # ACR - Enable Core

	