<?xml version="1.0" standalone="no" ?>
<!--  MIPS 4Kc Register Configuration File -->
<CPU type="4Kc" family="MIPS32" immr="false" description="this is the MIPS32 4Kc cp0 register configration file">
    <Group name="CP0" description="Coprocessor 0 Registers list" >
        <Register name="index"  alias="inx"  memorymap="false" id="0x800000"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true"  description="CP0 Register 0,contains the index used to access the TLB for TLBP, TLBR, and TLBWI instructions.Compliance Level: Required for TLB-based MMUs; Optional otherwise."  signed="false" >
            <Field name="P"     size="1" location="31" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Probe Failure. Set to 1 when the previous TLBProbe (TLBP) instruction failed to find a match in the TLB" />
            <Field name="Idx"   size="31" location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Index to the TLB entry affected by the TLBRead and TLBWrite instructions." />
        </Register>    
        <Register name="random"   alias="rand"     memorymap="false" id="0x800001"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="CP0 Register 1,whose value is used to index the TLB during a TLBWR instruction.Compliance Level: Required for TLB-based MMUs; Optional otherwise."  signed="false" />
        <Register name="entrylo0" memorymap="false" id="0x800002"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true"  rdable="true" wrable="false" description="CP0 Register 2,The pair ofEntryLo registers act as the interface between the TLB and the TLBR, TLBWI, and TLBWR instructions.Compliance Level: Required for a TLB-based MMU; Optional otherwise."  signed="false" >
            <Field name="PFN"  size="24" location="6" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Page Frame Number. Corresponds to bits 31:12 of the physical address." />
            <Field name="C"    size="3"  location="3" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Coherency attribute of the page." /> 
            <Field name="D"    size="1"  location="2" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="'Dirty' bit, indicating that the page is writable." />
            <Field name="V"    size="1"  location="1" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Valid bit, indicating that the TLB entry, and thus the virtual page mapping are valid." /> 
            <Field name="G"    size="1"  location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Global bit." />
        </Register>
        <Register name="entrylo1" memorymap="false" id="0x800003"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true"  rdable="true" wrable="false" description="CP0 Register 3,Compliance Level: Required for a TLB-based MMU; Optional otherwise."  signed="false" >
            <Field name="PFN"  size="24" location="6" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Page Frame Number. Corresponds to bits 31:12 of the physical address." />
            <Field name="C"    size="3"  location="3" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Coherency attribute of the page. 0, 1, 3*, 4, 5, 6 is Cacheable, noncoherent, write through, no write allocate. 2*, 7 is Uncached" /> 
            <Field name="D"    size="1"  location="2" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="'Dirty' bit, indicating that the page is writable." />
            <Field name="V"    size="1"  location="1" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Valid bit, indicating that the TLB entry, and thus the virtual page mapping are valid." /> 
            <Field name="G"    size="1"  location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Global bit." />
        </Register>        
        <Register name="context"  alias="ctxt"  memorymap="false" id="0x800004"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true"  rdable="true" wrable="true"  description="CP0 Register 4, containing a pointer to an entry in the page table entry (PTE) array.Compliance Level: Required for TLB-based MMUs; Optional otherwise."  signed="false" >
            <Field name="PTEBase" size="9"  location="23" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"   description="a pointer into the current PTE array in memory." />
            <Field name="BadVPN2" size="19"  location="4" bitable="false" minval="0" maxval="1" rdable="true" wrable="false"  description="This field is written by hardware on a TLB exception,It contains bits VA31:13 of the virtual address that missed" /> 
        </Register>           
        <Register name="pagemask" memorymap="false" id="0x800005"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true"  description="CP0 Register 5,holds a comparison mask that sets the variable page size for each TLB entry. Compliance Level: Required for TLB-based MMUs; Optional otherwise."  signed="false" >   
            <Field name="Mask" size="16"  location="13" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="The Mask field is a bit mask in which a 1 indicates that the corresponding bit of the virtual address should not participate in the TLB match." /> 
        </Register>
        <Register name="wired"    memorymap="false" id="0x800006"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true"  description="CP0 Register 6,specifies the boundary between the wired and random entries in the TLB.Compliance Level: Required for TLB-based MMUs; Optional otherwise."  signed="false" />   
        <Register name="badvaddr" alias="vaddr" memorymap="false" id="0x800008"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="CP0 Register 8,captures the most recent virtual address that caused one of the following exceptions."  signed="false" />
        <Register name="count"    memorymap="false" id="0x800009"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true"  description="CP0 Register 9,The Count register acts as a timer,incrementing at a constantrate,whether or not an instruction is executed,retired,or any forward progress is made through the pipeline."  signed="false" />                     
        <Register name="entryhi"  memorymap="false" id="0x80000A"  bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true"  description="CP0 Register 10,TheEntryHi register contains the virtual address match information used for TLB read, write, and access operations." signed="false" >                     
            <Field name="VPN2"  size="19"  location="13" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"   description="VA31:13 of the virtual address(virtual page number/2).This field is written by hardware on a TLB exceptionor on a TLB read,and is written by software before a TLB write." />
            <Field name="ASID"  size="8"   location="0"  bitable="false" minval="0" maxval="1" rdable="true" wrable="false"  description="Address space identifier. This field is written by hardware on a TLB read and by software to establish the current ASID value for TLB write and against which TLB references match each entry's TLB ASID  eld" /> 
        </Register>  
        <Register name="compare"  memorymap="false" id="0x80000B"  bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true"  description="CP0 Register 11,The Compare register acts in conjunction with the Count register to implement a timer and timer interrupt function."  signed="false" />                     
        <Register name="status"  alias="sr" memorymap="false" id="0x80000C"  bytes="4" width="32" unused="0xFFFFFFFF" bitable="true"  rdable="true" wrable="true"  description="CP0 Register 12,contains the operating mode,interrupt enabling,and the diagnostic states of the processor" signed="false">
            <Field name="CU"  size="4" location="28" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Controls access to coprocessors 3, 2, 1, and 0," />
            <Field name="RP"  size="1" location="27" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Enables reduced power mode.The state of the RP bitis available on the bus interface as the SI_RP signal" />
            <Field name="RE"  size="1" location="25" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Used to enable reverse-endian memory references while the processor is running in user mode, 0=User mode uses configured endianness, 1=User mode uses reversed endianness." />
            <Field name="BEV" size="1" location="22" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Controls the location of exception vectors: 0=Normal 1=Bootstrap." value="1" />
            <Field name="TS"  size="1" location="21" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="TLB shutdown.This bit is set if a TLBWI or TLBWR instruction is issued that would cause a TLB shutdown condition if allowed to complete. " />
            <Field name="SR"  size="1" location="20" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Indicates that the entry through the reset exception vector was due to a Soft Reset." />
            <Field name="NMI" size="1" location="19" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Indicates that the entry through the reset exception vector was due to an NMI." />
            <Field name="IM"  size="8" location="8"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Interrupt Mask: Controls the enabling of each of the external,internal,and software interrupts." />
            <Field name="UM"  size="1" location="4"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Indicates that the processor is operating in user mode: 0=in kernel mode, 1=in user mode." />
            <Field name="ERL" size="1" location="2"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Error Level. Set by the processor when a Reset, Soft Reset, or NMI exception is taken." value="1" />
            <Field name="EXL" size="1" location="1"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Exception Level. Set by the processor when any exception other than a Reset, Soft Reset, or NMI exception is taken." />
            <Field name="IE"  size="1" location="0"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Interrupt Enable.Acts as the master enable for software and hardware interrupts: 0=disables interrupts. 1=enables interrupts" />
        </Register>
        <Register name="cause"   alias="cr"    memorymap="false" id="0x80000D" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="CP0 Register 13,primarily describes the cause of the most recent exception.also control software interrupt requests and th evector." signed="false" >
            <Field name="BD"  size="1" location="31" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates whether the last exception taken occurred in a branch delay slot" />
            <Field name="CE"  size="2" location="28" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Coprocessor unit number referenced when a Coprocessor Unusable exception is taken." />
            <Field name="IV"  size="1" location="23" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Indicates whether an interrupt exception uses the general exception vector or a special interrupt vector." />
            <Field name="WP"  size="1" location="22" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Indicates that a watch exception was deferred because Status EXL or Status ERL were a one at the time the watch exception was detected." />  
            <Field name="IP[7:2]"  size="6" location="10" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates an external interrupt is pending: 15=Hardware interrupt 5 or timer interrupt. 14 mapped to hardware interrupt 4,13 to 3,12 to 2,11 to 1,10 to 0" />
            <Field name="IP[1:0]"  size="2" location="8" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Controls the request for software interrupts. 9=Request software interrupt 1, 8=Request software interrupt 0." />
            <Field name="Exc Code" size="5" location="2" context="true" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="cause Exc Code: 0=Interrupt;1,2,3=TLB exception;4,5,6,7=address error,8=syscall,9=break,10=reserved Instruction" >
            	<Item name="Interrupt" value="0" />
            	<Item name="TLB exception" value="1!2!3" />
            	<Item name="address error" value="4!5!6!7" />
            	<Item name="syscall" value="8" />
            	<Item name="break" value="9" />
            	<Item name="reserved Instruction" value="10" />
            </Field>
        </Register>
        <Register name="epc"      memorymap="false" id="0x80000E" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 14,The Exception Program Counter (EPC) contains the address at which processing resumes after an exception has been serviced." signed="false" />
        <Register name="prid"     memorymap="false" id="0x80000F" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="CP0 Register 15,The Processor Identi cation (PRId) register contains information identifying the manufacturer, manufacturer options, processor identi cation, and revision level of the processor." signed="false" >
            <Field name="CompanyOp"    size="8" location="24" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Available to the designer or manufacturer of the processor for company-dependent options." />
            <Field name="CompanyID"    size="8" location="16" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Identifies the company that designed or manufactured the processor." />
            <Field name="ProcessorID"  size="8" location="8"  bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Identifies the type of processor." />  
            <Field name="Revision"     size="8" location="0"  bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Specifies the revision number of the processor." />
        </Register>        
        <Register name="config"   memorymap="false" id="0x800010" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="CP0 Register 16,select 0,The Config register specifies various configuration and capabilities information." signed="false" >
            <Field name="M"   size="1" location="31" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This bit is hardwired to 1 to indicate the presence of the Config1 register" />
            <Field name="K23" size="3" location="28" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="This field controls the cacheability of the kseg2 and kseg3 address segments in FM implementations." />
            <Field name="KU"  size="3" location="25" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="This field controls the cacheability of the kuseg and useg address segments in FM implementations." />
            <Field name="MDU" size="1" location="20" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This bit indicates the MDU type. 0 = Fast Multiplier Array (4Kc and 4Km cores), 1 = Iterative multiplier (4Kp cores)" />
            <Field name="MM"  size="2" location="17" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This field contains the merge mode for the 32-byte collapsing write buffer: 00 = No Merging 01 = SysAD Valid merging 10 = Full merging 11 = Reserved"/>
            <Field name="BM"  size="1" location="16" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Burst order. 0 = Sequential, 1 = SubBlock" />
            <Field name="BE"  size="1" location="15" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates the endian mode in which the processor is running:0=Little endian,1= Big endian." />
            <Field name="AT"  size="2" location="13" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Architecturetypeimplementedbytheprocessor.This field is always 00 to indicate MIPS32" />
            <Field name="AR"  size="3" location="10" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Architecture revision level. This field is always 000 to indicate revision 1.  0=Revision, 1-7=Reserved." />  
            <Field name="MT"  size="3" location="7" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="MMU Type: 1=Standard TLB (4Kc core,) 3=Fixed Mapping (4Kp, 4Km cores), All other values: Reserved" />
            <Field name="K0"  size="3" location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Kseg0 coherency algorithm. 0, 1, 3*, 4, 5, 6 is Cacheable, noncoherent, write-through, no write allocate. 2*, 7 is Uncached" />
        </Register>
        <Register name="config1"   memorymap="false" id="0x800050" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="CP0 Register 16,select 1, read-only;The Config1 register is an adjunct to the Config register and encodes additional capabilities information." signed="false" >
            <Field name="MMU Size" size="6" location="25" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="This field contains the number of entries in the TLB minus one. The field is read as 15 decimal in the 4Kc processor and as 0 decimal in the 4Kp and 4Km processors." />
            <Field name="IS"  size="3" location="22" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="This field contains the number of instruction cache sets per way. Three options are available. All others values are reserved: 0x0: 64; 0x1: 128; 0x2: 256; 0x3 - 0x7: Reserved " />
            <Field name="IL" size="3" location="19" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This field contains the instruction cache line size. If an instruction cache is present, it must contain a fixed line size of 16 bytes. 0x0: No Icache present; 0x3: 16 bytes;0x1, 0x2, 0x4 - 0x7: Reserved" />
            <Field name="IA"  size="3" location="16" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This field contains the level of instruction cache associativity.0x0: Direct mapped; 0x1: 2-way; 0x2: 3-way; 0x3: 4-way; 0x4 - 0x7: Reserved"/>
            <Field name="DS"  size="3" location="13" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This field contains the number of data cache sets per way: 0x0: 64; 0x1: 128; 0x2: 256; 0x3 - 0x7: Reserved" />
            <Field name="DL"  size="3" location="10" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This field contains the data cache line size. If a data cache is present, it must contain a line size of 16 bytes. 0x0: No Dcache present; 0x3: 16 bytes; 0x1, 0x2, 0x4 - 0x7: Reserved" />
            <Field name="DA"  size="3" location="7" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="This field contains the type of set associativity for the data cache: 0x0: Direct mapped; 0x1: 2-way; 0x2: 3-way; 0x3: 4-way; 0x4 - 0x7: Reserved" />
            <Field name="PC"  size="1" location="4" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Performance Counter registers implemented. Always a 0 since the cores do not implement any." />  
            <Field name="WR"  size="1" location="3" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Watch registers implemented. This bit always reads as 1 since the cores each contain one pair of Watch registers." />
            <Field name="CA"  size="1" location="2" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Code compression (MIPS16™) implemented. This bit always reads as 0 because MIPS16 is not supported." />
            <Field name="EP"  size="1" location="1" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="EJTAG present: This bit is always set to indicate that the core implements EJTAG." />
            <Field name="FP"  size="1" location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="FPU implemented. This bit is always zero since the core does not contain a floating-point unit." />
        </Register>
        <Register name="lladdr"   memorymap="false" id="0x800011" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="CP0 Register 17,TheLLAddr register contains the physical address read by the most recent Load Linked (LL) instruction." signed="false" />        
        <Register name="watchlo"  memorymap="false" id="0x800012" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="CP0 Register 18,The WatchLo and WatchHi registers together provide the interface to a watchpoint debug facility." signed="false" >
            <Field name="VAddr"  size="29" location="3" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="This field specifies the virtual address to match. Note that this is a doubleword address, since bits [2:0] are used to control the type of match." />
            <Field name="I"      size="1"  location="2" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If this bit is one, watch exceptions are enabled for instruction fetches that match the address" />
            <Field name="R"      size="1"  location="1" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If this bit is one, watch exceptions are enabled for loads that match the address." />  
            <Field name="W"      size="1"  location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If this bit is one, watch exceptions are enabled for stores that match the address." />
        </Register>                
        <Register name="watchhi"  memorymap="false" id="0x800013" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true" description="CP0 Register 19" signed="false" >        
            <Field name="G"      size="1"  location="30" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If this bit is one, any address that matches that specified in theWatchLo register will cause a watch exception." />
            <Field name="ASID"   size="8"  location="16" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="ASID value which is required to match that in the EntryHi register if the G bit is zero in the WatchHi register." />  
            <Field name="MASK"   size="9"  location="3"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Optional bit mask that qualifies the address in the WatchLo register." />
        </Register> 
        <Register name="debug"    memorymap="false" id="0x800017" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true"  rdable="true" wrable="true" description="CP0 Register 23,controls the debug exception and provide information about the cause of the debug exception" signed="false" >
            <Field name="DBD" size="1" location="31" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates whether the last debug exception or exception in debug mode, occurred in a branch delay slot." />
            <Field name="DM"  size="1" location="30" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that the processor is operating in debug mode:" />
            <Field name="LSNM"  size="1" location="28" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Controls access of load/store between dseg and main memory: 0=Load/stores in dseg address range goes to dseg. 1=Load/stores in dseg address range goes to main memory." />  
            <Field name="Doze"  size="1" location="27" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that the processor was in any kind of low power mode when a debug exception occurred." />
            <Field name="Halt"  size="1" location="26" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that the internal system bus clock was stopped when the debug exception occurred.0=Internal system bus clock stopped,1: Internal system bus clock running." />
            <Field name="CountDM"  size="1" location="25" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Indicates the Count register behavior in debug mode.0=Count register stopped in debug mode,1=Count register increments in debug mode." />
            <Field name="IBusEP"   size="1" location="24" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Instruction fetch Bus Error exception Pending." />
            <Field name="DBusEP"   size="1" location="21" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Data access Bus Error exception Pending." />  
            <Field name="IEXI"     size="1" location="20" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Imprecise Error eXception Inhibit controls exceptions taken due to imprecise error indications. " />
            <Field name="Ver"      size="3" location="15" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="EJTAG version" />
            <Field name="DEexCode" size="5" location="10" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates the cause of the latest exception in debug mode" />
            <Field name="SSt"      size="1" location="8" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Controls if debug single step exception is enabled." />  
            <Field name="DINT"     size="1" location="5" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Indicates that a debug interrupt exception occurred.Cleared on exception in debug mode." />
            <Field name="DIB"      size="1" location="4" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that a debug instruction break exception occurred. Cleared on exception in debug mode." />
            <Field name="DDBS"     size="1" location="3" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that a debug data break exception occurred on a store. Cleared on exception in debug mode." />
            <Field name="DDBL"     size="1" location="2" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that a debug data break exception occurred on a load. Cleared on exception in debug mode." />  
            <Field name="DBp"      size="1" location="1" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that a debug software breakpoint exception occurred. Cleared on exception in debug mode." />
            <Field name="DSS"      size="1" location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Indicates that a debug single step exception occurred.Cleared on exception in debug mode." />
        </Register>
        <Register name="depc"     memorymap="false" id="0x800018" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 24,The Debug Exception Program Counter register contains the address at which processing resumes after a debug exception or debug mode exception has been serviced." signed="false" />
        <Register name="errctl"   memorymap="false" id="0x80001A" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 26,The ErrCtl register provides a mechanism for enabling software testing of the way-select and data RAM arraysforboth the ICache and DCache. " signed="false" />
        <Register name="taglo"    memorymap="false" id="0x80001C" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 28,select 0; TheTagLo register acts as the interface to the cache tag array.Compliance Level: Required if a cache is implemented; Optional otherwise." signed="false" >
            <Field name="PA"     size="22" location="10" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="TagLo PA Bit:This field contains the physical address of the cache line being stored." />
            <Field name="Valid"  size="4"  location="4"  bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="TagLo Valid Bits :This field indicates whether the corresponding word in the cache line is valid in the cache." />
            <Field name="L"      size="1"  location="2" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"   description="TagLo L Bits: Specifies the lock bit for the cache tag. When this bit is set,the corresponding cache line should not be replaced by the cache replacement algorithm." />  
            <Field name="LRF"   size="1"  location="1" bitable="false" minval="0" maxval="1" rdable="true" wrable="false"   description="TagLo LRF Bit: LRF. One bit of the LRF bits for the set this cache line is a part of. This bit is inverted every time a new cache line is filled in the cache entry." />
        </Register>
        <Register name="datalo"    memorymap="false" id="0x80005C" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 28,select 1;The DataLo register acts as the interface to the cache data array.The Index Load Tag operation of the CACHE instruction reads the corresponding data values into the DataLo register.Note that the 4K cores do not implement the DataHi register." signed="false" />
        <Register name="eepc"     memorymap="false" id="0x80001E" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 30,TheErrorEPC register similar to theEPC register, except thatErrorEPC is used on error exceptions." signed="false" />
        <Register name="desave"   memorymap="false" id="0x80001F" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 31,The Debug Exception Save (DeSave) functions as a simple memory location.Compliance Level: Optional." signed="false" />        
    </Group>
</CPU>