<?xml version="1.0" standalone="no" ?>
<!--  MIPS 3k Register Configuration File -->
<CPU type="3k" family="MIPS32" immr="false" description="this is the MIPS32 3k cp0 register configration file">
    <Group name="CP0" description="Coprocessor 0 Registers list" >
         <Register name="index"  alias="inx"  memorymap="false" id="0x800000"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true"  description="CP0 Register 0,TLB entry index register."  signed="false" >
            <Field name="P"    size="1" location="31" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Probe Failure. Set to 1 when the previous TLBProbe (TLBP) instruction failed to find a match in the TLB" />
            <Field name="Idx"  size="6" location="8" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="TLB entry number for tlbwi, tlbr, and tlbp.." />
         </Register>    
         <Register name="random"  alias="rand"  memorymap="false" id="0x800001"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="CP0 Register 1,TLB randomized access register."  signed="false" >
            <Field name="random"  size="6" location="8" bitable="false" minval="0" maxval="1" rdable="true" wrable="false"  description="Semi-random TLB entry number used by tlbwr. Updated by processor. Never has a value between 0-7." />
        </Register>           
         <Register name="entrylo"  alias="tlblo" memorymap="false" id="0x800002"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true"  description="CP0 Register 2,Low-order word of 'current' TLB entry."  signed="false" >                      
            <Field name="PFN"    size="20" location="12" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Physical page number (bits 12-31 of address) for VM mapping." />
            <Field name="N"  size="1" location="11" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="Non-cacheable; if set, RAM cache is disabled accessing this page." />
            <Field name="D"    size="1" location="10" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description=" Dirty; if set, page may be written to. " />
            <Field name="V"  size="1" location="9" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description=" Valid; if set, page may be accessed. " />
            <Field name="G"    size="1" location="8" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Global; if set, valid in every address space." />
         </Register>    
         <Register name="context"  alias="ctxt" memorymap="false" id="0x800004"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true"  rdable="true" wrable="true"  description="CP0 Register 4, Page-table lookup address."  signed="false" >
            <Field name="PTEBase" size="11"  location="21" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"   description="Base address of page table. Untouched by hardware; maintained by software." />
            <Field name="BadVPN" size="20"  location="0" bitable="false" minval="0" maxval="1" rdable="true" wrable="false"  description=" Offset into page table for a kuseg fault (bits 12-30 of c0_vaddr), set by hardware. " /> 
        </Register>           
        <Register name="badvaddr" alias="vaddr"  memorymap="false" id="0x800008"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="false" description="CP0 Register 8,Virtual address associated with certain exceptions."  signed="false" />
        <Register name="count"    memorymap="false" id="0x800009"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true"  description="CP0 Register 9,The Count register acts as a timer,incrementing at a constantrate,whether or not an instruction is executed,retired,or any forward progress is made through the pipeline."  signed="false" />                     
        <Register name="entryhi"  alias="tlbhi"  memorymap="false" id="0x80000A"   bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="true"  description="CP0 Register 10,High-order word of 'current' TLB entry."  signed="false" >           
            <Field name="VPN" size="20"  location="12" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"   description="Virtual page number (bits 12-31 of address) for VM mapping." />
            <Field name="PID" size="6"  location="6" bitable="false" minval="0" maxval="1" rdable="true" wrable="true"  description="ID of address space in which virtual address exists." /> 
        </Register>           
        <Register name="status"   alias="sr"  memorymap="false" id="0x80000C"  bytes="4" width="32" unused="0xFFFFFFFF" bitable="true"  rdable="true" wrable="true"  description="CP0 Register 12,contains the operating mode,interrupt enabling,and the diagnostic states of the processor" signed="false">
            <Field name="CU1"  size="1" location="29" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="coprocessors 1 usable: 1 to use FPA if you have it, 0 to disable. when 0, all FPA instructions cause an exception." />
            <Field name="CU0"  size="1" location="28" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="coprocessors 0 usable: 1 to use cp0 if you have it, 0 to disable. when 0, all cp0 instructions cause an exception." />
            <Field name="BEV" size="1" location="22" bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description=" If set the 'bootstrap' exception handler addresses are used;Controls the location of exception vectors: 0=Normal 1=Bootstrap." value="1" />
            <Field name="TS"  size="1" location="21"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If set to 1, the processor is dead in the water and needs to be reset." />
            <Field name="PE"  size="1" location="20"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Set to 1 if a cache parity error occurs. Clear by writing 1." />
            <Field name="CM"  size="1" location="19"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Set to 1 if the most recent data cache load missed, but only if IsC is set." />
            <Field name="PZ" size="1" location="18"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If set to 1, uses space parity for outgoing data." value="1" />
            <Field name="SwC" size="1" location="17"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If set, the cache control lines affect the instruction cache rather than the data cache." />
            <Field name="IsC" size="1" location="16"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="If set, the data cache is detached from main memory. (For flushing.)" />
            <Field name="IM"  size="8" location="8"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="While these bits are set, the corresponding interrupts are masked and do not cause interrupt exceptions." />
            <Field name="KUo"  size="1" location="5"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Old kernel/user mode bit (1 = user mode)" />
            <Field name="IEo"  size="1" location="4"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Old interrupt enable bit (0 = mask all interrupts)" />
            <Field name="KUp"  size="1" location="3"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Previous kernel/user mode bit (1 = user mode)" />
            <Field name="IEp" size="1" location="2"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Previous interrupt enable bit (0 = mask all interrupts)" value="1" />
            <Field name="KUc" size="1" location="1"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Current kernel/user mode bit (1 = user mode)" />
            <Field name="IEc"  size="1" location="0"  bitable="false" minval="0" maxval="1" rdable="true" wrable="true" description="Current interrupt enable bit (0 = mask all interrupts)" value="1" />
        </Register>
        <Register name="cause"   alias="cr" memorymap="false" id="0x80000D" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="CP0 Register 13,primarily describes the cause of the most recent exception.also control software interrupt requests and th evector." signed="false" >
            <Field name="BD"  size="1" location="31" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Set if last exception occurred in a branch delay slot." />
            <Field name="CE"  size="2" location="28" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Coprocessor number resulting from a coprocessor unusable exception." />
            <Field name="IP"  size="6" location="10" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Bits reflecting the state of the external hardware interrupt lines. Bit 10 is irq 0." />
            <Field name="Sw"  size="2" location="8" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Software interrupts. Like IP, but controlled by software." />
            <Field name="Exc Code[4:0]" size="5" location="2" context="true" bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="cause Exc Code: 0=Interrupt;1,2,3=TLB exception;4,5,6,7=address error,8=syscall,9=break,10=reserved Instruction, 12 =Arithmetic overflow ">
            <Item name="Interrupt" value="0" />
            	<Item name="TLB exception" value="1!2!3" />
            	<Item name="address error" value="4!5!6!7" />
            	<Item name="syscall" value="8" />
            	<Item name="break" value="9" />
            	<Item name="reserved Instruction" value="10" />
            	<Item name="Arithmetic overflow" value="12" />
            </Field>
        </Register>
        <Register name="epc"      memorymap="false" id="0x80000E" bytes="4" width="32" unused="0xFFFFFFFF" bitable="false" rdable="true" wrable="true" description="CP0 Register 14,The Exception Program Counter (EPC): PC at which exception occurred." signed="false" />
        <Register name="prid"     memorymap="false" id="0x80000F" bytes="4" width="32" unused="0xFFFFFFFF" bitable="true" rdable="true" wrable="false" description="CP0 Register 15,The Processor Identi cation (PRId) register contains information identifying the manufacturer, manufacturer options, processor identification, and revision level of the processor." signed="false" >
            <Field name="ProcessorID"  size="8" location="8"  bitable="false" minval="0" maxval="1" rdable="true" wrable="false" description="Identifies the type of processor. id value of r3000 = 2" />  
        </Register>
    
    </Group>
</CPU>