/*********************************************************************
 *
 *  Copyright (C) 2004  Freescale Semiconductors, Inc.
 *
 ********************************************************************/
/*********************************************************************
 *  FILE: rio_regs.h
 *
 *  DESCRIPTION :
 *    Contains some definitions regarding the RapidIO registers and
 *    bit positions
 * NOTES :
 *     Adapted from Lan Van Nguyen's rio_85xx.h file
 * HISTORY
 * Version    Date     Auth.,Loc.     Comments
 *   0.1    27-Jul-04  LM and CC EKB  First released version
 *   0.2    16-Aug-04  LM and CC EKB  Removed unused definitions
 ********************************************************************/



typedef unsigned int u32;

typedef struct ccsr_srio {
	u32	didcar;		/* 0xc0000 - Device Identity Capability Register */
	u32	dicar;		/* 0xc0004 - Device Information Capability Register */
	u32	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
	u32	aicar;		/* 0xc000c - Assembly Information Capability Register */
	u32	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
	u32	spicar_x;		/* 0xc0014 - Switch Port Information Capability Register */
	u32	socar;		/* 0xc0018 - Source Operations Capability Register */
	u32	docar;		/* 0xc001c - Destination Operations Capability Register */
	char	res1[32];
	u32	msr_x;		/* 0xc0040 - Mailbox Command And Status Register */
	u32	pwdcsr_x;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
	char	res2[4];
	u32	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
	char	res3[12];
	u32	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
	u32	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
	char	res4[4];
	u32	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
	u32	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
	char	res5[144];
	u32	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
	char	res6[28];
	u32	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
	u32	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
	char	res7[20];
	u32	pgccsr;		/* 0xc013c - Port General Command and Status Register */
	u32	p0lmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
	u32	p0lmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
	u32	p0lascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
	char	res8[12];
	u32	p0escsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
	u32	p0ccsr;		/* 0xc015c - Port Control Command and Status Register */
	char	res9[1184];
	u32	erbh;		/*0xc0600*/
	char	res9b[4];
	u32	ltledcsr;	/*0xc0608*/
	u32	ltleecsr;	/*0xc060c*/
	char	res9c[4];
	u32 	ltlaccsr;	/*0xc0614*/
	u32 	ltldidccsr;	/*0xc0618*/
	u32	ltlcccsr;	/*0xc061c*/
	char	res9d[32];
	u32	p0edcsr;	/*0xc0640*/
	char	res9e[63932];

	u32	cr;		/* 0xd0000 - Port Control Command and Status Register */
	char	res10[12];
	u32	pcr;		/* 0xd0010 - Port Configuration Register */
	u32	peir;		/* 0xd0014 - Port Error Injection Register */
	char	res11a[264];
	u32	pptaacr;        /* 0xd0120 - accept all */ 
	char	res11b[2780];
	u32	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
	char	res12[12];
	u32	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
	char	res13[12];
	u32	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
	char	res14[4];
	u32	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
	char	res15[4];
	u32	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
	char	res16[12];
	u32	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
	char	res17[4];
	u32	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
	char	res18[4];
	u32	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
	char	res19[12];
	u32	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
	char	res20[4];
	u32	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
	char	res21[4];
	u32	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
	char	res22[12];
	u32	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
	char	res23[4];
	u32	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
	char	res24[4];
	u32	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
	char	res25[12];
	u32	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
	char	res26[4];
	u32	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
	char	res27[4];
	u32	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
	char	res28[12];
	u32	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
	char	res29[4];
	u32	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
	char	res30[4];
	u32	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
	char	res31[12];
	u32	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
	char	res32[4];
	u32	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
	char	res33[4];
	u32	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
	char	res34[12];
	u32	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
	char	res35[4];
	u32	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
	char	res36[4];
	u32	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
	char	res37[76];
	u32	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
	char	res38[4];
	u32	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
	char	res39[4];
	u32	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
	char	res40[12];
	u32	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
	char	res41[4];
	u32	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
	char	res42[4];
	u32	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
	char	res43[12];
	u32	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
	char	res44[4];
	u32	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
	char	res45[4];
	u32	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
	char	res46[12];
	u32	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
	char	res47[4];
	u32	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
	char	res48[4];
	u32	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
	char	res49[12];
	u32	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
	char	res50[12];
	u32	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
	char	res51[12];
	u32	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
	u32	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
	u32	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
	u32	pecr;		/* 0xd0e0c - Port Error Control Register */
	u32	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
	u32	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
	u32	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
	char	res52[4];
	u32	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
	char	res53[4];
	u32	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
	u32	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
	/*Changes by lorraine, 22nd March */
	//char	res54[464];
	char 	res54a[216];
	u32	pdedr;		/*d0f08 */
	u32 	pdedir;		/*d0f0c */
	char	res54b[240];
	/*end of these changes by lorraine */
	char	res54c[8192];
	u32	om0mr;		/* 0xd3000 - Outbound Mode Register */
	u32	om0sr;		/* 0xd3004 - Outbound Status Register */
	u32	om0edqdpar;	/* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
	u32	om0dqdpar;	/* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
	u32	om0eosar;	/* 0xd3010 - Extended Outbound Unit Source Address Register */
	u32	om0sar;	/* 0xd3014 - Outbound Unit Source Address Register */
	u32	om0dpr;	/* 0xd3018 - Outbound Destination Port Register */
	u32	om0datr;		/* 0xd301c - Outbound Destination Attributes Register */
	u32	om0dcr;		/* 0xd3020 - Outbound Doubleword Count Register */
	u32	om0edqepar;	/* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
	u32	om0dqepar;	/* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
	u32	om0retcr;	/* 0xd302c - Outbound Message 0 Retry Error Threshold */ 
	u32	om0mgr;		/* 0xd3030 - Outbound message 0 Multicast Group Register*/
	u32	om0mlr;		/* 0xd3034 - Outbound Message 0 Multicast List REgister */
	char	res55[40];
	u32	im0mr;		/* 0xd3060 - Outbound Mode Register */
	u32	im0sr;		/* 0xd3064 - Inbound Status Register */
	u32	im0efqdpar;	/* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
	u32	im0fqdpar;	/* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
	u32	im0efqepar;	/* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
	u32	im0fqepar;	/* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
	char	res56[904];
	u32	od0mr;		/* 0xd3400 */
	u32	od0sr;		/* 0xd3404 */
	char    res57[16];
	u32	od0dpr;		/* 0xd3418 */
	u32	od0datr;	/* 0xd341c */
	char	res58[12];
	u32	od0retcr;	/* 0xd342c */
	char	res59[48];
	u32	id0mr;		/* 0xd3460 */
	u32	id0sr;		/* 0xd3464 */
	u32	eid0qdpar;	/* 0xd3468 */
	u32	id0qdpar;	/* 0xd346c */
	u32	eid0qepar;	/* 0xd3470 */
	u32	id0qepar;	/* 0xd3474 */
	u32	id0mirir;	/* 0xd3478 */
	char	res60[100];
	u32	ipw0mr;		/* 0xd34e0 */
	u32 	ipw0sr;		/* 0xd34e4 */
	u32 	eipw0qbar;	/* 0xd34e8 */
	u32	ipw0qbar;	/* 0xd34ec */

	char	res61[51984];
	

} ccsr_srio_t;



//#define	NULL          ((void *) 0)
#define TRUE           1
#define FALSE          0

/* Error Codes */
#define SUCCESS                 0       /* successful return code */
/* Return when there is another host which has bigger power-on Device ID */
#define ERROR_BAD_TRANSACTION  -1
#define ERROR_SLAVE            -2       /* slave device */
#define ERR_LOCK               -3       /* device has been locked by another host */
#define ERR_INVALID_PARAMETER  -4       /* invalid input paramenters */

/* RIO transaction types */
#define RIO_MREAD       7       /* RIO maintenance read */
#define RIO_MWRITE      RIO_MREAD       /* RIO maintenance write */
#define RIO_NREAD       4       /* RIO Normal read */
#define RIO_NWRITE      RIO_NREAD       /* RIO Normal write */

/* RIO Transaction flow */
#define MEDIUM_LEVEL    1

#define RIO_ROWTAR1                                   0xD0C20
#define   ROW_DEV_ID_Mask                             0x3FC00000
#define   ROW_DEV_ID_Shift                            22
#define   ROW_TEA_Mask                                0x00300000
#define   ROW_TEA_Shift                               20
#define   ROW_HOPCNT_Mask                             0x000FF000       /* maintenance only */
#define   ROW_HOPCNT_Shift                            12
#define   ROW_OFS_Mask                                0x00000FFF       /* maintenance only */
#define   ROW_OFS_Shift                               0
#define   ROW_TA_Mask                                 0x000FFFFF
#define   ROW_TA_Shift                                0
/* For maintenance configuration read/write offset conversion */
#define   ROW_OFF2CO(x)  (((x)>>ROW_OFS_Shift)&ROW_OFS_Mask)   /* regOffset to configOffset */
#define   ROW_CO2OFF(x)  (((x)&ROW_OFS_Mask)<<ROW_OFS_Shift)   /* configOffset to regOffset */
/* For normal read/write address conversion */
#define   ROW_ADDR2TA(x) (((x)>>12)&ROW_TA_Mask)
#define   ROW_TA2ADDR(x) (((x)&ROW_TA_Mask)<<12)
#define RIO_ROWBAR1                                   0xD0C28
#define   ROW_BEA_Mask                                0x00F00000
#define   ROW_BEA_Shift                               20
#define   ROW_BA_Mask                                 0x000FFFFF
#define   ROW_BA_Shift                                0
#define   ROW_ADDR2BA(x) (((x)>>12)&ROW_BA_Mask)
#define   ROW_BA2ADDR(x) (((x)&ROW_BA_Mask)<<12)
#define RIO_ROWAR1                                    0xD0C30
#define   ROW_En_Mask                                 0x80000000
#define   ROW_En_Shift                                31
#define   ROW_Tflowlvl_Mask                           0x0C000000
#define   ROW_Tflowlvl_Shift                          26
#define   ROW_pci_order_Mask                          0x02000000
#define   ROW_pci_order_Shift                         25
#define   ROW_ReadTType_Mask                          0x000F0000
#define   ROW_ReadTType_Shift                         16
#define   ROW_WriteTType_Mask                         0x0000F000
#define   ROW_WriteTType_Shift                        12
#define   ROW_WindSize_Mask                           0x0000003F
#define   ROW_WindSize_Shift                          0
#define RIO_RIWTAR1                                   0xD0DC0
#define   RIW_TEA_Mask                                0x00F00000
#define   RIW_TEA_Shift                               20
#define   RIW_TA_Mask                                 0x000FFFFF
#define   RIW_TA_Shift                                0
#define RIO_RIWBAR1                                   0xD0DC8
#define   RIW_BEA_Mask                                0x00300000
#define   RIW_BEA_Shift                               20
#define   RIW_BA_Mask                                 0x000FFFFF
#define   RIW_BA_Shift                                0
#define RIO_RIWAR1                                    0xD0DD0
#define   RIW_En_Mask                                 0x80000000
#define   RIW_En_Shift                                31
#define   RIW_TgtInt_Mask                             0x00F00000
#define   RIW_TgtInt_Shift                            20
#define   RIW_ReadTType_Mask                          0x000F0000
#define   RIW_ReadTType_Shift                         16
#define   RIW_WriteTType_Mask                         0x0000F000
#define   RIW_WriteTType_Shift                        12
#define   RIW_WindSize_Mask                           0x0000003F
#define   RIW_WindSize_Shift                          0

