/*
 * Copyright 2004 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#undef PQ37PC_DEBUG
#ifdef PQ37PC_DEBUG
	#define DEBUG(arg...) printf(arg)
#else
	#define DEBUG(arg...)
#endif


#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>

#include "../../drivers/tsec.h"


#include <miiphy.h>

#include "mpc8548pc.h"

/* MPC8548PC */
/*extern int tsec_miiphy_write(char *devname, unsigned char addr,
		unsigned char reg, unsigned short value);

extern void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);		
*/		

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33333333
 *    66666666
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.
 */
unsigned long get_clock_freq(void)
{
	/*Use on board 66.66667Mhz*/
	return 66666667;
}


/*Get boot port size from PORMBSR register for BR0*/
/*For MPC8548PC REVA, the flash is 8-bit */
/*For MPC8548PC REVB, the flash is 16-bit */
unsigned long get_br0(void)
{
	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
    volatile ccsr_gur_t *gur = &immap->im_gur;
    
    long temp = (gur->porbmsr & 0x07000000)>>24;
    if (temp == 0x5)
    	return 0xff800801;

    else if (temp == 0x6)
		return 0xff801001;
     
}

/*Get boot port size from PORMBSR register for BR1*/
/*For MPC8548PC REVA, the flash is 8-bit */
/*For MPC8548PC REVB, the flash is 16-bit */
unsigned long get_br1(void)
{
	
	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
    volatile ccsr_gur_t *gur = &immap->im_gur;
    
	long temp = (gur->porbmsr & 0x07000000)>>24;
    if (temp == 0x5)
       	return 0xff000801;

    else if (temp == 0x6)
		return 0xff001001;
      
}


char* get_prompt(void)
{
	uint svr = get_svr();
  
	switch (svr){
	  	case 0x80390011:
      			return "MPC8548E_Rev1.1=> ";
	  	case 0x80390020:
      			return "MPC8548EPC_Rev2.0=> ";
	  	case 0x80390021:
      			return "MPC8548PC_Rev2.0=> ";
		case 0x80390120:
			return "MPC8547EPC_Rev2.0=> ";
		case 0x80390220:
			return "MPC8545EPC_Rev2.0=> ";
		case 0x80310220:
			return "MPC8545PC_Rev2.0=> ";
		case 0x803A0020:
			return "MPC8543EPC_Rev2.0=> ";
		case 0x80320020:
			return "MPC8543PC_Rev2.0=> ";
    	default:
      	return "=> ";
  }
}

int board_early_init_f (void)
{
/*rapncsg*/
	uint svr = get_svr();
	if (svr == 0x80390011)
	{

	DEBUG("%s: ENTER\n", __FUNCTION__);
/*Add GEN5 errata if Rev1.x silicon */
	vu_char* base = (vu_char *)GEN5_REG;
/*MPC8548PC, add GEN5 errata fix for Rev1.x silicon */
		*base = 0x00800000;
	base = (vu_char *)0xe00d0120; /*enable RIO AACR*/
	*base = 1;
	DEBUG("%s: EXIT\n", __FUNCTION__);	
	}


   return 0;
}

int	board_early_init_r (void)
{
	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_lbc_t *memctl = &immap->im_lbc;

/*Set the initial value for scan the flash*/
	memctl->br0 = CFG_BR0_PRELIM;
	memctl->or0 = CFG_OR0_PRELIM;
	memctl->or1 = CFG_OR1_PRELIM;
	memctl->br1 = CFG_BR1_PRELIM;

	return 0;
}

/* various things to do after relocation */


int misc_init_r ()
{
	
/* misc configuration for the board */		   	
    	return 0;
}


#define ECNTRL_RPM		0x00000010


void reset_phy(void)
{
	/*MPC8548PC*/
	/*Need switch to detect if RGMII is used and set RGMII 1.5ns clk skew*/
	/*Need switch to detect if Marvell phy to set RGMII 1.5ns*/
	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_tsec_t *tsec1 = &immap->im_tsec1;
	volatile ccsr_tsec_t *tsec2 = &immap->im_tsec2;
	volatile ccsr_tsec_t *tsec3 = &immap->im_tsec3;
	volatile ccsr_tsec_t *tsec4 = &immap->im_tsec4;
	struct eth_device *dev;
	struct tsec_private *priv;
	struct phy_info *theInfo;

    vu_char* base = (vu_char *)CFG_LED_BASE;
	DEBUG("%s: ENTER\n", __FUNCTION__);

	dev = (struct eth_device *)eth_get_dev_by_name("eTSEC0");
	priv = (struct tsec_private*)dev->priv;
	if (tsec1->ecntrl&ECNTRL_RPM){
		printf("eTSEC0 & eTSEC1 in Reduce mode\n");
		/*set RGMII 1.5ns on tx, rx clk in Marvell*/
		if (priv->phyinfo->name == "Marvell 88E1111S")
		{
			DEBUG("eTSEC0: Add 1.5ns clk skew in Marvell\n");
			DEBUG("Phyaddr = %d\n",priv->phyaddr);
			tsec_miiphy_write("eTSEC0", priv->phyaddr,20,0x0ce2);
		}
	}
   	/*reset Phy*/
   	tsec_miiphy_write("eTSEC0", priv->phyaddr,0,0x9140);

	dev = (struct eth_device *)eth_get_dev_by_name("eTSEC1");
	priv = (struct tsec_private*)dev->priv;
	if ((tsec2->ecntrl&ECNTRL_RPM)&&(priv->phyinfo->name == "Marvell 88E1111S"))
	{
		DEBUG("eTSEC1: Add 1.5ns clk skew in Marvell\n");
		DEBUG("Phyaddr = %d\n",priv->phyaddr);
		/*set RGMII 1.5ns on tx, rx clk in Marvell*/
		tsec_miiphy_write("eTSEC1", priv->phyaddr,20,0x0ce2);
	}
	/*reset Phy*/
   	tsec_miiphy_write("eTSEC1", priv->phyaddr,0,0x9140);

	dev = (struct eth_device *)eth_get_dev_by_name("eTSEC2");
	priv = (struct tsec_private*)dev->priv;
	if (tsec3->ecntrl&ECNTRL_RPM){
		printf("eTSEC2 & eTSEC3 in Reduce mode\n");
		/*set RGMII 1.5ns on tx, rx clk in Marvell*/
		if (priv->phyinfo->name == "Marvell 88E1111S")
		{
			DEBUG("eTSEC2: Add 1.5ns clk skew in Marvell\n");
			DEBUG("Phyaddr = %d\n",priv->phyaddr);
			tsec_miiphy_write("eTSEC2", priv->phyaddr,20,0x0ce2);
		}
	}
   	/*reset Phy*/
   	tsec_miiphy_write("eTSEC2", priv->phyaddr,0,0x9140);

	dev = (struct eth_device *)eth_get_dev_by_name("eTSEC3");
	priv = (struct tsec_private*)dev->priv;
	if ((tsec4->ecntrl&ECNTRL_RPM)&&(priv->phyinfo->name == "Marvell 88E1111S"))
	{
		DEBUG("eTSEC3: Add 1.5ns clk skew in Marvell\n");
		DEBUG("Phyaddr = %d\n",priv->phyaddr);
		/*set RGMII 1.5ns on tx, rx clk in Marvell*/
		tsec_miiphy_write("eTSEC3", priv->phyaddr,20,0x0ce2);
	}
   	/*reset Phy*/
   	tsec_miiphy_write("eTSEC3", priv->phyaddr,0,0x9140);

/*MPC8548PC*/	
	udelay(1000);
	*base = 0xf0;
	DEBUG("%s: EXIT\n", __FUNCTION__);
}


long int initdram(int board_type)
{
	long dram_size = 0;
	extern long spd_sdram (void);
    vu_char* base = (vu_char *)CFG_LED_BASE;
	sys_info_t sysinfo;

	unsigned long val;
    *base = 0xf7;

	DEBUG("%s: ENTER\n", __FUNCTION__);

	puts("Initializing\n");
	get_sys_info(&sysinfo);

	dram_size = fixed_sdram(&sysinfo);

	puts("DDR:   ");

	DEBUG("%s: EXIT\n", __FUNCTION__);
	*base = 0xf3;
	return dram_size;
}


/*
 * Initialize Local Bus
 */

void
local_bus_init(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
    vu_char* base = (vu_char *)CFG_LED_BASE;

	uint lbc_hz;
	sys_info_t sysinfo;

	DEBUG("%s: ENTER\n", __FUNCTION__);

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	lbc_hz = sysinfo.freqSystemBus / 1000000 / (CFG_LBC_LCRR & 0x0f);

	DEBUG("(CFG_LBC_LCRR & 0x0f): %d\n", (CFG_LBC_LCRR & 0x0f));
	DEBUG("sysinfo.freqSystemBus %d\n", sysinfo.freqSystemBus);
	DEBUG("lbc_hz: %d\n", lbc_hz);

	if (lbc_hz < 66) {
		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
	}
	else if (lbc_hz >= 133){
		if (lbc_hz > 166)		/* LBC not support > 166 */
			lbc->lcrr = CFG_LBC_LCRR4 & (~0x80000000); /* DLL Enabled */
		else
		 	lbc->lcrr = CFG_LBC_LCRR2 & (~0x80000000); /* DLL Enabled */
		udelay(200);
	}
	else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		
		uint pvr = get_pvr();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
	DEBUG("%s: EXIT\n", __FUNCTION__);
	*base = 0xf1;
}

#if defined(CFG_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test passed.\n");
	return 0;
}
#endif


/*************************************************************************
 *  fixed sdram init -- on board DDR2
 ************************************************************************/
long int fixed_sdram (sys_info_t * sysinfopt)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	#if defined (CFG_DDR_IO_OVCR)
	volatile ccsr_gur_t *gur= &immap->im_gur;
	#endif
	DEBUG("System Freq: %lu\n", sysinfopt->freqSystemBus);
	ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
	ddr->cs0_bnds = CFG_CS0_BNDS;
	ddr->cs0_config = CFG_CS0_CONFIG;
	ddr->timing_cfg_0 = CFG_TIMING_CFG_0;
	ddr->sdram_cfg = CFG_DDR_SDRAM_CFG;
	ddr->sdram_mode_2 = CFG_DDR_SDRAM_MODE2;
	ddr->sdram_md_cntl = CFG_DDR_SDRAM_MD_CNTL;
	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
    #if defined (CONFIG_DDR_ECC)
		ddr->sdram_cfg_2 = (CFG_DDR_SDRAM_CFG2 | 0x10);
		printf("..init ECC");
	#else
		ddr->sdram_cfg_2 = CFG_DDR_SDRAM_CFG2;
	#endif

	#if defined (CFG_DDR_IO_OVCR)
		gur->ddrioovcr = CFG_DDR_IO_OVCR;
	#endif

	if (sysinfopt->freqSystemBus<420000000) {
		ddr->ext_refrec = CFG_EXT_REFREC_400;
		ddr->timing_cfg_1 = CFG_TIMING_CFG_1_400;
		ddr->timing_cfg_2 = CFG_TIMING_CFG_2_400;
		ddr->sdram_mode = CFG_DDR_SDRAM_MODE_400;
		ddr->sdram_interval = CFG_DDR_SDRAM_INT_400;
	} else if (sysinfopt->freqSystemBus<540000000) {
		ddr->ext_refrec = CFG_EXT_REFREC_533;
		ddr->timing_cfg_1 = CFG_TIMING_CFG_1_533;
		ddr->timing_cfg_2 = CFG_TIMING_CFG_2_533;
		ddr->sdram_mode = CFG_DDR_SDRAM_MODE_533;
		ddr->sdram_interval = CFG_DDR_SDRAM_INT_533;
	} else {
		ddr->ext_refrec = CFG_EXT_REFREC_667;
		ddr->timing_cfg_1 = CFG_TIMING_CFG_1_667;
		ddr->timing_cfg_2 = CFG_TIMING_CFG_2_667;
		ddr->sdram_mode = CFG_DDR_SDRAM_MODE_667;
		ddr->sdram_interval = CFG_DDR_SDRAM_INT_667;
	}
		DEBUG("\ntiming setup\n");

    #if defined (CONFIG_DDR_ECC)
		ddr->err_disable = 0x0000000D;
		ddr->err_sbe = 0x00ff0000;
    #endif
		DEBUG("disable ECC checking\n");
	asm("sync;isync;msync");
	udelay(500);

    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
		ddr->sdram_cfg = (CFG_DDR_SDRAM_CFG | 0xA0000000);
    #else
		ddr->sdram_cfg = (CFG_DDR_SDRAM_CFG | 0x80000000);
    #endif
   		DEBUG("enable DDR\n");
	asm("sync; isync; msync");
	udelay(500);


	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
    #if defined (CONFIG_DDR_ECC)
		DEBUG("start poll\n");
		while ((ddr->sdram_cfg_2 & 0x10) != 0) {
			udelay(1000);
			DEBUG("ddr->sdram_cfg_2=0x%x\n",ddr->sdram_cfg_2);
		}
		DEBUG("ddr->sdram_cfg_2=0x%x\n",ddr->sdram_cfg_2);
		DEBUG("          ");
		printf("\b\b\b\b\b\b\b\b\b\b");
    #endif

	return (CFG_SDRAM_SIZE * 1024 * 1024);
}

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_pq38pc_config_table[] = {
    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
      PCI_IDSEL_NUMBER, PCI_ANY_ID,
      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				   PCI_ENET0_MEMADDR,
				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
      } },
    { }
};
#endif


static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_pq38pc_config_table,
#endif
};

#endif	/* CONFIG_PCI */

void pci_init_board(void)
{
#ifdef CONFIG_PCI
	extern void pci_mpc85xx_init(struct pci_controller *hose);

	pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}

int checkboard(void)
{
   	volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
   	volatile ccsr_gur_t *gur = &immap->im_gur;
   	vu_char* base = (vu_char *)CFG_LED_BASE;
   	*base = 0xff;

   	uint pci1_32 = (gur->pordevsr & 0x10000)>>16;	/* PORDEVSR[15] */
   	uint io_sel = (gur->pordevsr & 0x00380000)>>19;	/* PORDEVSR[10:12] */
   	/*rapncsg*/
   	uint srds_en = (gur->pordevsr2 & 0x00000004)>>2;	/* PORDEVSR2[29] */
   	uint xmieq03 = (gur->srdscr0 & 0x0000f000)>>12;	/* srdscr0[16:19] */
   	uint xmieq47 = (gur->srdscr0 & 0x00000f00)>>8;		/* srdscr0[20:23] */
   	/*rapncsg*/
   	uint pci1_clk_sel = (gur->porpllsr & 0x8000) >>15; /* PORPLLSR[16] */
   	uint pci2_clk_sel = (gur->porpllsr & 0x4000) >>14; /* PORPLLSR[17] */
   	uint pci1_speed = (*base & 0x4) >> 2;    
   	uint pci2_speed = (*base & 0x8) >> 3;
	/*rapncsg*/
	uint host_agt = (gur->porbmsr & 0x00070000) >>16; /* PORBMSR[13:15] */
		
	
	/*S2 SW2 for BOOT1#*/
	/*BOOT1# = 0, boot0 = 1, U30 is boot flash*/
	/*BOOT1# = 1, boot0 = 0, U28 is boot flash*/
	uint boot0 = (*base & 0x10) >> 4;
	
	uint devdisr = gur->devdisr;
	
	/*rapncsg*/
	uint CFG_PEX_HOST = 0;
	uint CFG_SRIO_HOST = 0;
	uint CFG_PCI1_HOST = 0;    

	DEBUG("%s: ENTER\n", __FUNCTION__);
	DEBUG("porpllsr=%x:pci1_clk_sel=%x:pci2_clk_sel=%x \n", gur->porpllsr, pci1_clk_sel, pci2_clk_sel);
   	printf("\nBoard: MPC85xx Processor Card Rev. %.1c.\n", ((*base & 0x3) + 'A'));
	printf("       -- Boot Flash is %s\n\n", (boot0 == 0) ? "U28" : "U30");
	
	//printf("host_agt =%x \n",host_agt);
	/*rapncsg*/
	switch (host_agt){

			   	
	  	case 0:
	   	//#undef CFG_PEX_HOST
	   	//#undef CFG_SRIO_HOST
	   	//#define CFG_PCI1_HOST
	   	CFG_PCI1_HOST = 1;   	
	   	break;
    		
    		case 1:
	   	//#define CFG_PEX_HOST
	   	//#undef CFG_SRIO_HOST
	   	//#define CFG_PCI1_HOST
	   	CFG_PEX_HOST = 1;   	
	   	CFG_PCI1_HOST = 1;   	
	   	break;
	  	
	  	case 2:
	   	//#undef CFG_PEX_HOST
	   	//#define CFG_SRIO_HOST
	   	//#define CFG_PCI1_HOST
	   	CFG_SRIO_HOST = 1;   	
	   	CFG_PCI1_HOST = 1;   	
	     	break;
	     	
	  	case 4:	
	  	//#define CFG_PEX_HOST
	   	//#undef CFG_SRIO_HOST
	   	//#undef CFG_PCI1_HOST
	   	CFG_PEX_HOST = 1;  
	   	 	
	     	break;
	  
	  	case 5:
	   	//#define CFG_PEX_HOST
	   	//#undef CFG_SRIO_HOST
	   	//#define CFG_PCI1_HOST
	   	CFG_PEX_HOST = 1;   
	   	CFG_PCI1_HOST = 1;   		
	      	break;
	   
	   	case 6:
	   	//#define CFG_PEX_HOST
	   	//#define CFG_SRIO_HOST
	   	//#undef CFG_PCI1_HOST
	   	CFG_SRIO_HOST = 1;   
	   	CFG_PEX_HOST = 1;   
	    	break;
	   	
	   	case 7:
	   	//#define CFG_PEX_HOST
	   	//#define CFG_SRIO_HOST
	   	//#define CFG_PCI1_HOST
	   	CFG_PEX_HOST = 1;   
	   	CFG_SRIO_HOST = 1;   
	   	CFG_PCI1_HOST = 1;  
	     	break;
    	default:
	   	printf("unknown Host/Agent mode\n");
	   	}
 	
	
	
	if (srds_en == 1)
	{
		printf("SerDes Interface is enabled\n");
		/*rapncsg*/
		vu_char* srio_base = (vu_char *)SRIO_AACR; /*enable RIO AACR*/
		
		/*printf("CFG_PEX_HOST =%x \n",CFG_PEX_HOST);
		printf("CFG_srio_HOST =%x \n",CFG_SRIO_HOST);
		printf("CFG_pci1_HOST =%x \n",CFG_PCI1_HOST);*/

#if 1	/*rapncsg*/
		if (io_sel == 7){
			printf("PEX :  X8 2.5Gbps,");
	  		if (CFG_PEX_HOST)
	  			printf(" Root Complex\n");
	  		else
	  			printf(" Endpoint\n");	  		
	  	}
	  	
		else if (io_sel == 6){
			printf("SRIO:  X4 1.25Gbps,");
	   		*srio_base = 0x1;	/*rapncsg*/
	   		if (CFG_SRIO_HOST)
	  			printf(" Host\n");
	  		else
	  			printf(" Agent\n");
	  		
		}
		
		else if (io_sel == 5){
			printf("SRIO:  X4 3.125Gbps, Need 125Mhz serdes clock,");
	   		*srio_base = 0x1;	/*rapncsg*/
	   		if (CFG_SRIO_HOST)
	  			printf(" Host\n");
	  		else
	  			printf(" Agent\n");
	  	
		}
		
		else if (io_sel == 4){
			printf("SRIO:  X4 1.25Gbps,");
	   		*srio_base = 0x1;	/*rapncsg*/
	   		if (CFG_SRIO_HOST)
	  			printf(" Host\n");
	  		else
	  			printf(" Agent\n");
	  			  	
	  		printf("PEX :  X4 2.5Gbps,");
	  		if (CFG_PEX_HOST)
	  			printf(" Root Complex\n");
	  		else
	  			printf(" Endpoint\n");
	  	
			
		}
		
		else if (io_sel == 3){
			printf("SRIO:  X4 2.5Gbps,");
	   		*srio_base = 0x1;	/*rapncsg*/
	   		if (CFG_SRIO_HOST){
	  			printf(" Host\n");}
	  		else{
	  			printf(" Agent\n");}
	  		
	  	
	  		printf("PEX :  X4 2.5Gbps,");
	  		if (CFG_PEX_HOST){
	  			printf(" Root Complex\n");}
	  		else{
	  			printf(" Endpoint\n");}			
		}
		
		else{
		printf("unknown SERDES mode\n");
		}
#endif	
#if 0	
	switch (io_sel){
	  	case 7:
	  	printf("PEX :  X8 2.5Gbps\n ");
	  	break;
    		
    		case 6:
	   	printf("SRIO:  X4 1.25Gbps\n");
	   	*srio_base = 0x1;	/*rapncsg*/
	   	break;
	  	
	  	case 5:
	   	printf("SRIO:  X4 3.125Gbps, Caution!! need 125Mhz serdes clock input\n");
	   	*srio_base = 0x1;	/*rapncsg*/
	   	break;
	  	
	  	case 4:		
	   	printf("SRIO:  X4 1.25Gbps \n");
	   	*srio_base = 0x1;	/*rapncsg*/
	 
	  	printf("PEX :  X4 2.5Gbps \n");
	  	
	   	break;
	  	
	  	case 3:
	   	printf("SRIO:  X4 2.5Gbps \n");
	   	*srio_base = 0x1;	/*rapncsg*/
	   	
	  	printf("PEX :  X4 2.5Gbps \n");
	  	
	   	break;
    	default:
	   	printf("unknown SERDES mode\n");
	   	}
#endif 	
	}
	else
		printf("SerDes Interface is disabled, No sRIO and PEX support\n\n");
	
	
	if (CFG_PCI1_HOST){
		printf("PCI1:  %d bit, %s\n", (pci1_32) ? 32 : 64, pci1_clk_sel ? "sync," : "async, " "Host");
	}
	else 
		printf("PCI1:  %d bit, %s\n", (pci1_32) ? 32 : 64, pci1_clk_sel ? "sync," : "async, " "Agent");
   
/*   printf("PCI1:  %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, (pci1_speed == 0) ? "33" : 
   	(pci1_speed == 1) ? "66" : "unknown", pci1_clk_sel ? "sync" : "async");
*/

   if ((pci1_32 == 0) || (devdisr & 0x40000000))   /* PCI2 disabled if not dual pci */
      printf("PCI2:  disabled\n");
	else if (pci2_clk_sel) /*sync mode*/
/*	   printf("PCI2:  32 bit, sync\n", (pci1_speed == 0) ? "33" : (pci1_speed == 1) ? "66" : "unknown"); */
	   printf("PCI2:  32 bit, sync, Host\n");
	else	/*async mode*/    
/*	  	printf("PCI2:  32 bit, async\n", (pci2_speed == 0) ? "33" : (pci2_speed == 1) ? "66" : "unknown");*/
	  	printf("PCI2:  32 bit, async, Host\n");

	/*
	 * Initialize local bus.
	 */
	local_bus_init();

	DEBUG("%s: EXIT\n", __FUNCTION__);
    return 0;
}
