/*
 *  tsec.h
 *
 *  Driver for the Motorola Triple Speed Ethernet Controller
 *
 *  This software may be used and distributed according to the
 *  terms of the GNU Public License, Version 2, incorporated
 *  herein by reference.
 *
 * (C) Copyright 2003, Motorola, Inc.
 * maintained by Xianghua Xiao (x.xiao@motorola.com)
 * author Andy Fleming
 *
 */

#ifndef __TSEC_TEST_H
#define __TSEC_TEST_H

#include <net.h>
#include <mpc85xx.h>

// Lu ATM def
typedef volatile unsigned char		Vint8u;
typedef volatile unsigned short int	Vint16u;
typedef volatile unsigned int		Vint32u;

typedef	char		   		BYTE;
typedef unsigned char 			UBYTE;	
typedef	short		   		HWORD;	
typedef	unsigned short			UHWORD;	
typedef	long		   		WORD;	
typedef unsigned long 			UWORD;	
typedef unsigned char 			BOOL;	

typedef	volatile char		   	VBYTE;
typedef volatile unsigned char 		VUBYTE;	
typedef	volatile short		   	VHWORD;	
typedef	volatile unsigned short		VUHWORD;	
typedef	volatile long		   	VWORD;	
typedef volatile unsigned long		VUWORD;	
typedef volatile unsigned char 		VBOOL;	

/*-----------------------------------*/
/* CPM Command Register definitions. */
/*-----------------------------------*/

#define CR_FLG       0x00010000   /* Command Register "flag" bit */ 
#define CPCR_ATM     0x0A         /* ATM Protocol specification  */ 
#define INIT_TX_RX   0x00000000   /* "Initialize Rx/Tx param." command */ 
#define ATM_TRANSMIT 0x0000000A   /* "Activate ATM Transmit" command   */ 

/*-----------------------------------------------*/
/* General FCC Mode Register (GFMR) definitions. */
/*-----------------------------------------------*/

#define GFMR_ENT      0x00000010  /* Enable Transmitter */ 
#define GFMR_ENR      0x00000020  /* Enable Receiver    */ 
#define GFMR_ATM      0x0000000A  /* ATM protocol def.  */ 
#define GFMR_DIAG_LPB 0x40000000  /* Enable Receiver    */ 

#define FPSMR_ATM_RUMS	0x00200000

#define TRUE 	1
#define FALSE 	0 

#define INTERNAL 1  /* Internal loopback or schedule tick */ 
#define EXTERNAL 2  /* External loopback or schedule tick */ 

#define READY_TO_RX_CMD  0   /* Ready to receive a command */

// End Lu ATM def

#define TSEC_BASE_ADDR	(CFG_IMMR + 0x24000)
#define TSEC2_BASE_ADDR (CFG_IMMR + 0x25000)
#define TSEC_MEM_SIZE	0x01000

#define MAC_ADDR_LEN 6

#define TSEC_TIMEOUT 	1000000
#define TOUT_LOOP 	1000000

/* MAC register bits */
#define MACCFG1_SOFT_RESET	0x80000000
#define MACCFG1_RESET_RX_MC	0x00080000
#define MACCFG1_RESET_TX_MC	0x00040000
#define MACCFG1_RESET_RX_FUN	0x00020000
#define	MACCFG1_RESET_TX_FUN	0x00010000
#define MACCFG1_LOOPBACK	0x00000100
#define MACCFG1_RX_FLOW		0x00000020
#define MACCFG1_TX_FLOW		0x00000010
#define MACCFG1_SYNCD_RX_EN	0x00000008
#define MACCFG1_RX_EN		0x00000004
#define MACCFG1_SYNCD_TX_EN	0x00000002
#define MACCFG1_TX_EN		0x00000001

#define MACCFG2_INIT_SETTINGS	0x00007205
#define MACCFG2_FULL_DUPLEX	0x00000001
#define MACCFG2_IF              0x00000300
#define MACCFG2_MII             0x00000100
#define MACCFG2_GMII            0x00000200

#define ECNTRL_INIT_SETTINGS	0x00001000
#define ECNTRL_TBI_MODE         0x00000020

#define TBIPA_VALUE		0x1f
#define MIIMCFG_INIT_VALUE	0x00000003
#define MIIMCFG_RESET		0x80000000

#define MIIMIND_BUSY            0x00000001
#define MIIMIND_NOTVALID        0x00000004

#define MIIM_TBICON		0x11
#define MIIM_TBICON_GMII	0x00000010
#define MIIM_TBICON_AN		0x00000100

#define MIIM_CONTROL            0x00
#define MIIM_CONTROL_INIT       0x00001140
#define MIIM_ANEN               0x00001000

#define MIIM_TBI_STATUS		0x1
#define MIIM_TBI_STATUS_AN_DONE 0x00000020

#define MIIM_TBI_ANEX		0x6
#define MIIM_TBI_ANEX_NP	0x00000004
#define MIIM_TBI_ANEX_PRX	0x00000002

#define MIIM_TBI_ANLPBPA	0x5
#define MIIM_TBI_ANLPBPA_HALF	0x00000040
#define MIIM_TBI_ANLPBPA_FULL	0x00000020

#ifdef CONFIG_PHY_CIS8201
#define MIIM_AUX_CONSTAT	0x1c
#define MIIM_AUXCONSTAT_INIT	0x0004
#define MIIM_AUXCONSTAT_DUPLEX	0x0020
#define MIIM_AUXCONSTAT_SPEED   0x0018
#define MIIM_AUXCONSTAT_GBIT    0x0010
#define MIIM_AUXCONSTAT_100     0x0008

#define MIIM_EXT_CON1		0x17
#define MIIM_EXTCON1_INIT	0x0000

#endif

#define MIIM_ANAR		0x04
#define MIIM_ANAR_ADVERTISEMENT	0x01e1

#define MIIM_GBIT_CON		0x09
#define MIIM_GBIT_CON_ADVERT	0x1e00

#define MIIM_PHY_STATUS         0x11
#define MIIM_PHYSTAT_SPEED      0xc000
#define MIIM_PHYSTAT_GBIT       0x8000
#define MIIM_PHYSTAT_100        0x4000
#define MIIM_PHYSTAT_DUPLEX     0x2000
#define MIIM_PHYSTAT_SPDDONE	0x0800
#define MIIM_PHYSTAT_LINK	0x0400

#ifdef CONFIG_PHY_M88E1111 /* add by jeffrey for 88E1111*/
#define MIIM_ANAR		0x04    /*reg 4 for auto-neg adver reg*/
#define MIIM_ANAR_ADVERTISEMENT	0x01e1	/*reg value for 10/100/half/full enable*/

#define MIIM_GBIT_CON		0x09	/*reg 9 for 1000Base control reg*/
#define MIIM_GBIT_CON_ADVERT	0x0e00	/*reg value for auto master/slave and 1000base FD only */

#define MIIM_PHY_STATUS         0x11	/*reg 17 for phy status reg*/
#define MIIM_PHYSTAT_SPEED      0xc000
#define MIIM_PHYSTAT_GBIT       0x8000
#define MIIM_PHYSTAT_100        0x4000
#define MIIM_PHYSTAT_DUPLEX     0x2000
#define MIIM_PHYSTAT_SPDDONE	0x0800
#define MIIM_PHYSTAT_LINK	0x0400
#endif

#define MIIM_READ_COMMAND       0x00000001

#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN

#define MINFLR_INIT_SETTINGS	0x00000040

#define DMACTRL_INIT_SETTINGS   0x000000c3
#define DMACTRL_GRS             0x00000010
#define DMACTRL_GTS             0x00000008

#define TSTAT_CLEAR_THALT       0x80000000
#define RSTAT_CLEAR_RHALT       0x00800000

/* Write value to the PHY at phyid to the register at offset, */
/* using the register space defined in regbase.  Note that */
/* miimcfg needs to have the clock speed setup correctly.  This */
/* macro will wait until the write is done before it finishes */

#define write_phy_reg(regbase, phyid, offset, value) do { \
	int timeout=1000000; \
	regbase->miimadd = (phyid << 8) | offset; \
	regbase->miimcon = value; \
	asm("msync"); \
	while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
} while(0)


#define IEVENT_INIT_CLEAR	0xffffffff
#define IEVENT_BABR		0x80000000
#define IEVENT_RXC		0x40000000
#define IEVENT_BSY		0x20000000
#define IEVENT_EBERR		0x10000000
#define IEVENT_MSRO		0x04000000
#define IEVENT_GTSC		0x02000000
#define IEVENT_BABT		0x01000000
#define IEVENT_TXC		0x00800000
#define IEVENT_TXE		0x00400000
#define IEVENT_TXB		0x00200000
#define IEVENT_TXF		0x00100000
#define IEVENT_IE		0x00080000
#define IEVENT_LC		0x00040000
#define IEVENT_CRL		0x00020000
#define IEVENT_XFUN		0x00010000
#define IEVENT_RXB0		0x00008000
#define IEVENT_GRSC		0x00000100
#define IEVENT_RXF0		0x00000080

#define IMASK_INIT_CLEAR	0x00000000
#define IMASK_TXEEN		0x00400000
#define IMASK_TXBEN		0x00200000
#define IMASK_TXFEN             0x00100000
#define IMASK_RXFEN0		0x00000080


/* Default Attribute fields */
#define ATTR_INIT_SETTINGS     0x000000c0
#define ATTRELI_INIT_SETTINGS  0x00000000


/* TxBD status field bits */
#define TXBD_READY		0x8000
#define TXBD_PADCRC		0x4000
#define TXBD_WRAP		0x2000
#define TXBD_INTERRUPT		0x1000
#define TXBD_LAST		0x0800
#define TXBD_CRC		0x0400
#define TXBD_DEF		0x0200
#define TXBD_HUGEFRAME		0x0080
#define TXBD_LATECOLLISION	0x0080
#define TXBD_RETRYLIMIT		0x0040
#define	TXBD_RETRYCOUNTMASK	0x003c
#define TXBD_UNDERRUN		0x0002
#define TXBD_STATS              0x03ff

/* RxBD status field bits */
#define RXBD_EMPTY		0x8000
#define RXBD_RO1		0x4000
#define RXBD_WRAP		0x2000
#define RXBD_INTERRUPT		0x1000
#define RXBD_LAST		0x0800
#define RXBD_FIRST		0x0400
#define RXBD_MISS		0x0100
#define RXBD_BROADCAST		0x0080
#define RXBD_MULTICAST		0x0040
#define RXBD_LARGE		0x0020
#define RXBD_NONOCTET		0x0010
#define RXBD_SHORT		0x0008
#define RXBD_CRCERR		0x0004
#define RXBD_OVERRUN		0x0002
#define RXBD_TRUNCATED		0x0001
#define RXBD_STATS		0x003f

typedef struct txbd8
{
	ushort       status;         /* Status Fields */
	ushort       length;         /* Buffer length */
	uint         bufPtr;         /* Buffer Pointer */
} txbd8_t;

typedef struct rxbd8
{
	ushort       status;         /* Status Fields */
	ushort       length;         /* Buffer Length */
	uint         bufPtr;         /* Buffer Pointer */
} rxbd8_t;

typedef struct rmon_mib
{
	/* Transmit and Receive Counters */
	uint	tr64;		/* Transmit and Receive 64-byte Frame Counter */
	uint	tr127;		/* Transmit and Receive 65-127 byte Frame Counter */
	uint	tr255;		/* Transmit and Receive 128-255 byte Frame Counter */
	uint	tr511;		/* Transmit and Receive 256-511 byte Frame Counter */
	uint	tr1k;		/* Transmit and Receive 512-1023 byte Frame Counter */
	uint	trmax;		/* Transmit and Receive 1024-1518 byte Frame Counter */
	uint	trmgv;		/* Transmit and Receive 1519-1522 byte Good VLAN Frame */
	/* Receive Counters */
	uint	rbyt;		/* Receive Byte Counter */
	uint	rpkt;		/* Receive Packet Counter */
	uint	rfcs;		/* Receive FCS Error Counter */
	uint	rmca;		/* Receive Multicast Packet (Counter) */
	uint	rbca;		/* Receive Broadcast Packet */
	uint	rxcf;		/* Receive Control Frame Packet */
	uint	rxpf;		/* Receive Pause Frame Packet */
	uint	rxuo;		/* Receive Unknown OP Code */
	uint	raln;		/* Receive Alignment Error */
	uint	rflr;		/* Receive Frame Length Error */
	uint	rcde;		/* Receive Code Error */
	uint	rcse;		/* Receive Carrier Sense Error */
	uint	rund;		/* Receive Undersize Packet */
	uint	rovr;		/* Receive Oversize Packet */
	uint	rfrg;		/* Receive Fragments */
	uint	rjbr;		/* Receive Jabber */
	uint	rdrp;		/* Receive Drop */
	/* Transmit Counters */
	uint	tbyt;		/* Transmit Byte Counter */
	uint	tpkt;		/* Transmit Packet */
	uint	tmca;		/* Transmit Multicast Packet */
	uint	tbca;		/* Transmit Broadcast Packet */
	uint	txpf;		/* Transmit Pause Control Frame */
	uint	tdfr;		/* Transmit Deferral Packet */
	uint	tedf;		/* Transmit Excessive Deferral Packet */
	uint	tscl;		/* Transmit Single Collision Packet */
	/* (0x2_n700) */
	uint	tmcl;		/* Transmit Multiple Collision Packet */
	uint	tlcl;		/* Transmit Late Collision Packet */
	uint	txcl;		/* Transmit Excessive Collision Packet */
	uint	tncl;		/* Transmit Total Collision */

	uint	res2;

	uint	tdrp;		/* Transmit Drop Frame */
	uint	tjbr;		/* Transmit Jabber Frame */
	uint	tfcs;		/* Transmit FCS Error */
	uint	txcf;		/* Transmit Control Frame */
	uint	tovr;		/* Transmit Oversize Frame */
	uint	tund;		/* Transmit Undersize Frame */
	uint	tfrg;		/* Transmit Fragments Frame */
	/* General Registers */
	uint	car1;		/* Carry Register One */
	uint	car2;		/* Carry Register Two */
	uint	cam1;		/* Carry Register One Mask */
	uint	cam2;		/* Carry Register Two Mask */
} rmon_mib_t;

typedef struct tsec_hash_regs
{
	uint	iaddr0;		/* Individual Address Register 0 */
	uint	iaddr1;		/* Individual Address Register 1 */
	uint	iaddr2;		/* Individual Address Register 2 */
	uint	iaddr3;		/* Individual Address Register 3 */
	uint	iaddr4;		/* Individual Address Register 4 */
	uint	iaddr5;		/* Individual Address Register 5 */
	uint	iaddr6;		/* Individual Address Register 6 */
	uint	iaddr7;		/* Individual Address Register 7 */
	uint	res1[24];
	uint	gaddr0;		/* Group Address Register 0 */
	uint	gaddr1;		/* Group Address Register 1 */
	uint	gaddr2;		/* Group Address Register 2 */
	uint	gaddr3;		/* Group Address Register 3 */
	uint	gaddr4;		/* Group Address Register 4 */
	uint	gaddr5;		/* Group Address Register 5 */
	uint	gaddr6;		/* Group Address Register 6 */
	uint	gaddr7;		/* Group Address Register 7 */
	uint	res2[24];
} tsec_hash_t;

typedef struct tsec
{
	/* General Control and Status Registers (0x2_n000) */
	uint	res000[4];

	uint	ievent;		/* Interrupt Event */
	uint	imask;		/* Interrupt Mask */
	uint	edis;		/* Error Disabled */
	uint	res01c;
	uint	ecntrl;		/* Ethernet Control */
	uint	minflr;		/* Minimum Frame Length */
	uint	ptv;		/* Pause Time Value */
	uint	dmactrl;	/* DMA Control */
	uint	tbipa;		/* TBI PHY Address */

	uint	res3[22];
	uint	fifo_tx_thr;		/* 0x.08c - FIFO transmit threshold register */
	uint	res4[2];
	u32	fifo_tx_starve;		/* 0x.098 - FIFO transmit starve register */
	u32	fifo_tx_starve_shutoff;	/* 0x.09c - FIFO transmit starve shutoff register */
	uint	res5[24];

	/* Transmit Control and Status Registers (0x2_n100) */
	uint	tctrl;		/* Transmit Control */
	uint 	tstat;		/* Transmit Status */
	uint	res108;
	uint	tbdlen;		/* Tx BD Data Length */
	uint	res110[5];
	uint	ctbptr;	        /* Current TxBD Pointer */
	uint	res128[23];
	uint	tbptr;		/* TxBD Pointer */
	uint	res188[30];
	/* (0x2_n200) */
	uint        res200;
	uint	tbase;		/* TxBD Base Address */
	uint	res208[42];
	uint	ostbd;		/* Out of Sequence TxBD */
	uint	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
	uint        res2b8[18];

	/* Receive Control and Status Registers (0x2_n300) */
	uint	rctrl;		/* Receive Control */
	uint	rstat;		/* Receive Status */
	uint	res308;
	uint	rbdlen;		/* RxBD Data Length */
	uint	res310[4];
	uint        res320;
	uint	crbptr; 	/* Current Receive Buffer Pointer */
	uint	res328[6];
	uint	mrblr;  	/* Maximum Receive Buffer Length */
	uint	res344[16];
	uint	rbptr;   	/* RxBD Pointer */
	uint        res388[30];
	/* (0x2_n400) */
	uint        res400;
	uint	rbase;  	/* RxBD Base Address */
	uint        res408[62];

	/* MAC Registers (0x2_n500) */
	uint	maccfg1;	/* MAC Configuration #1 */
	uint	maccfg2;	/* MAC Configuration #2 */
	uint	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
	uint	hafdup;		/* Half-duplex */
	uint	maxfrm;		/* Maximum Frame */
	uint	res514;
	uint	res518;

	uint	res51c;

	uint	miimcfg;	/* MII Management: Configuration */
	uint	miimcom;	/* MII Management: Command */
	uint	miimadd;	/* MII Management: Address */
	uint	miimcon;	/* MII Management: Control */
	uint	miimstat;	/* MII Management: Status */
	uint	miimind;	/* MII Management: Indicators */

	uint	res538;

	uint	ifstat;		/* Interface Status */
	uint	macstnaddr1;	/* Station Address, part 1 */
	uint	macstnaddr2;	/* Station Address, part 2 */
	uint	res548[46];

	/* (0x2_n600) */
	uint	res600[32];

	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
	rmon_mib_t	rmon;
	uint	res740[48];

	/* Hash Function Registers (0x2_n800) */
	tsec_hash_t	hash;

	uint        res900[128];

	/* Pattern Registers (0x2_nb00) */
	uint        resb00[62];
	uint        attr;          /* Default Attribute Register */
	uint        attreli;       /* Default Attribute Extract Length and Index */

	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
	uint	resc00[256];
} tsec_t;


/*---------------------------*/
/* ATM mode parameters table */
/*---------------------------*/

typedef struct AtmPram
{
	Vint8u reserved0[64];		/* Reserved */
	Vint16u RxCellTmpBase;		/* Rx cell temporary base address */
	Vint16u TxCellTmpBase;		/* Tx cell temporary base address */
	Vint16u VUdcTmpBase;		/* VUDC temp base address (in VUDC mode only) */
	Vint16u IntRctBase;			/* Internal RTC base address */
	Vint16u IntTctBase;			/* Internal TCT base address */
	Vint16u IntTcteBase;		/* Internal ACT base address */
	Vint32u RasTimerDuration;	/* RAS_Timer for AAL2 */
	Vint32u ExtRctBase;			/* Extrnal RTC base address */
	Vint32u ExtTctBase;			/* Extrnal TCT base address */
	Vint32u ExtTcteBase;		/* Extrnal ACT base address */
	Vint16u VUeadOffset;		/* The offset in half-wordunits of the VUEAD
								   entry in the VUDC extra header. Should be
								   even address. If little-endian format is
								   used, the VUeadOffset is of the little-endian
								   format. */
	Vint16u RxQDBaseInt;		/* Point to the base of internal Rx_Queue_Descriptor Table (AAL2) */
	Vint16u PmtBase;			/* Performance monitoring table base address */
	Vint16u ApcParamBase;		/* APC Parameters table base address */
	Vint16u FbpParamBase;		/* Free buffer pool parameters base address */
	Vint16u IntQParamBase;		/* Interrupt queue parameters table base */
	Vint16u MspParamBase;		/* Base address for MSP parameter table in DPR */
	Vint16u VUniStatTableBase;	/* VUNI statistics table base */
	Vint32u BdBaseExt;			/* BD ring base address extension */

	Vint32u VptBase;			/* VP-level addressing table base address */
	Vint32u VctBase;			/* VC-level addressing table base address */
	Vint32u Vpt1Base;			/* VP1-level addressing table base address */
	Vint32u Vct1Base;			/* VC1-level addressing table base address */
	Vint16u VpMask;				/* VP mask for address compression look-up */

	Vint16u VciFiltering;		/* VCI filtering enable bits. If bit i is set,
								   the cell with VCI=i will be sent to the
								   raw cell queue. The bits 0-2 and 5 should
								   be zero. */
	Vint16u Gmode;				/* Global mode */
	Vint16u CommInfo1;			/* The information field associated with the host command */
	Vint16u CommInfo2;			/* Information field for channel code */
	Vint16u CommInfo3;			/* Information field for Burst tolerance or cell ptr (MSP) */
	Vint8u reserved4[4];		/* Reserved */
	Vint32u CRC32Preset;		/* Preset for CRC32 */
	Vint32u CRC32Mask;			/* Constant mask for CRC32 */
	Vint16u AAL1SnpTableBase;	/* AAl1 SNP protection look-up table base */
	Vint16u reserved5;			/* Reserved */
	Vint32u SrtsBase;			/* External SRTS logic base address. For AAL1
								   only. Should be 16 bytes aligned */
	Vint16u IdleBase;			/* Idle cell base address */
	Vint16u IdleSize;			/* Idle cell size: 52, 56, 60, 64 */
	Vint32u EmptyCellPayload;	/* Empty cell payload (little-indian) */

	/* ABR specific only */
	Vint32u Trm;				/* VUpper bound on time between F-RM cells for active source */
	Vint16u Nrm;				/* Controls the maximum data cells sent for each F-RM cell. */
	Vint16u Mrm;				/* Controls bandwidth between F-RM, B-RM and user data cell */
	Vint16u Tcr;				/* Tag cell rate */
	Vint16u AbrRxTcte;			/* ABR reserved area address (2-int16u aligned) */

	/* For AAL2 */
	Vint32u RxQDBaseExt;		/* Point to the base of external Rx_Queue_Descriptor Table */
	Vint32u RxUDCBase;			/* Point to the base of Rx UDC header Table */
	Vint32u TxUDCBase;			/* Point to the base of Tx UDC header Table */
	Vint8u rsvd1[32];
	Vint32u TCellTmpBaseExt;	/* Transmit Cell Temporary Base address */

	Vint8u reserved7[24];
	Vint16u PadTmpBase;			/* internal DPRAM PAD template base address */
	/* For Policer */
	Vint16u P_Param_Base;
}
AtmPram_t;

typedef struct cpm_iop {
	uint pdir;
	uint ppar;
	uint psor;
	uint podr;
	uint pdat;
	char res1[12];
} cpm_iop_t;

/* 0x91300-0x9131f: FCC1, 0x91320-0x9133f: FCC2, 0x91340-0x9135f: FCC3 */
typedef struct cpm_fcc {
	uint gfmr;
	uint psmr;
	ushort todr;
	u_char res1[2];
	ushort dsr;
	u_char res2[2];
	uint fcce;
	uint fccm;
	u_char fccs;
	char res3[3];
	uint ftprr;
} cpm_fcc_t;

/* 0x91360-0x9137f reserved */

/* 0x91380-0x913df : FCC1, FCC2, FCC3 continued  */
typedef struct cpm_fcc_cont {
	uint firper;
	uint firer;
	uint firsr_hi;
	uint firsr_lo;
	u_char gfemr;
	char res[15];
} cpm_fcc_cont_t;

typedef struct cpm_intctl {
	ushort sicr;
	char res1[2];
	uint sivec;
	uint sipnrh;
	uint sipnrl;
	uint siprr;
	uint scprrh;
	uint scprrl;
	uint simrh;
	uint simrl;
	uint siexr;
	char res2[88];
	uint sccr;
	char res3[124];
} cpm_intctl_t;

typedef struct cpm_mux {
	u_char cmxsi1cr;
	char res1;
	u_char cmxsi2cr;
	char res2;
	uint cmxfcr;
	uint cmxscr;
	char res3[2];
	ushort cmxuar;
	char res4[16];
} cpm_mux_t;

/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
typedef struct cpm_brg2 {
	uint brgc5;
	uint brgc6;
	uint brgc7;
	uint brgc8;
	char res[608];
} cpm_brg2_t;

/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
typedef struct cpm_brg1 {
	uint brgc1;
	uint brgc2;
	uint brgc3;
	uint brgc4;
} cpm_brg1_t;

/* 0x919c0-0x919ef: CPM core */
typedef struct cpm_cp {
	uint cpcr;
	uint rccr;
	char res1[14];
	ushort rter;
	char res2[2];
	ushort rtmr;
	ushort rtscr;
	char res3[2];
	uint rtsr;
	char res4[12];
} cpm_cp_t;


////////////////////////// ATM data structure///////////////////////////////////////////////

/**********************************************/
/* Receive Connection Table (RCT) structures. */ 
/**********************************************/

/*--------------------------------------------*/
/* RCT status and control bit data structure. */ 
/*--------------------------------------------*/

typedef struct 
{
    unsigned reserved1:2;
    unsigned gbl:1;        /* Global - enable snooping */ 
    unsigned bo:2;         /* Byte ordering            */     
    unsigned reserved2:1; 
    unsigned dtb:1;        /* Data Buffer bus selection */ 
    unsigned bib:1;        /* BD/Int queue bus selection */ 
    unsigned reserved3:1;
    unsigned bufm:1;       /* Buffer mode               */
    unsigned segf:1;       /* F5 segment filtering      */
    unsigned endf:1;       /* F5 end-to-end segment filtering */ 
    unsigned cpuu:1;       /* CPUU copying - enable     */ 
    unsigned reserved4:1;
    unsigned intq:2;       /* Int. queue selection.     */
    unsigned reserved5:1;
    unsigned inf:1;        /* In-frame indication.      */ 
    unsigned reserved6:10;
    unsigned abrf:1;       /* ABR Flow control.         */
    unsigned aal:3;        /* AAL selection.            */ 
}  t_Rct_stat; 

/*---------------------*/
/* RCT data structure. */ 
/*---------------------*/
#if 0
typedef struct
{	t_Rct_stat Stat_field; /* RCT status/control word data structure */ 
union{
	VUWORD p_RxData;	 /* Rx data buffer pointer*/
	VUWORD abcd;
}aa;

	VUWORD CellTimeStamp; /* Cell time stamp */
	VUHWORD RxBdOffset;	 /* Rx BD offset from Rx BD base address */

	      VUHWORD Tml;		
	      VUWORD CRC_TempRes;	
	      VUHWORD RxBdCnt;
	      VUHWORD Pcr;		
	      VUHWORD StatusMask;	


	VUHWORD Mrblr;		/* Maximum receive buffer length */
	VUWORD RxBdBase;		/* Rx BD base address */
} t_Rct;
#endif

typedef struct 
{
    union				/* RCT Status Fields */
    {
      VUWORD Stat_word;	     /* RCT status/control word */
      t_Rct_stat Stat_field; /* RCT status/control word data structure */ 
    } RctStatus; 

//4byte
    VUWORD p_RxData;	 /* Rx data buffer pointer*/
    VUWORD CellTimeStamp; /* Cell time stamp */
    VUHWORD RxBdOffset;	 /* Rx BD offset from Rx BD base address */
//14byte

    union				/* Protocol specific RCT */
    {

	   /* AAL5 protocol specific RCT */
	//VUHWORD StatusMask;	
	    struct
	   {
	      VUHWORD Tml;		
	      VUHWORD CRC_TempRes1;	   		    	
//	      VUWORD CRC_TempRes;	
	      VUHWORD CRC_TempRes2;
	      VUHWORD RxBdCnt;
	      VUHWORD Pcr;		
	      VUHWORD StatusMask;	
	   }  AAL_5;
//26 byte

	   /* AAL1 protocol specific RCT */
	    struct
	   {	    
	      VUHWORD StatusBits;	/* The SRTV, SRT, PFM and STF status bits */

	      VUHWORD SrtsDevice;  /* SRTS device (0-15) */

	      VUBYTE Vos;		      /* Valid octet size ( 1-47 for unstructured 
	                              format and 1-46 for structured). Used in 
	                              partially filled cell mode only. */

	      VUBYTE Sp;		      /* Structured pointer. */
	      VUHWORD RxBdCnt;	   /* Receive BD count */
	      VUHWORD SeqNumber;	/* Sequence number */

	      VUHWORD StatusMask;	/* RXBM (Receive buffer mask) and SNEM (Sequence 
	                              number error flag) interrupt masks */    
	   }  AAL_1;
//26 byte
	   
/*
	    struct
	    {
	    	VUHWORD a;
	    	VUHWORD b;
	    	VUBYTE c;
	    	VUBYTE d;
	    	VUHWORD e;
	    	VUHWORD f;
	    	VUHWORD g;
	} hihi;
*/	
	   /* AAL0 protocol specific RCT */
	    struct
	   {
	      VUHWORD StatusBits;	
	      VUBYTE reserved3[8];
	      VUHWORD StatusMask;
	   }  AAL_0;
//26 bytes

	    struct
	   {
	      VUBYTE reserved4[10];
	      VUHWORD StatusMask;	
	   }  General;

//26 bytes

    } ProtocolSpecificRct;

//26 bytes
    VUHWORD Mrblr;		/* Maximum receive buffer length */
    VUWORD RxBdBase;		/* Rx BD base address */
//32 bytes
} t_Rct;

/*********************************************/
/* Transmit Connection Table (TCT) structure */ 
/*********************************************/

typedef  struct 
{
    unsigned reserved1:2;
    unsigned gbl:1;       /* Global - enable snooping */ 
    unsigned bo:2;        /* Byte ordering.           */ 
    unsigned reserved2:1;
    unsigned dtb:1;       /* Data buffer bus - local/ppc   */
    unsigned bib:1;       /* BD/int. queue bus - local/ppc */
    unsigned avcf:1;      /* Auto VC                       */ 
    unsigned reserved3:1;
    unsigned att:2;       /* ATM traffic type - e.g. CBR   */ 
    unsigned cpuu:1;      /* CPUU insertion.               */ 
    unsigned vcon:1;      /* Virtual Channel On            */ 
    unsigned intq:2;      /* Interrupt queue selection.    */ 
    unsigned reserved4:1;
    unsigned inf:1;       /* In-frame, xmit state.         */ 
    unsigned reserved5:10;
    unsigned abrf:1;      /* ABR Flow control.             */ 
    unsigned aal:3;       /* AAL selection.                */ 
} t_Tct_stat; 

/*---------------------*/
/* TCT data structure. */ 
/*---------------------*/

typedef  struct 
{
    union				/* TCT Status Fields */
    {
      VUWORD Stat_word;	     /* TCT status/control word. */
      t_Tct_stat Stat_field; /* TCT status/control data structure */
    } TctStatus; 

    VUWORD p_TxData;		   /* Tx data buffer pointer */
    VUHWORD  TxBdCnt;		/* Tx BD count */
    VUHWORD  TxBdOffset;	/* Tx BD offset from TBD_BASE */
    VUBYTE  RateReminder;	/* Rate reminder */
    VUBYTE  PcrFraction;	/* Peak cell rate fraction */
    VUHWORD  Pcr;			   /* Peak cell rate */

    union				/* Protocol specific TCT */
      {
	      /* AAL5 protocol specific TCT */
	       struct 
	      {
	         VUHWORD CRC_TempRes1;	/* CRC32 temporary result */
	         VUHWORD CRC_TempRes2;
	         VUHWORD  Tml;		/* Total message length */
	      }  AAL_5;

	      /* AAL1 protocol specific TCT */
	       struct 
	      {
	         VUBYTE  Vos;		/* Valid octed size (1-47 for unstructured 
	                              format, 1-46 for structured) Used in partial 
	                              fill cell mode only */

	         VUBYTE  StatusBits;	/* SRT - Synchronous residuum time stamp;
					                     PFM - Partially filled mode;
					                     STF - Structured format;
					                     SPF - Structured pointer flag;
					                     SN - Sequence number bits */

	         VUHWORD  BlockSize;	/* Structured block size. (In structured 
	                                 format only) */

	         VUHWORD  Sp;		/* Structured pointer (12 least significant bits). */
	      }  AAL_1;

	      /* AAL0 protocol specific TCT */
	       struct 
	      {
	         VUHWORD  StatusBits;	/* CR10 and ACHC bits */
	         VUHWORD RESERVED4_1;
	         VUHWORD RESERVED4_2;
	      }  AAL_0;

      } ProtocolSpecificTct;

    VUHWORD  ApcLinkedChannel;	/* APC linked channel */
    VUWORD CellHeader;		      /* ATM cell header */
    VUWORD TxBdBase;		         /* Holds the PMT number Tx BD base address
					                  and interrupt masks */
} t_Tct;

/*----------------------------------------*/ 
/* Interrupt Queue (INTQ) Parameter Table.*/ 
/*----------------------------------------*/ 

typedef  struct
{
    VUWORD IntqBase;	/* Base address of interrupt queue */
    VUWORD p_IntQ;	/* Pointer to interrupt queue entry */
    VUHWORD IntCnt;	/* Interrupt counter */
    VUHWORD IntInitCnt;	/* Interrupt counter initial value */
    VUWORD IntqEntry;	/* Pointer to interrupt queue entry */
}  t_IntQParameterTbl;

/************************/
/* APC Parameter Table  */
/************************/

typedef  struct
{
    VUHWORD ApcLevFirst; /* Address of first APC priority level */
    VUHWORD ApcLevLast;  /* Address of last APC priority level */
    VUHWORD ApcLevPtr;   /* Address of current APC priority level */
    VUBYTE Cps;          /* Number of cells sent per APC slot */
    VUBYTE CpsCnt;       /* Cells per APC slot counter */
    VUBYTE MaxIteration; /* Max iteration allowed */
    VUBYTE CpsABR;       /* Cells per APC slot for ABR protocol only */
    VUHWORD LineRateABR; /* The line rate of the port for ABR protocol only */
    VUWORD RealTstPtr;   /* Real time stamp pointer */ 
    VUWORD ApcState;	
    VUBYTE RESERVED11[12];
}  t_ApcParameterTbl;

/***********************/
/* APC Priority table  */
/***********************/

typedef  struct
{
    VUHWORD ApcLevBase;	/* APC level i base address */
    VUHWORD ApcLevEnd;	/* APC level i end address */
    VUHWORD ApcLevRptr;	/* APC level i real-time pointer */
    VUHWORD ApcLevSptr;	/* APC level i service pointer */
}  t_ApcPriorityTbl;

/* RCT initialization parameters */ 
typedef struct
{
    UWORD  ch_num;      /* Initialize this channel's RCT entry */
    UWORD  bd_addr;     /* Address of BD */ 
    UBYTE  reset;
    UBYTE  interrupt;   /* Enable interrupt */  
} t_RCT_param; 
	
/* TCT initialization parameters */ 
typedef struct
{
    UWORD  ch_num;      /* Initialize this channel's TCT entry */ 
    UWORD  bd_addr;     /* BD address */
    UWORD  be_header;   /* Big Endian header */ 
    UWORD  vc_rate; 
    UBYTE  reset;
} t_TCT_param; 

/*
 * ATM Cell header data structure used in TCT.
 *
 * Note: This data structure is Big Endian.
 *
*/ 

typedef  struct
{
 unsigned gfc:4; 	/* Generic Flow Control;      */ 
 unsigned vpi:8;	/* Virtual Path Identifier    */ 
 unsigned vci:16;	/* Virtual Channel Identifier */ 
 unsigned pti:3; 	/* Payload type Identifier    */
 unsigned clp:1; 	/* Cell Loss Priority         */
}t_Cell_header; 

/* AAL0 data buffer format */ 
typedef  struct
{
  t_Cell_header cell_header; 
  UBYTE payload[48]; 
  UBYTE reserved[12];

} t_AAL0_buf; 

/* CPM CPCR - bit definitions. */ 
typedef  struct
{
  unsigned rst:1; 
  unsigned page:5; 
  unsigned sbc:5; 
  unsigned unused1:4; 
  unsigned flg:1; 
  unsigned unused2:2; 
  unsigned protocol:8; 
  unsigned unused3:2; 
  unsigned opcode:4; 

} t_Cpm_cpcr; 

typedef struct 
{
    UHWORD  status; 	 /* Transmit BD status/control field */
    UHWORD  length;	 /* Length of frame to transmit */ 
    UBYTE   *buf;	    /* Pointer to frame data structure */ 
} t_BD_ATM;

/* Buffer Descriptor initialization parameters */ 
typedef struct
{
    UWORD  ch_num;      /* Initialize THIS channel's BD */
    UBYTE  interrupt;   /* Enable interrupts? TRUE/FALSE */
    UBYTE  type;        /* BD type, NORMAL/PORT_TO_PORT */ 
} t_BD_param; 

////////////////////////// End ATM data structure ///////////////////////////////////////////////

#endif /* __TSEC_H */
