/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PQ37pc_8540 board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
#define CONFIG_MPC8540		1	/* MPC8540 specific */
#define CONFIG_PQ37PC	1	/* PQ37PC board specific */

#define CONFIG_PCI
#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
#define CONFIG_RESET_PHY_R		/*MPC8548PC*/


#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
extern unsigned long get_br0(void);		
extern unsigned long get_br1(void);
#endif

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	get_clock_freq()
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board early init in ram before flash init*/
#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest region */
#define CFG_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */


/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

/****************************************/
/* DDR SDRAM 256Mbit     13 Row, 9 Col  */
/* DDR SDRAM 512Mbit     13 Row, 10 Col */
/* DDR SDRAM 1024Mbit    14 Row, 10 col */
/****************************************/
#define CFG_DDR_CS0_BNDS_64		0x00000003	/* 0-64MB */
#define CFG_DDR_CS0_CONFIG_64	0x80000001
#define CFG_DDR_CS0_BNDS_128	0x00000007	/* 0-128MB */
#define CFG_DDR_CS0_CONFIG_128	0x80000101
#define CFG_DDR_CS0_BNDS_256	0x0000000f	/* 0-256MB */
#define CFG_DDR_CS0_CONFIG_256	0x80000102
#define CFG_DDR_CS0_BNDS_512	0x0000001f	/* 0-512MB */
#define CFG_DDR_CS0_CONFIG_512	0x80000202

/*
 * Manually set up DDR parameters
 */
#define CFG_DDR_TIMING_1	0x47433331
#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL	0x07a10100	/* autocharge,no open page */
/* Auto Select for DDR */
#define SAMSUNG_DDR333
/*#define FAST_DDR*/

#if defined(SAMSUNG_DDR333) || defined(NANYA_DDR333)
  
  /* Define timing parameters of DDR in ns*/
  #define CFG_DDR_TRP	18
  #define CFG_DDR_TRAS  42
  #define CFG_DDR_TRCD  18
  #define CFG_DDR_CAS   15
  #define CFG_DDR_TRFC  72
  #define CFG_DDR_TWR   15
  #define CFG_DDR_TRRD  12
  #define CFG_DDR_TWTR  6
  #define CFG_DDR_TREFI 7800
  
  #define CFG_DDR_BSTOPRE 0x100 /* hard-code */
  
  #define CFG_DDR_REFINT_MASK  0x3FFF0000
  #define CFG_DDR_BSTOPRE_MASK 0x00003FFF       /* open page mode, no auto precharge */
  
#endif
/* End of Modification of auto select for DDR */



#define	CFG_FLASH_BASE     	0xff000000      	/* start of FLASH   */
#define CFG_BR0_PRELIM		get_br0()		/* Get BR0 setting from get_br0()*/
#define CFG_OR0_PRELIM  	0xff806f37

/* For AUTO adjustment of Flash base addresses */
#define CFG_BR0_SCAN		get_br0()		/* depends on port size 	*/
#define CFG_BR1_SCAN		get_br1()		/* depends on port size 	*/
#define CFG_OR1_SCAN    	0xff806f37
#define CFG_OR0_SCAN    	0xff806f37
#define CFG_MAX_FLASH_ADJUST	5
#define CFG_MAX_FLASH_TSIZE		BOOKE_PAGESZ_16M
#define CFG_FLASH_BANKS_LIST	{(CFG_FLASH_BASE + 0x800000), CFG_FLASH_BASE}

#define CFG_OR0_PRELIM      0xff806f37


#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_LED_BASE        0xf8000000  /* start of LED and Board ID */
#define CFG_BR7_PRELIM      0xf8000801  /* port size 8 bit */
#define CFG_OR7_PRELIM      0xffffef97  /* LED and Board ID */

#define CFG_LBC_LCRR		0x00010008    /* LB clock ratio reg = CCB/8 */
#define CFG_LBC_LCRR2		0x00010002    
#define CFG_LBC_LCRR4		0x00010004    
#define CFG_LBC_BASE		0xf0000000		/* LB base for all the LBC CSx*/

#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */

#define CFG_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*#define CFG_MONITOR_LEN	    	(256 * 1024) *//* Reserve 256 kB for Mon */
#define CFG_MONITOR_LEN	    	(512 * 1024)	/* Reserve 512 kB for u-boot size */
#define CFG_MALLOC_LEN	    	(4 * 1024 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* I2C */
#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */

/* RapidIO MMU */
#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0xe2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MPC85XX_TSEC1	1
#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
#define CONFIG_MPC85XX_TSEC2	1
#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		4
#define TSEC2_PHY_ADDR		5
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define CONFIG_MPC85XX_FEC	1
#define CONFIG_MPC85XX_FEC_NAME		"FEC"
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0

#define CONFIG_ETHPRIME		"MOTO ENET0"

#endif	/* CONFIG_TSEC_ENET */


/*
 * Environment
 */
  #define CFG_ENV_IS_IN_FLASH	1
/*  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)*/
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x10000)
  #define CFG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
  #define CFG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C | CFG_CMD_MII | CFG_CMD_PCI)

#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CFG_LOAD_ADDR	0x1000000	/* default load address */
#define CFG_PROMPT	get_prompt()		/* Monitor Command Prompt */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_ETHADDR   00:E0:0C:40:00:30
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:E0:0C:40:01:30
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:E0:0C:40:02:30
#endif

#define CONFIG_IPADDR    10.196.31.233

#define CONFIG_HOSTNAME		PQ37PC_8540
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_BOOTFILE		vmlinux-2.4.8540.pc

#define CONFIG_SERVERIP  10.196.31.35
#define CONFIG_GATEWAYIP 10.196.31.254
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  1000000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 2	/* -1 disables auto-boot */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS		        \
   "netdev=eth0\0"								\
   "consoledev=ttyS0\0"							\
   "ramdiskaddr=1200000\0"						\
   "ramdiskfile=cramdisk\0"						\
   "hddev=sda3\0"								\
   "hdboot=setenv bootargs root=/dev/$hddev rw console=$consoledev,$baudrate; bootm ff800000\0" \
   "fname=u-boot-1.1.2.8540.pc\0"				\
   "fub=tftp 1000000 $fname;erase ffb80000 ffbfffff;cp.b 1000000 ffb80000 80000"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200" 

#define CONFIG_BOOTCOMMAND  CONFIG_RAMBOOTCOMMAND

#endif	/* __CONFIG_H */
