/*********************************************************************
 *
 *  Copyright (C) 2004  Freescale Semiconductors, Inc.
 *
 ********************************************************************/
/*********************************************************************
 *  FILE: rio_msgs.h
 *
 *  DESCRIPTION :
 *    * NOTES :
 *
 * HISTORY
 * Version    Date     Auth.,Loc.     Comments */
 

typedef struct {
	u32	ommr;
	u32	omsr;
	u32 	eomdqdpar;
	u32	omdqdpar;
	u32	eomsar;
	u32	omsar;
	u32	omdpr;
	u32	omdatr;
	u32	omdcr;
	u32	eomdqepar;
	u32	omdqepar;
	u32	omretcr;
	u32	ommgr;
	u32	ommlr;
	u32	reserved[10];
	u32	immr;
	u32	imsr;
	u32	eimfqdpar;
	u32	imfqdpar;
	u32	eimfqepar;
	u32	imfqepar;
	u32	immirir;
}data_msg_cntrllr;


 
 
/******************************************************************************
Definitions related to the memory mapping.
******************************************************************************/
#define CCSR_BAR 0xe0000000

#define START_OF_RIO_WINDOW 0xc0000000
#define START_OF_MAINT_WINDOW START_OF_RIO_WINDOW
#define LCS_BASE  (START_OF_RIO_WINDOW+0x01000000)
#define REMOTEMEMBASE (START_OF_RIO_WINDOW+0x06000000)

#define CCSR_ADDR_ON_RIO 0x01000000
#define MEM_ADDRESS_ON_AGENT 0x01000000

#define ADDRESS_AGENT_IMAGE_FABRIC 0xff800000
#define ADDRESS_AGENT_IMAGE_P2P 0xffc00000

#define MAX_DEVICES_IN_SYSTEM 4
//#define MAX_PORT_ON_SWITCH 16

#define MBYTE 0x100000

#define DOORBELL_RECEIVED 0x10101
#define DB_TIMEOUT 0x202020
#define DB_MISMATCH 0x303030
#define MESSAGE_UNIT_BUSY 0x404040
#define MESSAGE_QUEUE_FULL 0x505050
#define MESSAGE_READ 0x606060
#define INBOUND_QUEUE_EMPTY 0x707070
#define MESSAGE_IN_IBQ 0x808080
#define MSG_TIMEOUT 0x909090
#define MSG_MISMATCH 0xa0a0a0
 

/****************************************************************************
Register and bit definitions
*****************************************************************************/

#define PWIDTH_MASK 0x38000000
#define PWIDTH1L0 0x00000000
#define PWIDTH1L2 0x08000000
#define PWIDTH4 0x10000000


#define RIWAR_TI_PCIX 0x0
#define RIWAR_TI_LOCALMEM 0xF


#define RIWAR_PCIX_READ 		0x4
#define RIWAR_PCIX_WRITE		0x4
#define RIWAR_LOCAL_READ_NOSNOOP 	0x4
#define RIWAR_LOCAL_READ_SNOOP 		0x5
#define RIWAR_LOCAL_READ_ULOCK_L2 	0x7
#define RIWAR_LOCAL_WRITE_NOSNOOP 	0x4
#define RIWAR_LOCAL_WRITE_SNOOP 	0x5
#define RIWAR_LOCAL_WRITE_ALLOC_L2 	0x6
#define RIWAR_LOCAL_WRITE_LOCK_L2 	0x7




#define DMA_CHANNEL_BUSY 0x00000004
#define DMA_CHANNEL_TRANSFER_MODE 0x00000004
#define DMA_DATR_NWRITER 0x00050000
#define DMA_DATR_SNOOP 0x00050000
#define DMA_SATR_NREAD 0x00040000
#define DMA_SATR_SNOOP 0x00050000
#define DMA_CHANNEL_START 0x00000001


#define PRIORITY_LOW	0
#define PRIORITY_MED	1
#define PRIORITY_HIGH	2

#define LOCAL_RIO_TRAINED 0x00000002
#define DEVICE_CONFIG_HOST 0xe0000000

#define RIWBAR_Address_Shift_RIGHT 12
#define SHIFT_RIO_ADDR_TO_LCSBACSR 3
#define SHIFT_BDIDCSR_TO_DEVICEID 16

#define BOOT_LOCATION 0x07000000
#define BOOT_OVER_RIO 0x03000000

/******************************************************************************
Default register settings
******************************************************************************/
#define LAWAR_DEFAULTS 0x80c0001B
#define AGENT_BOOTING_LAWBAR 0x000ff000
#define AGENT_BOOTING_LAWAR 0x80c00017
#define AGENT_BOOTING_PGCCSR 0x40000000
#define AGENT_BOOTING_EEBPCR 0x01000000


//#define AGENT_BOOTING_ROWTAR ((1 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask)

#define HOST_BOOTING_RIWAR ((0x01 << RIW_En_Shift)  & RIW_En_Mask) \
  |((RIWAR_TI_LOCALMEM << RIW_TgtInt_Shift) & RIW_TgtInt_Mask)\
  |((RIWAR_LOCAL_READ_SNOOP << RIW_ReadTType_Shift) & RIW_ReadTType_Mask)\
  |((LAWAR_SIZE_4M << RIW_WindSize_Shift) & RIW_WindSize_Mask)

#define HOST_BOOTING_FABRIC_RIWTAR (ADDRESS_AGENT_IMAGE_FABRIC>>12)
#define HOST_BOOTING_P2P_RIWTAR (ADDRESS_AGENT_IMAGE_P2P >>12)
#define HOST_BOOTING_RIWBAR 0x000ffc00
#define AGENT_RIWTAR_DEFAULTS (MEM_ADDRESS_ON_AGENT>>12)

#define ROWAR_MAINT_DEFAULTS ((0x01 << ROW_En_Shift)  & ROW_En_Mask) \
  |((PRIORITY_LOW << ROW_Tflowlvl_Shift) & ROW_Tflowlvl_Mask)\
  | ((RIO_MREAD << ROW_ReadTType_Shift) & ROW_ReadTType_Mask)\
  | ((RIO_MWRITE << ROW_WriteTType_Shift) & ROW_WriteTType_Mask)\
  | ((LAWAR_SIZE_1M << ROW_WindSize_Shift) & ROW_WindSize_Mask)

#define ROWAR_IO_DEFAULTS ((0x01 << ROW_En_Shift)  & ROW_En_Mask) \
  |((PRIORITY_LOW << ROW_Tflowlvl_Shift) & ROW_Tflowlvl_Mask)\
  | ((RIO_NREAD << ROW_ReadTType_Shift) & ROW_ReadTType_Mask)\
  | ((RIO_NWRITE << ROW_WriteTType_Shift) & ROW_WriteTType_Mask)\
  | ((LAWAR_SIZE_16M << ROW_WindSize_Shift) & ROW_WindSize_Mask)

#define ROWAR_CCSR_DEFAULTS ((0x01 << ROW_En_Shift)  & ROW_En_Mask) \
  |((PRIORITY_LOW << ROW_Tflowlvl_Shift) & ROW_Tflowlvl_Mask)\
  | ((RIO_NREAD << ROW_ReadTType_Shift) & ROW_ReadTType_Mask)\
  | ((RIO_NWRITE << ROW_WriteTType_Shift) & ROW_WriteTType_Mask)\
  | ((LAWAR_SIZE_8M << ROW_WindSize_Shift) & ROW_WindSize_Mask)\

#define AGENT_RIWAR_DEFAULTS ((0x01 << RIW_En_Shift)  & RIW_En_Mask) \
  |((RIWAR_TI_LOCALMEM << RIW_TgtInt_Shift) & RIW_TgtInt_Mask)\
  |((RIWAR_LOCAL_READ_SNOOP << RIW_ReadTType_Shift) & RIW_ReadTType_Mask)\
  |((RIWAR_LOCAL_WRITE_SNOOP << RIW_WriteTType_Shift) & RIW_WriteTType_Mask)\
  |((LAWAR_SIZE_4M << RIW_WindSize_Shift) & RIW_WindSize_Mask)

#define HOST_RIWAR_DEFAULTS AGENT_RIWAR_DEFAULTS
#define HOST_RIWTAR_DEFAULTS AGENT_RIWTAR_DEFAULTS
//#define RIO_IO_DEV2_BAR ((RIO_IO_DEVICE2_ADDR) >> RIWBAR_Address_Shift_RIGHT)
//#define RIO_IO_DEV3_BAR ((RIO_IO_DEVICE3_ADDR) >> RIWBAR_Address_Shift_RIGHT)
//#define RIO_IO_DEV4_BAR ((RIO_IO_DEVICE4_ADDR) >> RIWBAR_Address_Shift_RIGHT)
//#define RIO_IO_DEV1_TAR ((1 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask)

//#define RIO_IO_DEV2_TAR ((2 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask)

//#define RIO_IO_DEV3_TAR ((3 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask)

//#define RIO_IO_DEV4_TAR ((4 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask)

/*#define RIO_CCSR_DEV1_TAR ((1 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask) \
  | ((CCSR_ADDR_ON_RIO >> 12) & ROW_TA_Mask)

#define RIO_CCSR_DEV2_TAR ((2 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask) \
  | ((CCSR_ADDR_ON_RIO >> 12) & ROW_TA_Mask)

#define RIO_CCSR_DEV3_TAR ((3 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask) \
  | ((CCSR_ADDR_ON_RIO >> 12) & ROW_TA_Mask)

#define RIO_CCSR_DEV4_TAR ((4 << ROW_DEV_ID_Shift) & ROW_DEV_ID_Mask) \
  | ((CCSR_ADDR_ON_RIO >> 12) & ROW_TA_Mask)
*/
/******************************************************************************
TSI500 Definitions
******************************************************************************/
//#define SWITCH_ROUTING_VALUE 0xfff3210f
//#define TSI500_PORT_TRAINED 0xff800800
//#define TSI568_DIDCAR_VALUE 0x0568000D
#define P0_ERR_STATUS_OFFSET 0x158
#define P0_CTL_OFFSET 0x15c
#define TSI568_PORT_STRIDE 0x20
#define RIO_ROUTE_CFG_DESTID 0x70
#define RIO_ROUTE_CFG_PORT 0x74
#define TSI568_PORTOK_BIT 0x02
#define TSI568_INIT_PWIDTH_MASK 0x38000000
#define TSI568_INIT_PWIDTH_1L0 0x00000000
#define TSI568_INIT_PWIDTH_1L2 0x08000000
#define TSI568_INIT_PWIDTH_4 0x10000000
#define TSI568_SW_PORT 0x14

/*#define TSI500_P0_OFFSET 0x10000
#define TSI500_P1_OFFSET 0x30000
#define TSI500_P2_OFFSET 0x50000
#define TSI500_P3_OFFSET 0x70000
#define TSI500_TRN_STAT 0x68
#define TSI500_ROUTE0 0xa00
#define TSI500_INBOUND_PKT_COUNT 0x918
#define TSI500_IB_READ_PRIO0 0x91c
#define TSI500_IB_READ_PRIO1 0x920
#define TSI500_IB_READ_PRIO2 0x924
#define TSI500_IB_READ_PRIO3 0x928
#define TSI500_IB_WRITE_PRIO0 0x92c
#define TSI500_IB_WRITE_PRIO1 0x930
#define TSI500_IB_WRITE_PRIO2 0x944
#define TSI500_IB_WRITE_PRIO3 0x938
#define TSI500_NONRECOV 0xE00
#define TSI500_RECOVERABLE 0xE08
#define TSI500_IB_ERR3 0x990
#define TSI500_OB_ERR1 0x82c
#define TSI500_DESTID_248_LKUP 0xa7C
#define ROUTE_ALL_TO_PORT0 0x00000000
#define ROUTE_ALL_TO_PORT1 0x11111111
#define ROUTE_ALL_TO_PORT2 0x22222222
#define ROUTE_ALL_TO_PORT3 0x33333333
*/
/******************************************************************************
RapidIO Definitions
******************************************************************************/
#define RIO_DIDCAR_OFFSET 0x0
#define RIO_HOSTLOCK_OFFSET 0x68
#define RIO_BDIDCSR_OFFSET 0x60
#define RIO_LCSBACSR_OFFSET 0x5c

#define MPC8548_DIDCAR_VALUE 0x00120002

#define HBDIDLCSR_NOT_LOCKED 0x0000FFFF

/******************************************************************************
Application specific Definitions
******************************************************************************/

#define FABRIC_SYSTEM 0
#define P2P_SYSTEM 1


#define MAX_TRANSFER_BYTES (64 * 1024)
#define MAX_TRANSFER_U32 MAX_TRANSFER_BYTES>>2


#define SUCCESS 0
#define RIO_NOT_TRAINED 101
#define UNKNOWN_DEVICE 102
#define ROUTING_NOT_UPDATED 103
#define NOT_ON_BOOT_PROCESSOR 104
#define NOT_HOST_PROCESSOR 105
#define TEST_FAILED


#define MASK_DOUBLEWORD_ALIGNED 0xFFFFFFF8
#define BOTTOM_BYTE_ONLY_MASK 0x000000FF

