/*
 * (C) Copyright 2002-2004
 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
 *
 * Copyright (C) 2003 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 * Modified to work with AMD flashes
 *
 * Copyright (C) 2004
 * Ed Okerson
 * Modified to work with little-endian systems.
 *
 * Copyright (C) 2004
 * York Sun
 * Modified to support 8-bit port and 32-bit chip, not verified
 * Modified to support polling DQ7 and DQ6 for AMD flash
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * It's originally a CFI flash driver. Specifications for mpc85xxsk are made.
 *
 * History
 * 01/20/2004 - combined variants of original driver.
 * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
 * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
 * 01/27/2004 - Little endian support Ed Okerson
 * 10/26/2004 - Revised to support polling DQ7 and DQ6 for AMD flash
 *              and to support 8-bit port width on 8-bit chip
 * 				and 32/64-bit port width on 32-bit chip (not verified) by York Sun
 * 				According to AMD technical support: It is a good practice
 *              to the use exact where data is being written to when using
 *              "DQ6" method, even though in theory you don't have to.
 * 03/03/2005 - Top boot and Byte mode in Am29LV320D
 * 04/03/2005 - Remap of OR0 and BR0 in mpc85xx according to real size. (Find if CONFIG_MPC85xx)
 * 14/03/2005 - Device ID for MPC85xxPC added.
 * - Added the combinations of addresses of flash for MCP85xxPC
 *
 * Tested Architectures
 * Port Width  Chip Width    # of banks	   Flash Chip  Board
 * 32	       16	     1		   28F128J3    seranoa/eagle
 * 64	       16	     1		   28F128J3    seranoa/falcon
 * 16          16            2             AM29LV641DH MPC8555CDS rev 1.0
 * 16          16            2             AM29LV641MH MPC8555CDS rev 1.0
 * 8	       8	     2		   Am29LV320D  MPC85xxSK rev A & B
 *
 */

/* The DEBUG define must be before common to enable debugging */
#undef DEBUG
#undef PQ37PC_DEBUG
#ifdef PQ37PC_DEBUG
	#define debug(arg...) printf(arg)
#else
	#define debug(arg...)
#endif

#define POLLING_AMD_DQ6
#ifndef POLLING_AMD_DQ6
#define POLLING_AMD_DQ7		/* To use polling DQ7 instead of DQ6 for AMD algorithm */
#endif

#include <common.h>
#include <asm/processor.h>
#include <asm/byteorder.h>
#include <linux/byteorder/swab.h>

/*
 * This file implements a Common Flash Interface (CFI) driver for U-Boot.
 * The width of the port and the width of the chips are determined at initialization.
 * These widths are used to calculate the address for access CFI data structures.
 * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
 *
 * References
 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
 *
 * TODO
 *
 * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
 * Table (ALT) to determine if protection is available
 *
 * Add support for other command sets Use the PRI and ALT to determine command set
 * Verify erase and program timeouts.
 */

#ifndef CFG_FLASH_BANKS_LIST
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#endif

#define FLASH_CMD_CFI			0x98
#define FLASH_CMD_READ_ID		0x90
#define FLASH_CMD_RESET			0xff
#define FLASH_CMD_BLOCK_ERASE		0x20
#define FLASH_CMD_ERASE_CONFIRM		0xD0
#define FLASH_CMD_WRITE			0x40
#define FLASH_CMD_PROTECT		0x60
#define FLASH_CMD_PROTECT_SET		0x01
#define FLASH_CMD_PROTECT_CLEAR		0xD0
#define FLASH_CMD_CLEAR_STATUS		0x50
#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0

#define FLASH_STATUS_DONE		0x80
#define FLASH_STATUS_ESS		0x40
#define FLASH_STATUS_ECLBS		0x20
#define FLASH_STATUS_PSLBS		0x10
#define FLASH_STATUS_VPENS		0x08
#define FLASH_STATUS_PSS		0x04
#define FLASH_STATUS_DPS		0x02
#define FLASH_STATUS_R			0x01
#define FLASH_STATUS_PROTECT		0x01

#define AMD_CMD_RESET			0xF0
#define AMD_CMD_WRITE			0xA0
#define AMD_CMD_ERASE_START		0x80
#define AMD_CMD_ERASE_SECTOR		0x30
#define AMD_CMD_UNLOCK_START		0xAA
#define AMD_CMD_UNLOCK_ACK		0x55
#define AMD_CMD_AUTOSELECT		0x90

#define AMD_DQ7				0x80
#define AMD_DQ5				0x20
#define AMD_STATUS_TIMEOUT		0x20

#define AMD_STATUS_TOGGLE		0x40
#define AMD_STATUS_ERROR		0x20
#define AMD_ADDR_ERASE_START		0x555
#define AMD_ADDR_START			0x555
#define AMD_ADDR_ACK			0x2AA
/* For byte mode */
#define AMD_ADDR_ERASE_START_BYTE	0xAAA
#define AMD_ADDR_START_BYTE			0xAAA
#define AMD_ADDR_ACK_BYTE			0x555

#define FLASH_OFFSET_CFI		0x55
#define FLASH_OFFSET_CFI_RESP		0x10
#define FLASH_OFFSET_PRIMARY_VENDOR	0x13
#define FLASH_OFFSET_WTOUT		0x1F
#define FLASH_OFFSET_WBTOUT		0x20
#define FLASH_OFFSET_ETOUT		0x21
#define FLASH_OFFSET_CETOUT		0x22
#define FLASH_OFFSET_WMAX_TOUT		0x23
#define FLASH_OFFSET_WBMAX_TOUT		0x24
#define FLASH_OFFSET_EMAX_TOUT		0x25
#define FLASH_OFFSET_CEMAX_TOUT		0x26
#define FLASH_OFFSET_SIZE		0x27
#define FLASH_OFFSET_INTERFACE		0x28
#define FLASH_OFFSET_BUFFER_SIZE	0x2A
#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
#define FLASH_OFFSET_ERASE_REGIONS	0x2D
#define FLASH_OFFSET_PROTECT		0x02
#define FLASH_OFFSET_USER_PROTECTION	0x85
#define FLASH_OFFSET_INTEL_PROTECTION	0x81
#define FLASH_OFFSET_AMD_BOOT_FLAG	0x4F


#define FLASH_MAN_CFI			0x01000000

#define CFI_CMDSET_NONE		    0
#define CFI_CMDSET_INTEL_EXTENDED   1
#define CFI_CMDSET_AMD_STANDARD	    2
#define CFI_CMDSET_INTEL_STANDARD   3
#define CFI_CMDSET_AMD_EXTENDED	    4
#define CFI_CMDSET_MITSU_STANDARD   256
#define CFI_CMDSET_MITSU_EXTENDED   257
#define CFI_CMDSET_SST		    258

#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
# undef  FLASH_CMD_RESET
# define FLASH_CMD_RESET                AMD_CMD_RESET /* use AMD-Reset instead */
#endif

/* Mask for Device id read */
#define FLASH_DEVICE_ID_MASK 0xFF
#define AMD_ID_LV081D 0x38
#define AMD_ID_LV065M_2 0x13	/* 2nd ID for AM29LV065M at 0x0E */

#define FLASH_AMLV081D 0x0020
#define FLASH_AMLV065M 0x00AD

typedef union {
	unsigned char c;
	unsigned short w;
	unsigned long l;
	unsigned long long ll;
} cfiword_t;

typedef union {
	volatile unsigned char *cp;
	volatile unsigned short *wp;
	volatile unsigned long *lp;
	volatile unsigned long long *llp;
} cfiptr_t;

#define NUM_ERASE_REGIONS 4

static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;

flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	  */

/*-----------------------------------------------------------------------
 * Functions
 */

typedef unsigned long flash_sect_t;

static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
static int flash_isequal (flash_info_t * info, cfiptr_t cptr, uchar cmd);
static int flash_isset (flash_info_t * info, cfiptr_t cptr, uchar cmd);
static int flash_toggle (flash_info_t * info, cfiptr_t cptr, uchar cmd);
static int flash_detect_cfi (flash_info_t * info);
static ulong flash_get_size (ulong base, int banknum);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int Data_Polling_Check(flash_info_t * info, cfiptr_t cptr, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, cfiptr_t cptr, cfiword_t cword, ulong tout, char *prompt);
#ifdef CFG_FLASH_USE_BUFFER_WRITE
static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
#endif


/*-----------------------------------------------------------------------
 * create an address based on the offset and the port width
 */
inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
{
	return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
}


#ifdef DEBUG
/*-----------------------------------------------------------------------
 * Debug support
 */
void print_longlong (char *str, unsigned long long data)
{
	int i;
	char *cp;

	cp = (unsigned char *) &data;
	for (i = 0; i < 8; i++)
		sprintf (&str[i * 2], "%2.2x", *cp++);
}
static void flash_printqry (flash_info_t * info, flash_sect_t sect)
{
	cfiptr_t cptr;
	int x, y;

	for (x = 0; x < 0x40; x += 16 / info->portwidth) {
		cptr.cp =
			flash_make_addr (info, sect,
					 x + FLASH_OFFSET_CFI_RESP);
		debug ("%p : ", cptr.cp);
		for (y = 0; y < 16; y++) {
			debug ("%2.2x ", cptr.cp[y]);
		}
		debug (" ");
		for (y = 0; y < 16; y++) {
			if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
				debug ("%c", cptr.cp[y]);
			} else {
				debug (".");
			}
		}
		debug ("\n");
	}
}
#endif


/*-----------------------------------------------------------------------
 * read a character at a port width address
 */
inline uchar flash_read_uchar (flash_info_t * info, uint offset)
{
	uchar *cp;

	cp = flash_make_addr (info, 0, offset);
#if defined(__LITTLE_ENDIAN)
	return (cp[0]);
#else
	return (cp[info->portwidth - 1]);
#endif
}

/*-----------------------------------------------------------------------
 * read a short word by swapping for ppc format.
 */
ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
{
	uchar *addr;
	ushort retval;

#ifdef DEBUG
	int x;
#endif
	addr = flash_make_addr (info, sect, offset);

#ifdef DEBUG
	debug ("ushort addr is at %p info->portwidth = %d\n", addr,
	       info->portwidth);
	for (x = 0; x < 2 * info->portwidth; x++) {
		debug ("addr[%x] = 0x%x\n", x, addr[x]);
	}
#endif
#if defined(__LITTLE_ENDIAN)
	retval = ((addr[(info->portwidth)] << 8) | addr[0]);
#else
	retval = ((addr[(2 * info->portwidth) - 1] << 8) |
		  addr[info->portwidth - 1]);
#endif

	debug ("retval = 0x%x\n", retval);
	return retval;
}

/*-----------------------------------------------------------------------
 * read a long word by picking the least significant byte of each maiximum
 * port size word. Swap for ppc format.
 */
ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
{
	uchar *addr;
	ulong retval;

#ifdef DEBUG
	int x;
#endif
	addr = flash_make_addr (info, sect, offset);

#ifdef DEBUG
	debug ("long addr is at %p info->portwidth = %d\n", addr,
	       info->portwidth);
	for (x = 0; x < 4 * info->portwidth; x++) {
		debug ("addr[%x] = 0x%x\n", x, addr[x]);
	}
#endif
#if defined(__LITTLE_ENDIAN)
	retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
		(addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
#else
	retval = (addr[(2 * info->portwidth) - 1] << 24) |
		(addr[(info->portwidth) - 1] << 16) |
		(addr[(4 * info->portwidth) - 1] << 8) |
		addr[(3 * info->portwidth) - 1];
#endif
	return retval;
}

/*-----------------------------------------------------------------------
 */
unsigned char boot_flag = 0xffff;
unsigned long flash_init (void)
{
	unsigned long size = 0;
	int i, j, k,e;
	flash_sect_t sect_cnt;
	unsigned long sector;
	unsigned long temp = 0;
	unsigned long tmp[NUM_ERASE_REGIONS];
	int erase_region_size;
	int erase_region_count;
	cfiptr_t cptr;
	int size_ratio;
	uchar num_erase_regions = 0;

	/* Init: no FLASHes known */
	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i){
		flash_info[i].flash_id = FLASH_UNKNOWN;
		size += flash_info[i].size = flash_get_size(bank_base[i], i);
		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
			printf ("## Unknown FLASH on Bank %d at 0x%08lx - Size = 0x%08lx = %ld MB\n",
				i, bank_base[j], flash_info[i].size, flash_info[i].size << 20);
		}
		else{
		size_ratio = flash_info[i].portwidth / flash_info[i].chipwidth;
		debug ("flash_init: size_ratio %d port %d bits chip %d bits\n",
		       size_ratio, flash_info[i].portwidth << CFI_FLASH_SHIFT_WIDTH,
		       flash_info[i].chipwidth << CFI_FLASH_SHIFT_WIDTH);
		       
		/* if the chip is x8/x16 reduce the ratio by half */
		if ((flash_info[i].interface == FLASH_CFI_X8X16)
		    && (flash_info[i].chipwidth == FLASH_CFI_BY8)) {
			size_ratio >>= 1;
		}
		
		flash_info[i].size *= size_ratio;		
				
		if ((boot_flag == 0) || (boot_flag == 1)){					
/*			flash_write_cmd (&flash_info[i], 0, 0, flash_info[i].cmd_reset);*/
			flash_write_cmd (&flash_info[i], 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
			num_erase_regions = flash_read_uchar (&flash_info[i], FLASH_OFFSET_NUM_ERASE_REGIONS);
		} else if (boot_flag == 2)
			num_erase_regions = 1;

		for (j = 0; j < num_erase_regions; j++)
		{
			if (boot_flag == 1)
			{
				tmp[j] = flash_read_long (&flash_info[i], 0, FLASH_OFFSET_ERASE_REGIONS + (num_erase_regions - 1 - j) * 4);
				debug("flash_init: tmp[%d] = %d\n", j, tmp[j]);
			}
			else if (boot_flag == 0)
			{				
				tmp[j] = flash_read_long (&flash_info[i], 0, FLASH_OFFSET_ERASE_REGIONS + j * 4);
				debug("flash_init: tmp[%d] = %d\n", j, tmp[j]);
			}
			else if (boot_flag == 2)
				tmp[j] = 0x000f0100;
					
			if (j > NUM_ERASE_REGIONS)
			{
				printf ("flash_init: %d erase regions found, only %d used\n",
						num_erase_regions, NUM_ERASE_REGIONS);
				break;
			}
			
		}	
		
		debug ("flash_init: found %d erase regions\n", num_erase_regions);
		
  		if ((boot_flag == 0) || (boot_flag == 1))
			flash_write_cmd (&flash_info[i], 0, 0, flash_info[i].cmd_reset);
		
		if ((flash_info[i].interface == FLASH_CFI_X8X16) && (flash_info[i].chipwidth == FLASH_CFI_BY8)) {
			flash_info[i].portwidth >>= 1;	/* XXX - Need to test on x8/x16 in parallel. */
		}
		
		flash_info[i].start[0] = 0xFFFFFFFF;
		for (k=0; k <= i; k++){
			flash_info[i].start[0] -= flash_info[k].size;
		}
		flash_info[i].start[0] += 1;		
		debug("flash_init: flash_info[%d] base is %x\n", i, flash_info[i].start[0]);
		
		{
		static volatile immap_t		*immap  = (immap_t *)CFG_IMMR;
  		static volatile unsigned int * memctl;
  		static volatile unsigned int tempctl;

  		memctl = &immap->im_lbc;
 		
  		/* Set BRn */
  		tempctl = *(memctl + i * 2);
  		tempctl &= 0x7EF;
  		tempctl |= (flash_info[i].start[0] & 0xFFFF8000) | ((flash_info[i].portwidth & 0x3) << 11);
  		*(memctl + i * 2) = tempctl;
  		
  		/* Set ORn */
  		tempctl = *(memctl + i * 2 + 1);
  		tempctl &= 0x1FFF;
  		tempctl |= 0x6000;
  		tempctl |= (~(flash_info[i].size-1) & 0xFFFF8000);
  		*(memctl + i * 2 + 1) = tempctl;
  		
  		asm("msync");
		}		
		
		sector = flash_info[i].start[0];
		sect_cnt = 0;
		for (j = 0; j < num_erase_regions; j++)
		{
#if 0
			if (boot_flag == 1)
				temp = flash_read_long (&flash_info[i], 0, (FLASH_OFFSET_ERASE_REGIONS + (num_erase_regions - 1 - j) * 4));
			else if (boot_flag == 0)
				temp = flash_read_long (&flash_info[i], 0, FLASH_OFFSET_ERASE_REGIONS + j * 4);
			else if (boot_flag == 2)
				temp = 0x000f0100;
#endif					
			if (j > NUM_ERASE_REGIONS) {
				printf ("%d erase regions found, only %d used\n",
					num_erase_regions, NUM_ERASE_REGIONS);
				break;
			}
			erase_region_size = (tmp[j] & 0xffff) ? ((tmp[j] & 0xffff) * 256) : 128;
			tmp[j] >>= 16;
			erase_region_count = (tmp[j] & 0xffff) + 1;
			debug ("flash_init: erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size);
			debug ("flash_init: sect_cnt = %d\n", sect_cnt);
			for (e=0; e < erase_region_count; e++, sect_cnt++)
			{
				flash_info[i].start[sect_cnt] = sector;
				debug("flash_init: flash_info[%d].start[%d]  0x%x\n", i, sect_cnt, flash_info[i].start[sect_cnt]);
				sector += (erase_region_size * size_ratio);
				/*
				 * Only read protection status from supported devices (intel...)
				 */
				switch (flash_info[i].vendor)
				{
					case CFI_CMDSET_INTEL_EXTENDED:
					case CFI_CMDSET_INTEL_STANDARD:
						cptr.cp = flash_make_addr(&flash_info[i],
								  sect_cnt,
								  FLASH_OFFSET_PROTECT);
						flash_info[i].protect[sect_cnt] =
									flash_isset (&flash_info[i],
							     	cptr,
							     	FLASH_STATUS_PROTECT);
					break;
				default:
					flash_info[i].protect[sect_cnt] = 0; /* default: not protected */
				}
			}
		}
		
		flash_info[i].sector_count = sect_cnt;
		switch (flash_info[i].vendor){
			case CFI_CMDSET_INTEL_STANDARD:
			case CFI_CMDSET_INTEL_EXTENDED:
				if (i == 0)
					printf("Bank %d -- ", i);
				else printf("       Bank %d -- ", i);
					printf ("Intel Flash (%d x %d) %ld MB\n",(flash_info[i].portwidth << 3), (flash_info[i].chipwidth << 3), flash_info[i].size >> 20);
				break;
			case CFI_CMDSET_AMD_STANDARD:
			case CFI_CMDSET_AMD_EXTENDED:
				if (i == 0)
					printf("Bank %d -- ", i);
				else printf("       Bank %d -- ", i);
					switch (flash_info[i].flash_id & FLASH_DEVICE_ID_MASK){
					case (FLASH_AMLV081D & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV081B");
						break;
					case (FLASH_AM320T & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV320T ");
						break;
					case (FLASH_AM320B & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV320B ");
						break;
					//case (FLASH_AMDLV016C & FLASH_DEVICE_ID_MASK):
						//printf ("AMD AM29LV016C/07D ");
						//break;
					case (FLASH_AMDLV033C & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV330C ");
						break;
					case (FLASH_AMDLV065D & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV065D ");
						break;
					case (FLASH_AM800T & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV800T ");
						break;
					case (FLASH_AM800B & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV800B ");
						break;
					case (FLASH_AM160T & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV320T ");
						break;
					case (FLASH_AM160B & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV160DB ");
						break;
					case (FLASH_AMLV320B & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV320MB");
						break;
					case (FLASH_AMLV320T & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV320MT ");
						break;
					case (FLASH_AMLV065M & FLASH_DEVICE_ID_MASK):
						printf ("AMD AM29LV065MU ");					
						break;
					//case (FLASH_S29GL064MB & FLASH_DEVICE_ID_MASK):
						//printf ("AMD S29GL064MB ");
						//break;
					//case (FLASH_S29GL064MT & FLASH_DEVICE_ID_MASK):
						//printf ("AMD S29GL064MT ");
						//break;
					case (FLASH_S29GL064M & FLASH_DEVICE_ID_MASK):
						printf ("AMD S29GL064M ");
						break;
					//case (FLASH_S29GL032MB & FLASH_DEVICE_ID_MASK):
						//printf ("AMD S29GL036MB ");
						//break;
					//case  (FLASH_S29GL032MT & FLASH_DEVICE_ID_MASK):
						//printf ("AMD S29GL036MT ");
						//break;
					default:
						printf ("AMD Flash ");
						break;
					}
				printf("(%d x %d) %ld MB\n",(flash_info[i].portwidth << 3), (flash_info[i].chipwidth << 3), flash_info[i].size >> 20);
				break;
			default:
				if (i == 0)
					printf("Bank %d -- ", i);
				else printf("       Bank %d -- ", i);
				printf ("CFI conformant Flash (%d x %d) %ld MB\n",(flash_info[i].portwidth << 3), (flash_info[i].chipwidth << 3), flash_info[i].size >> 20);
				break;
			}
		}
	}

	/* Monitor protection ON by default */
#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
	flash_protect (FLAG_PROTECT_SET,
		       CFG_MONITOR_BASE,
		       CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
		       &flash_info[0]);
#endif

	/* Environment protection ON by default */
#ifdef CFG_ENV_IS_IN_FLASH
	flash_protect (FLAG_PROTECT_SET,
		       CFG_ENV_ADDR,
		       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
		       &flash_info[0]);
#endif

	/* Redundant environment protection ON by default */
#ifdef CFG_ENV_ADDR_REDUND
	flash_protect (FLAG_PROTECT_SET,
		       CFG_ENV_ADDR_REDUND,
		       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
		       &flash_info[0]);
#endif
	return (size);
}

/*-----------------------------------------------------------------------
 */
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
	int rcode = 0;
	int prot;
	cfiword_t cword;
	cfiptr_t cptr;
	flash_sect_t sect;

	cword.c = 0xff;

/*	if (info->flash_id != FLASH_MAN_CFI) {*/
	if (info->flash_id == FLASH_UNKNOWN) {
		puts ("Can't erase unknown flash type - aborted\n");
		return 1;
	}
	if ((s_first < 0) || (s_first > s_last)) {
		puts ("- no sectors to erase\n");
		return 1;
	}

	prot = 0;
	for (sect = s_first; sect <= s_last; ++sect) {
		if (info->protect[sect]) {
			prot++;
		}
	}
	if (prot) {
		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
	} else {
		putc ('\n');
	}


	for (sect = s_first; sect <= s_last; sect++) {
		if (info->protect[sect] == 0) { /* not protected */
			switch (info->vendor) {
			case CFI_CMDSET_INTEL_STANDARD:
			case CFI_CMDSET_INTEL_EXTENDED:
				flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
				flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
				flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
				break;
			case CFI_CMDSET_AMD_STANDARD:
			case CFI_CMDSET_AMD_EXTENDED:
				flash_unlock_seq (info, sect);
				switch(info->chipwidth){
				case FLASH_CFI_BY8:
					flash_write_cmd (info, sect, AMD_ADDR_ERASE_START_BYTE, AMD_CMD_ERASE_START);
					break;
				default:
					flash_write_cmd (info, sect, AMD_ADDR_ERASE_START, AMD_CMD_ERASE_START);
					break;
				}
				flash_unlock_seq (info, sect);
				flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
				break;
			default:
				debug ("Unkown flash vendor %d\n",
				       info->vendor);
				break;
			}
			cptr.cp = flash_make_addr(info,sect,0);
			if (flash_full_status_check(info,cptr,cword, info->erase_blk_tout,"erase") ) {
				rcode = 1;
			} 
			else
				putc ('.');
		}
	}
	puts (" done\n");
	return rcode;
}

/*-----------------------------------------------------------------------
 */
void flash_print_info (flash_info_t * info)
{
	int i;

/*	if (info->flash_id != FLASH_MAN_CFI) {*/

	if (info->flash_id == FLASH_UNKNOWN) {
		puts ("missing or unknown FLASH type\n");
		return;
	}
	
	if ((info->flash_id & FLASH_DEVICE_ID_MASK) == (FLASH_AMLV081D & FLASH_DEVICE_ID_MASK))
		puts ("FLASH AMLV081D ");
	else
		puts ("CFI compatible FLASH ");
		
	printf ("(%d bit port width with %d bit chip width)\n", (info->portwidth << 3), (info->chipwidth << 3));
	printf ("Command set is ");
	switch (info->vendor) {
	case CFI_CMDSET_INTEL_EXTENDED:
		printf ("Intel/Sharp extended\n");
		break;
	case CFI_CMDSET_AMD_STANDARD:
		printf ("AMD/Fujitsu standard. ");
#ifdef POLLING_AMD_DQ7
		printf ("Driver is polling DQ7 for status checking.\n");
#else
		printf ("Driver is polling DQ6 for status checking.\n");
#endif
		break;
	case CFI_CMDSET_INTEL_STANDARD:
		printf ("Intel/Sharp standard\n");
		break;
	case CFI_CMDSET_AMD_EXTENDED:
		printf ("AMD/Fujitsu extended\n");
#ifdef POLLING_AMD_DQ7
		printf ("Driver is polling DQ7 for status checking.\n");
#else
		printf ("Driver is polling DQ6 for status checking.\n");
#endif
		break;
	case CFI_CMDSET_MITSU_STANDARD:
		printf ("Mitsubishi standard\n");
		break;
	case CFI_CMDSET_MITSU_EXTENDED:
		printf ("Mitsubishi extendend\n");
		break;
	default:
		printf ("Not defined\n");
		break;
	}
	printf ("  Size: %ld MB in %d Sectors\n",
		info->size >> 20, info->sector_count);
	if ((info->flash_id & FLASH_DEVICE_ID_MASK) != (FLASH_AMLV081D & FLASH_DEVICE_ID_MASK))	
		printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
			info->erase_blk_tout,
			info->write_tout,
			info->buffer_write_tout,
			info->buffer_size);

	puts ("  Sector Start Addresses:");
	for (i = 0; i < info->sector_count; ++i) {
#ifdef CFG_FLASH_EMPTY_INFO
		int k;
		int size;
		int erased;
		volatile unsigned long *flash;

		/*
		 * Check if whole sector is erased
		 */
		if (i != (info->sector_count - 1))
			size = info->start[i + 1] - info->start[i];
		else
			size = info->start[0] + info->size - info->start[i];
		erased = 1;
		flash = (volatile unsigned long *) info->start[i];
		size = size >> 2;	/* divide by 4 for longword access */
		for (k = 0; k < size; k++) {
			if (*flash++ != 0xffffffff) {
				erased = 0;
				break;
			}
		}

		if ((i % 5) == 0)
			printf ("\n");
		/* print empty and read-only info */
		printf (" %08lX%s%s",
			info->start[i],
			erased ? " E" : "  ",
			info->protect[i] ? "RO " : "   ");
#else
		if ((i % 5) == 0)
			printf ("\n   ");
		printf (" %08lX%s",
			info->start[i], info->protect[i] ? " (RO)  " : "     ");
#endif
	}
	putc ('\n');
	return;
}

/*-----------------------------------------------------------------------
 * Copy memory to flash, returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 */
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
	ulong wp;
	ulong cp;
	int aln;
	cfiword_t cword;
	int i, rc;
	ulong temp,count;
	
	count = cnt;

#ifdef DEBUG
	printf("0x%x, 0x%x, 0x%x\n", *src, addr, cnt);
	printf("size = %d\n",				info->size);			
	printf("sector_count = %d  \n",     info->sector_count);	
	printf("flash_id=0x%x\n",           info->flash_id);		
	printf("portwidth = 0x%x\n",		info->portwidth );
	printf("chipwidth = 0x%x\n",       info->chipwidth);
	printf("buffer_size = 0x%x\n",      info->buffer_size);
	printf("erase_blk_tout = 0x%x\n",   info->erase_blk_tout);
	printf("write_tout = 0x%x\n",       info->write_tout);
	printf("buffer_write_tout= 0x%x\n", info->buffer_write_tout);
	printf("vendor		= 0x%x\n",      info->vendor);
	printf("cmd_reset	= 0x%x\n",      info->cmd_reset);
	printf("interface = 0x%x\n",        info->interface);
#endif




#ifdef CFG_FLASH_USE_BUFFER_WRITE
	int buffered_size;
#endif
	/* get lower aligned address */
	/* get lower aligned address */
	wp = (addr & ~(info->portwidth - 1));

	/* handle unaligned start */
	if ((aln = addr - wp) != 0) {
		cword.l = 0;
		cp = wp;
		for (i = 0; i < aln; ++i, ++cp)
			flash_add_byte (info, &cword, (*(uchar *) cp));

		for (; (i < info->portwidth) && (cnt > 0); i++) {
			flash_add_byte (info, &cword, *src++);
			cnt--;
			cp++;
		}
		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
			flash_add_byte (info, &cword, (*(uchar *) cp));
		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
			return rc;
		wp = cp;
	}

	/* handle the aligned part */
#ifdef CFG_FLASH_USE_BUFFER_WRITE
	buffered_size = (info->portwidth / info->chipwidth);
	buffered_size *= info->buffer_size;
	while (cnt >= info->portwidth) {
		i = buffered_size > cnt ? cnt : buffered_size;
		if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
			return rc;
		i -= (i % info->portwidth);
		wp += i;
		src += i;
		cnt -= i;
	}
#else
	temp = 0;
	printf("\n");
	while (cnt >= info->portwidth) {
		cword.l = 0;
		for (i = 0; i < info->portwidth; i++) {
			flash_add_byte (info, &cword, *src++);
		}
		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
			return rc;
		wp += info->portwidth;
		cnt -= info->portwidth;
                if (((count-cnt)>>10)>temp) {
                        temp=(count-cnt)>>10;
                        printf("\r%d KB",temp);
                }
	}
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
	if (cnt == 0) {
		return (0);
	}

	/*
	 * handle unaligned tail bytes
	 */
	cword.l = 0;
	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
		flash_add_byte (info, &cword, *src++);
		--cnt;
	}
	for (; i < info->portwidth; ++i, ++cp) {
		flash_add_byte (info, &cword, (*(uchar *) cp));
	}

	return flash_write_cfiword (info, wp, cword);
}

/*-----------------------------------------------------------------------
 */
#ifdef CFG_FLASH_PROTECTION

int flash_real_protect (flash_info_t * info, long sector, int prot)
{
	int retcode = 0;

	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
	flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
	if (prot)
		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
	else
		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);

	if ((retcode =
	     flash_full_status_check (info, sector, 0,0,info->erase_blk_tout,
				      prot ? "protect" : "unprotect")) == 0) {

		info->protect[sector] = prot;
		/* Intel's unprotect unprotects all locking */
		if (prot == 0) {
			flash_sect_t i;

			for (i = 0; i < info->sector_count; i++) {
				if (info->protect[i])
					flash_real_protect (info, i, 1);
			}
		}
	}
	return retcode;
}

/*-----------------------------------------------------------------------
 * flash_read_user_serial - read the OneTimeProgramming cells
 */
void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
			     int len)
{
	uchar *src;
	uchar *dst;

	dst = buffer;
	src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
	flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
	memcpy (dst, src + offset, len);
	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
}

/*
 * flash_read_factory_serial - read the device Id from the protection area
 */
void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
				int len)
{
	uchar *src;

	src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
	flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
	memcpy (buffer, src + offset, len);
	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
}

#endif /* CFG_FLASH_PROTECTION */

/*
 * flash_is_busy - check to see if the flash is busy
 * This routine checks the status of the chip and returns true if the chip is busy
 */
static int flash_is_busy (flash_info_t * info, cfiptr_t cptr, cfiword_t cword)
{
	int retval;

	switch (info->vendor) {
	case CFI_CMDSET_INTEL_STANDARD:
	case CFI_CMDSET_INTEL_EXTENDED:
		retval = !flash_isset (info, cptr,  FLASH_STATUS_DONE);
		break;
	case CFI_CMDSET_AMD_STANDARD:
	case CFI_CMDSET_AMD_EXTENDED:
#ifdef POLLING_AMD_DQ7
		retval = Data_Polling_Check (info, cptr, cword);	/* data polling for D7 */
#else
		retval = flash_toggle (info, cptr, AMD_STATUS_TOGGLE);
#endif
		break;
	default:
		retval = 0;
	}
	debug ("flash_is_busy: %d\n", retval);
	return retval;
}


/* ----------------------------------------------------------------------
 * Polling DQ5 for AMD flash
 * Edited by York Sun (yorksun@freescale.com)
 */
static int flash_time_out (flash_info_t * info, cfiptr_t cptr, cfiword_t cword)
{
        int retval;
                                                                                                                 
        switch (info->vendor) {
        case CFI_CMDSET_AMD_STANDARD:
        case CFI_CMDSET_AMD_EXTENDED:
                retval = flash_isset (info, cptr,  AMD_STATUS_TIMEOUT);
                break;
        default:
                retval = 0;
        }
        debug ("flash_time_out: %d\n", retval);
        return retval;
}

/* ----------------------------------------------------------------------
 * Polling DQ7 for AMD flash
 * Edited by York Sun (yorksun@freescale.com)
 */
static int Data_Polling_Check(flash_info_t * info, cfiptr_t cptr, cfiword_t cword)
{
	uchar	read_data=0,polling_data=0;

	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		polling_data= cword.c;
		break;
	case FLASH_CFI_16BIT:
		polling_data=(uchar) (cword.w & 0xff);
		break;
	case FLASH_CFI_32BIT:
		polling_data=(uchar) (cword.l & 0xff);
		break;
	case FLASH_CFI_64BIT:
		polling_data=(uchar) (cword.ll & 0xff);
		break;
	default:
		printf("Error in function %s\n",__FUNCTION__);
	}
	do {
		switch (info->portwidth) {
		case FLASH_CFI_8BIT:
			read_data  = cptr.cp[0];
			break;
		case FLASH_CFI_16BIT:
			read_data  = (uchar) (cptr.wp[0] & 0xff);
			break;
		case FLASH_CFI_32BIT:
			read_data  = (uchar) (cptr.lp[0] & 0xff);
			break;
		case FLASH_CFI_64BIT:
			read_data  = (uchar) (cptr.llp[0] & 0xff);
			break;
		}
		if ((read_data & AMD_DQ7) == (polling_data & AMD_DQ7)) 
			break;
	} while ((read_data & AMD_DQ5) != (uchar) AMD_DQ5);
	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		read_data  = cptr.cp[0];
		break;
	case FLASH_CFI_16BIT:
		read_data  = (uchar) (cptr.wp[0] & 0xff);
		break;
	case FLASH_CFI_32BIT:
		read_data  = (uchar) (cptr.lp[0] & 0xff);
		break;
	case FLASH_CFI_64BIT:
		read_data  = (uchar) (cptr.llp[0] & 0xff);
		break;
	}
	if ((read_data & AMD_DQ7) != (polling_data & AMD_DQ7))
		return ERR_TIMOUT;
	else
		return ERR_OK;
} 

/*-----------------------------------------------------------------------
 *  wait for XSR.7 to be set. Time out with an error if it does not.
 *  This routine does not set the flash to read-array mode.
 *  get_timer does not always work. Polling DQ5 can get the time out info for AMD flash.
 */
static int flash_status_check (flash_info_t * info, cfiptr_t cptr, cfiword_t cword, ulong tout, char *prompt)
{
        ulong start,now;

	/* Wait for command completion */
    start = get_timer (0);
	while (flash_is_busy (info, cptr,cword)) 
	{
		if ((flash_time_out(info,cptr,cword)) || ((now=get_timer (start)) > info->erase_blk_tout * CFG_HZ)) 
		{
			if (flash_is_busy (info, cptr,cword)) 
			{
				printf ("Flash %s timeout at address %lx data %lx\n",prompt, (ulong)cptr.cp,cword.l);
				flash_write_cmd (info, 0, 0, info->cmd_reset);
				return ERR_TIMOUT;
			}
		}
	}
	return ERR_OK;
}

/*-----------------------------------------------------------------------
 * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
 * This routine sets the flash to read-array mode.
 */
static int flash_full_status_check (flash_info_t * info, cfiptr_t cptr, cfiword_t cword, ulong tout, char *prompt)
{
	int retcode;

	retcode = flash_status_check (info, cptr, cword, tout, prompt);
	debug("return = %d\n",retcode);
	switch (info->vendor) {
	case CFI_CMDSET_INTEL_EXTENDED:
	case CFI_CMDSET_INTEL_STANDARD:
		if ((retcode != ERR_OK)
		    && !flash_isequal (info, cptr, FLASH_STATUS_DONE)) {
			retcode = ERR_INVAL;
			printf ("Flash %s error at address %lx\n", prompt,(ulong)cptr.cp);
			if (flash_isset (info, cptr, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
				puts ("Command Sequence Error.\n");
			} else if (flash_isset (info, cptr, FLASH_STATUS_ECLBS)) {
				puts ("Block Erase Error.\n");
				retcode = ERR_NOT_ERASED;
			} else if (flash_isset (info, cptr, FLASH_STATUS_PSLBS)) {
				puts ("Locking Error\n");
			}
			if (flash_isset (info, cptr, FLASH_STATUS_DPS)) {
				puts ("Block locked.\n");
				retcode = ERR_PROTECTED;
			}
			if (flash_isset (info, cptr, FLASH_STATUS_VPENS))
				puts ("Vpp Low Error.\n");
		}
		flash_write_cmd (info, 0,0, FLASH_CMD_RESET);
		break;
	default:
		break;
	}
	debug("return = %d\n",retcode);
	return retcode;
}

/*-----------------------------------------------------------------------
 */
static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
{
#if defined(__LITTLE_ENDIAN)
	unsigned short	w;
	unsigned int	l;
	unsigned long long ll;
#endif

	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		cword->c = c;
		break;
	case FLASH_CFI_16BIT:
#if defined(__LITTLE_ENDIAN)
		w = c;
		w <<= 8;
		cword->w = (cword->w >> 8) | w;
#else
		cword->w = (cword->w << 8) | c;
#endif
		break;
	case FLASH_CFI_32BIT:
#if defined(__LITTLE_ENDIAN)
		l = c;
		l <<= 24;
		cword->l = (cword->l >> 8) | l;
#else
		cword->l = (cword->l << 8) | c;
#endif
		break;
	case FLASH_CFI_64BIT:
#if defined(__LITTLE_ENDIAN)
		ll = c;
		ll <<= 56;
		cword->ll = (cword->ll >> 8) | ll;
#else
		cword->ll = (cword->ll << 8) | c;
#endif
		break;
	}
}


/*-----------------------------------------------------------------------
 * make a proper sized command based on the port and chip widths
 */
static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
{
	int i;

#if defined(__LITTLE_ENDIAN)
	ushort stmpw;
	uint   stmpi;
#endif
	uchar *cp = (uchar *) cmdbuf;
	if (info->chipwidth < FLASH_CFI_BY32) {
		for (i = 0; i < info->portwidth; i++)
			*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
	}
	else {
		ushort *ccp= (ushort  *) cmdbuf;
		ushort cmd_16= cmd + cmd * 256;
		for (i = 0; i< info->portwidth; i=i+2)
			*ccp++= ((i + 2) % info->chipwidth) ? '\0' :cmd_16;
	}
#if defined(__LITTLE_ENDIAN)
	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		break;
	case FLASH_CFI_16BIT:
		stmpw = *(ushort *) cmdbuf;
		*(ushort *) cmdbuf = __swab16 (stmpw);
		break;
	case FLASH_CFI_32BIT:
		stmpi = *(uint *) cmdbuf;
		*(uint *) cmdbuf = __swab32 (stmpi);
		break;
	default:
		puts ("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n");
		break;
	}
#endif
}

/*
 * Write a proper sized command to the correct address
 */
static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
{

	volatile cfiptr_t addr;
	cfiword_t cword;

	addr.cp = flash_make_addr (info, sect, offset);
	flash_make_cmd (info, cmd, &cword);
	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		debug ("fwc: issues cmd %x to addr %p with %x,\nfwc:assuming flash port width 8bit, chip width %d bit\n",\
			cmd, addr.cp, cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
		*addr.cp = cword.c;
		break;
	case FLASH_CFI_16BIT:
		debug ("fwc: issues cmd %x to addr %p with %4.4x,\nfwc:assuming flash port width 16bit, chip width %d bit\n",\
			cmd, addr.wp, cword.w, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
		*addr.wp = cword.w;
		break;
	case FLASH_CFI_32BIT:
		debug ("fwc: issues cmd %x to addr %p with %8.8lx,\nfwc:assuming flash port width 32bit, chip width %d bit\n",\
			cmd, addr.lp, cword.l, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
		*addr.lp = cword.l;
		break;
	case FLASH_CFI_64BIT:
#ifdef DEBUG
		{
			char str[20];

			print_longlong (str, cword.ll);

			debug ("fwc: issues cmd %x to addr %p with %s,\nfwc:assuming flash port width 64 bit, chip width %d bit\n",\
				cmd, addr.llp, str, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
		}
#endif
		*addr.llp = cword.ll;
		break;
	}
}

static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
{
	/* Different AMD_ADDR_START and AMD_ADDR_ACK for word mode and byte mode */
	switch(info->chipwidth){
	case FLASH_CFI_BY8:
		flash_write_cmd (info, sect, AMD_ADDR_START_BYTE, AMD_CMD_UNLOCK_START);
		flash_write_cmd (info, sect, AMD_ADDR_ACK_BYTE, AMD_CMD_UNLOCK_ACK);
		break;
	default:
		flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
		flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
		break;
	}
}

/*-----------------------------------------------------------------------
 */
static int flash_isequal (flash_info_t * info, cfiptr_t cptr, uchar cmd)
{
	cfiword_t cword;
	int retval;

	flash_make_cmd (info, cmd, &cword);

	debug ("flash_isequal: expecting net value is %x(%c) at addr %p,\n", cmd, cmd, cptr.cp);
	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		debug ("flash_isequal: expected read value %x, actual read %x\n", cword.c,cptr.cp[0]);
		retval = (cptr.cp[0] == cword.c);
		break;
	case FLASH_CFI_16BIT:
		debug ("flash_isequal: expected read value %4.4x, actual read %4.4x\n", cword.w,cptr.wp[0]);
		retval = (cptr.wp[0] == cword.w);
		break;
	case FLASH_CFI_32BIT:
		debug ("flash_isequal: expected read value %8.8lx, actual read %8.8lx\n", cword.l,cptr.lp[0]);
		retval = (cptr.lp[0] == cword.l);
		break;
	case FLASH_CFI_64BIT:
#ifdef DEBUG
		{
			char str1[20];
			char str2[20];

			print_longlong (str1, cptr.llp[0]);
			print_longlong (str2, cword.ll);
			debug ("flash_isequal: expected read vaule is %s, actual read %s\n", str2, str1);
		}
#endif
		retval = (cptr.llp[0] == cword.ll);
		break;
	default:
		retval = 0;
		break;
	}
	return retval;
}

/*-----------------------------------------------------------------------
 */
static int flash_isset (flash_info_t * info, cfiptr_t cptr, uchar cmd)
{
	cfiword_t cword;
	int retval;

	flash_make_cmd (info, cmd, &cword);
	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		retval = ((cptr.cp[0] & cword.c) == cword.c);
		break;
	case FLASH_CFI_16BIT:
		retval = ((cptr.wp[0] & cword.w) == cword.w);
		break;
	case FLASH_CFI_32BIT:
		retval = ((cptr.lp[0] & cword.l) == cword.l);
		break;
	case FLASH_CFI_64BIT:
		retval = ((cptr.llp[0] & cword.ll) == cword.ll);
		break;
	default:
		retval = 0;
		break;
	}
	return retval;
}

/*-----------------------------------------------------------------------
 */
static int flash_toggle (flash_info_t * info, cfiptr_t cptr, uchar cmd)
{
	cfiword_t cword;
	int retval;

	flash_make_cmd (info, cmd, &cword);
	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
		break;
	case FLASH_CFI_16BIT:
		retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
		break;
	case FLASH_CFI_32BIT:
		retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
		break;
	case FLASH_CFI_64BIT:
		retval = ((cptr.llp[0] & cword.ll) !=
			  (cptr.llp[0] & cword.ll));
		break;
	default:
		retval = 0;
		break;
	}
	return retval;
}

/*-----------------------------------------------------------------------
 * detect if flash is compatible with the Common Flash Interface (CFI)
 * http://www.jedec.org/download/search/jesd68.pdf
 *
*/
static int flash_detect_cfi (flash_info_t * info)
{
	cfiptr_t cptr1,cptr2,cptr3;
	debug ("Start flash detect cfi\n");

	for (info->portwidth = FLASH_CFI_8BIT;
	     info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
		for (info->chipwidth = FLASH_CFI_BY8;
		     info->chipwidth <= info->portwidth;
		     info->chipwidth <<= 1) {
			cptr1.cp = flash_make_addr(info,0,FLASH_OFFSET_CFI_RESP);
			cptr2.cp = flash_make_addr(info,0,FLASH_OFFSET_CFI_RESP + 1);
			cptr3.cp = flash_make_addr(info,0,FLASH_OFFSET_CFI_RESP + 2);
			flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
			flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
			if (flash_isequal (info, cptr1,'Q')
			    && flash_isequal (info, cptr2, 'R')
			    && flash_isequal (info, cptr3, 'Y')) {
				info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
				debug ("flash detect cfi: device interface is %d\n",
				       info->interface);
				debug ("flash detect cfi: found port %d chip %d ",
				       info->portwidth, info->chipwidth);
				debug ("port %d bits chip %d bits\n",
				       info->portwidth << CFI_FLASH_SHIFT_WIDTH,
				       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
				return 1;
			}
		}
	}
	debug ("flash detect cfi: not found\n");
	return 0;
}

/*
 * The following code cannot be run from FLASH!
 *
 */
static ulong flash_get_size (ulong base, int banknum)
{
	flash_info_t *info = &flash_info[banknum];
	int i, j;
	unsigned long tmp;

	info->start[0] = base;

	if (flash_detect_cfi (info)){
		info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
		debug ("flash_get_size: manufacturer is %d\n", info->vendor);
#ifdef DEBUG
		flash_printqry (info, 0);
#endif
		switch (info->vendor) {
		case CFI_CMDSET_INTEL_STANDARD:
		case CFI_CMDSET_INTEL_EXTENDED:
			info->cmd_reset = FLASH_CMD_RESET;
			break;
		case CFI_CMDSET_AMD_STANDARD:
		case CFI_CMDSET_AMD_EXTENDED:
			info->cmd_reset = AMD_CMD_RESET;
			break;
		default:
			return 0;
		}

		/* Boot Sector flag = 1 if top boot device */
		/* Contrast to the mask for bottom boot sector type FLASH_BTYPE 0x0001 */
		boot_flag = flash_read_uchar (info, FLASH_OFFSET_AMD_BOOT_FLAG) & 1;
		
		/* multiply the size by the number of chips */
		info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE));
		info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
		info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
		info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
		info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
		info->flash_id = FLASH_MAN_CFI;
	}else{
		/* There is one non-CFI Flash in PQ37PC -- AM29LV081 */
		unsigned char vendor = 0;
		info->portwidth = 1;
		info->chipwidth = 1;
		flash_unlock_seq (info, 0);
		flash_write_cmd (info, 0, AMD_ADDR_START_BYTE, AMD_CMD_AUTOSELECT);
		vendor = (unsigned long) flash_read_uchar(info, 0);
		switch (vendor){
		case (AMD_MANUFACT & 0x000000FF):
			info->vendor = CFI_CMDSET_AMD_STANDARD;
			info->cmd_reset = AMD_CMD_RESET;
			break;
		default:
			return 0;
		}
	}			
	flash_write_cmd (info, 0, 0, info->cmd_reset);
	
	switch (info->vendor) {
		case CFI_CMDSET_INTEL_STANDARD:
		case CFI_CMDSET_INTEL_EXTENDED:
			break;
		case CFI_CMDSET_AMD_STANDARD:
		case CFI_CMDSET_AMD_EXTENDED:
			flash_unlock_seq (info, 0);
			flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_AUTOSELECT);
			tmp = (unsigned long) flash_read_uchar(info, 0x1);
			debug("flash_get_size: device is %x\n", tmp);
			switch(tmp){
				case (AMD_ID_LV081D & FLASH_DEVICE_ID_MASK) :	/* A non CFI flash */
					info->flash_id = FLASH_AMLV081D;
					info->size = 0x100000;
					boot_flag = 2;
					break;
				case (AMD_ID_LV320T & FLASH_DEVICE_ID_MASK):
					info->flash_id += FLASH_AM320T;
					break;
				case (AMD_ID_LV320B & FLASH_DEVICE_ID_MASK):
					info->flash_id += FLASH_AM320B;
					break;
				/* The same as AM29LV017D i.e. 0xC8 */
				case AMD_ID_LV016B:
					//info->flash_id += FLASH_AMDLV016C;
					break;
				case AMD_ID_LV033C:
					info->flash_id += FLASH_AMDLV033C;
					break;
				case AMD_ID_LV065D:
					info->flash_id += FLASH_AMDLV065D;
					break;
				case (AMD_ID_LV800T & FLASH_DEVICE_ID_MASK):
					info->flash_id += FLASH_AM800T;
					break;
				case (AMD_ID_LV800B & FLASH_DEVICE_ID_MASK):
					info->flash_id += FLASH_AM800B;
					break;
				case (AMD_ID_LV160T & FLASH_DEVICE_ID_MASK):
					info->flash_id += FLASH_AM160T;
					break;
				case (AMD_ID_LV160B & FLASH_DEVICE_ID_MASK):
					info->flash_id += FLASH_AM160B;
					break;
				/* ID 0x7e MirrorBit family; has to read once more */
				case (AMD_ID_MIRROR & FLASH_DEVICE_ID_MASK):
					/* 2nd Cycle -- Device */
					tmp = (unsigned long) flash_read_uchar(info, 0xE);
					switch(tmp){
						case AMD_ID_LV320B_2:
							/* 3rd Cycle -- Boot */
							tmp = (unsigned long) flash_read_uchar(info, 0xF);
							switch(tmp){
								case 0:
									info->flash_id += FLASH_AMLV320B;
									break;
								case 1:
									info->flash_id += FLASH_AMLV320T;
									break;
							}
							break;
						case (AMD_ID_LV065M_2 & FLASH_DEVICE_ID_MASK):
							info->flash_id += FLASH_AMLV065M;
							break;
						default:
							break;
					}
					break;
				default:
					break;
			}
		default:
			break;
	}
	flash_write_cmd (info, 0, 0, info->cmd_reset);
#ifdef DEBUG
		flash_printqry (info, 0);
		debug ("flash_get_size: return\n");
#endif
return (info->size);
}


/*-----------------------------------------------------------------------
 */
static int flash_write_cfiword (flash_info_t * info, ulong dest,
				cfiword_t cword)
{

	cfiptr_t ctladdr;
	cfiptr_t cptr;
	int flag,retcode;

	ctladdr.cp = flash_make_addr (info, 0, 0);
	cptr.cp = (uchar *) dest;


	/* Check if Flash is (sufficiently) erased */
	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		flag = ((cptr.cp[0] & cword.c) == cword.c);
		break;
	case FLASH_CFI_16BIT:
		flag = ((cptr.wp[0] & cword.w) == cword.w);
		break;
	case FLASH_CFI_32BIT:
		flag = ((cptr.lp[0] & cword.l) == cword.l);
		break;
	case FLASH_CFI_64BIT:
		flag = ((cptr.llp[0] & cword.ll) == cword.ll);
		break;
	default:
		return 2;
	}
	if (!flag)
		return 2;

	/* Disable interrupts which might cause a timeout here */
	flag = disable_interrupts ();

	switch (info->vendor) {
	case CFI_CMDSET_INTEL_EXTENDED:
	case CFI_CMDSET_INTEL_STANDARD:
		flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
		flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
		break;
	case CFI_CMDSET_AMD_EXTENDED:
	case CFI_CMDSET_AMD_STANDARD:
		flash_unlock_seq (info, 0);
		switch(info->chipwidth){
		case FLASH_CFI_BY8:
			flash_write_cmd (info, 0, AMD_ADDR_START_BYTE, AMD_CMD_WRITE);
			break;
		default:
			flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
			break;
		}
		break;
	}

	switch (info->portwidth) {
	case FLASH_CFI_8BIT:
		cptr.cp[0] = cword.c;
		break;
	case FLASH_CFI_16BIT:
		cptr.wp[0] = cword.w;
		break;
	case FLASH_CFI_32BIT:
		cptr.lp[0] = cword.l;
		break;
	case FLASH_CFI_64BIT:
		cptr.llp[0] = cword.ll;
		break;
	}

	/* re-enable interrupts if necessary */
	if (flag)
		enable_interrupts ();

	retcode = flash_full_status_check (info, cptr, cword, info->write_tout, "write"); 
	return retcode;
//	return flag;
}

#ifdef CFG_FLASH_USE_BUFFER_WRITE

/* loop through the sectors from the highest address
 * when the passed address is greater or equal to the sector address
 * we have a match
 */
static flash_sect_t find_sector (flash_info_t * info, ulong addr)
{
	flash_sect_t sector;

	for (sector = info->sector_count - 1; sector >= 0; sector--) {
		if (addr >= info->start[sector])
			break;
	}
	return sector;
}

static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
				  int len)
{
	flash_sect_t sector;
	int cnt;
	int retcode;
	volatile cfiptr_t src;
	volatile cfiptr_t dst;
	/* buffered writes in the AMD chip set is not supported yet */
	if((info->vendor ==  CFI_CMDSET_AMD_STANDARD) ||
		(info->vendor == CFI_CMDSET_AMD_EXTENDED))
		return ERR_INVAL;

	src.cp = cp;
	dst.cp = (uchar *) dest;
	sector = find_sector (info, dest);
	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
	flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
	if ((retcode =
	     flash_status_check (info, sector, 0,0,info->buffer_write_tout,
				 "write to buffer")) == ERR_OK) {
		/* reduce the number of loops by the width of the port	*/
		switch (info->portwidth) {
		case FLASH_CFI_8BIT:
			cnt = len;
			break;
		case FLASH_CFI_16BIT:
			cnt = len >> 1;
			break;
		case FLASH_CFI_32BIT:
			cnt = len >> 2;
			break;
		case FLASH_CFI_64BIT:
			cnt = len >> 3;
			break;
		default:
			return ERR_INVAL;
			break;
		}
		flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
		while (cnt-- > 0) {
			switch (info->portwidth) {
			case FLASH_CFI_8BIT:
				*dst.cp++ = *src.cp++;
				break;
			case FLASH_CFI_16BIT:
				*dst.wp++ = *src.wp++;
				break;
			case FLASH_CFI_32BIT:
				*dst.lp++ = *src.lp++;
				break;
			case FLASH_CFI_64BIT:
				*dst.llp++ = *src.llp++;
				break;
			default:
				return ERR_INVAL;
				break;
			}
		}
		flash_write_cmd (info, sector, 0,
				 FLASH_CMD_WRITE_BUFFER_CONFIRM);
		retcode =
			flash_full_status_check (info, sector,0,0,
						 info->buffer_write_tout,
						 "buffer write");
	}
	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
	return retcode;
}
#endif /* CFG_FLASH_USE_BUFFER_WRITE */

